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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas el ectronics products li sted herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by rene sas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringeme nt of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electroni cs products or techni cal information descri bed in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyri ghts or other intell ectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any re nesas electronics product, wh ether in whole or in part . 4. descriptions of circuits, software and other related informat ion in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully re sponsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this doc ument, you should comply with the applicable export control laws and regulations and follow the proc edures required by such laws and re gulations. you should not use renesas electronics products or the technology described in this docum ent for any purpose relating to mil itary applicati ons or use by the military, including but not l imited to the development of weapons of mass de struction. renesas electronics products and technology may not be used for or incor porated into any products or systems whose manufacture, us e, or sale is prohibited under any applicable dom estic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing th e information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products ar e classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product de pends on the product?s quality grade, as indicated below. you must check the qua lity grade of each renesas electronics pr oduct before using it in a particular application. you may not use any renesas electronics produc t for any application categorized as ?speci fic? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. document no. u18329ej4v0ud00 (4th edition) date published august 2008 ns printed in japan 2007 pd78f0471 pd78f0481 pd78f0491 pd78f0472 pd78f0482 pd78f0492 pd78f0473 pd78f0483 pd78f0493 pd78f0474 pd78f0484 pd78f0494 pd78f0475 pd78f0485 pd78f0495 78k0/lf3 8-bit single-chip microcontrollers user?s manual user?s manual u18329ej4v0ud 2 [memo] user?s manual u18329ej4v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u18329ej4v0ud 4 eeprom is a trademark of nec electronics corporation. superflash is a registered trademark of silicon storage t echnology, inc. in several countries including the united states and japan. caution: this product uses superflash ? technology licensed from silicon storage technology, inc. the information in this document is current as of june, 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific": user?s manual u18329ej4v0ud 5 introduction readers this manual is intended for user engineer s who wish to understand the functions of the 78k0/lf3 and design and develop applicatio n systems and programs for these devices. the target products are as follows. 78k0/lf3: pd78f0471, 78f0472, 78f04 73, 78f0474, 78f0475, pd78f0481, 78f0482, 78f0 483, 78f0484, 78f0485, pd78f0491, 78f0492, 78f 0493, 78f0494, 78f0495 purpose this manual is intended to give users an understanding of the functions described in the organization below. organization the 78k0/lf3 manual is separated into two parts: this manual and the instructions edition (common to the 78k0 microcontrollers). 78k0/lf3 user?s manual (this manual) 78k/0 series user?s manual instructions ? pin functions ? internal block functions ? interrupts ? other on-chip peripheral functions ? electrical specifications ? cpu functions ? instruction set ? explanation of each instruction how to read this manual it is assumed that the readers of this ma nual have general knowledge of electrical engineering, logic circuits, and microcontrollers. ? to gain a general understanding of functions: read this manual in the order of the contents . the mark ? user?s manual u18329ej4v0ud 6 conventions data significance: higher digits on the left and lower digits on the right active low representations: (overscore over pin and signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representations: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pu blication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. 78k0/lf3 user?s manual this manual 78k/0 series instructions user?s manual u12326e 78k0 microcontrollers self progr amming library type01 user?s manual note u18274e 78k0 microcontrollers eeprom tm emulation library type01 user?s manual note u18275e note this document is under engineering mana gement. for details, consult an nec electronics sales representative . documents related to development tools (software) (user?s manuals) document name document no. operation u17199e language u17198e ra78k0 ver. 3.80 assembler package structured assembly language u17197e operation u17201e cc78k0 ver. 3.70 c compiler language u17200e id78k0-qb ver. 3.00 integrat ed debugger operation u18492e pm+ ver. 6.30 u18416e documents related to development tools (hardware) (user?s manuals) document name document no. qb-78k0lx3 in-circuit emulator u18511e qb-mini2 on-chip debug emulator with programming function u18371e documents related to fl ash memory programming document name document no. pg-fp5 flash memory programme u18865e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u18329ej4v0ud 7 other documents document name document no. semiconductor selection guide ? products and packages ? x13769x semiconductor device mount manual note quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device m ount manual? website (h ttp://www.necel.com/pkg/en/mount/index.html). caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document when designing. user?s manual u18329ej4v0ud 8 contents chapter 1 outline ........................................................................................................... ................. 17 1.1 features.................................................................................................................. ....................... 17 1.2 applications .............................................................................................................. .................... 18 1.3 ordering information...................................................................................................... .............. 19 1.4 pin configuration (top view) .............................................................................................. ........ 20 1.5 78k0/lx3 microcontro ller series lineup.................................................................................... 24 1.6 block diagram ............................................................................................................. ................. 28 1.7 outline of functions ( pd78f047x)............................................................................................ 29 1.8 outline of functions ( pd78f048x)............................................................................................ 32 1.9 outline of functions ( pd78f049x)............................................................................................ 35 chapter 2 pin functions .................................................................................................... ........... 38 2.1 pin function list ......................................................................................................... ................. 38 2.2 description of pin functions .............................................................................................. ........ 45 2.2.1 p10 to p17 (por t 1)..................................................................................................... ..................... 45 2.2.2 p20 to p27 (por t 2)..................................................................................................... ..................... 46 2.2.3 p30 to p34 (por t 3)..................................................................................................... ..................... 46 2.2.4 p40 to p47 (por t 4)..................................................................................................... ..................... 47 2.2.5 p80 to p83 (por t 8)..................................................................................................... ..................... 48 2.2.6 p90 to p93 (por t 9)..................................................................................................... ..................... 48 2.2.7 p100 to p103 (por t 10).................................................................................................. .................. 49 2.2.8 p110 to p113 (por t 11).................................................................................................. .................. 49 2.2.9 p120 to p124 (por t 12).................................................................................................. .................. 49 2.2.10 p130 to p133 ( port 13)................................................................................................. ................. 50 2.2.11 p140 to p143 ( port 14)................................................................................................. ................. 50 2.2.12 p150 to p153 ( port 15)................................................................................................. ................. 51 2.2.13 av ref ( pd78f048x and 78f 049x only)....................................................................................... 51 2.2.14 av ss ( pd78f048x and 78f 049x onl y) ........................................................................................ 51 2.2.15 com0 to com7 ........................................................................................................... ................. 51 2.2.16 v lc0 to v lc3 ............................................................................................................................... ..... 51 2.2.17 reset .................................................................................................................. ........................ 51 2.2.18 regc................................................................................................................... ......................... 52 2.2.19 v dd ............................................................................................................................... ................. 52 2.2.20 v ss ............................................................................................................................... ................. 52 2.2.21 flmd0 .................................................................................................................. ........................ 52 2.3 pin i/o circuits and recomme nded connection of unused pins .... ....................................... 53 chapter 3 cpu architecture ................................................................................................. ..... 57 3.1 memory space .............................................................................................................. ................ 57 3.1.1 internal progr am memory space ........................................................................................... .......... 69 3.1.2 internal dat a memory space.............................................................................................. .............. 71 3.1.3 special function register (sfr) area .................................................................................... ........... 71 3.1.4 data me mory addr essing .................................................................................................. .............. 72 user?s manual u18329ej4v0ud 9 3.2 processor registers ....................................................................................................... ............. 82 3.2.1 contro l regist ers....................................................................................................... ........................82 3.2.2 general-pur pose registers ............................................................................................... ................86 3.2.3 special functi on register s (sfrs)....................................................................................... ..............87 3.3 instruction address addressing . ........................................................................................... .... 93 3.3.1 relati ve addre ssing ..................................................................................................... ....................93 3.3.2 immedi ate addres sing.................................................................................................... ..................94 3.3.3 table indi rect addr essing............................................................................................... ..................95 3.3.4 regist er addre ssing ..................................................................................................... ....................95 3.4 operand address addressing .................................... ............................................................ .... 96 3.4.1 impli ed addre ssing...................................................................................................... .....................96 3.4.2 regist er addre ssing ..................................................................................................... ....................97 3.4.3 direct addre ssing ....................................................................................................... ......................98 3.4.4 short di rect addr essing ................................................................................................. ...................99 3.4.5 special function register (sfr ) addres sing.............................................................................. ......100 3.4.6 register i ndirect addr essi ng ............................................................................................ ..............101 3.4.7 based addre ssing ........................................................................................................ ..................102 3.4.8 based in dexed addr essing................................................................................................ .............103 3.4.9 stack addre ssing ........................................................................................................ ...................104 chapter 4 port functions ................................................................................................... ...... 105 4.1 port functions ............................................................................................................ ................ 105 4.2 port configuration ........................................................................................................ ............. 108 4.2.1 po rt 1 .................................................................................................................. ...........................109 4.2.2 po rt 2 .................................................................................................................. ...........................115 4.2.3 po rt 3 .................................................................................................................. ...........................117 4.2.4 po rt 4 .................................................................................................................. ...........................120 4.2.5 po rt 8 .................................................................................................................. ...........................123 4.2.6 po rt 9 .................................................................................................................. ...........................124 4.2.7 po rt 10 ................................................................................................................. ..........................125 4.2.8 po rt 11 ................................................................................................................. ..........................126 4.2.9 po rt 12 ................................................................................................................. ..........................129 4.2.10 po rt 13 ................................................................................................................ .........................133 4.2.11 po rt 14 ................................................................................................................ .........................134 4.2.12 po rt 15 ................................................................................................................ .........................135 4.3 registers controlling port functi on ....................................................................................... . 136 4.4 port function operations.................................................................................................. ........ 143 4.4.1 writi ng to i/o port..................................................................................................... ......................143 4.4.2 reading from i/o port ................................................................................................... .................143 4.4.3 operatio ns on i/o port .................................................................................................. .................143 4.5 settings of pfall, pf2, pf1, isc, port mode register, and output latch when using alternate function ............................................................................................................. ...... 143 chapter 5 clock generator .................................................................................................. .. 147 5.1 functions of clock generator.................................... .......................................................... ..... 147 5.2 configuration of clock genera tor .......................................................................................... .. 148 5.3 registers controlling clock generator ..................... .............................................................. 15 0 5.4 system clock oscillator ................................................................................................... ......... 161 user?s manual u18329ej4v0ud 10 5.4.1 x1 oscill ator........................................................................................................... .........................161 5.4.2 xt1 oscilla tor .......................................................................................................... .......................161 5.4.3 when subsystem clock is not us ed ........................................................................................ ........164 5.4.4 internal hi gh-speed os cillator .......................................................................................... ...............164 5.4.5 internal lo w-speed os cillator........................................................................................... ................164 5.4.6 pr escaler............................................................................................................... .........................164 5.5 clock generator operation ................................................................................................. ...... 165 5.6 controlling clock......................................................................................................... ............... 168 5.6.1 example of controlli ng high-speed syst em clock.......................................................................... ..168 5.6.2 example of controlling intern al high-speed osc illation clock...........................................................1 70 5.6.3 example of cont rolling subsyst em clock.................................................................................. .......172 5.6.4 example of controlling intern al low-speed osci llation clock ............................................................1 74 5.6.5 clocks supplied to cp u and periphera l hardw are.......................................................................... 174 5.6.6 cpu clock stat us transiti on diagr am ..................................................................................... .........175 5.6.7 condition before changing cpu clock and processi ng after changing cpu cl ock .........................180 5.6.8 time required for switchover of cpu clock and main system cl ock ...............................................181 5.6.9 conditions before clock osc illation is stopp ed .......................................................................... ......182 5.6.10 peripheral hardw are and sour ce clocks .................................................................................. .....183 chapter 6 16-bit timer/event counter 00 ........................................................................... 184 6.1 functions of 16-bit timer/even t counter 00 ........................................................................... 184 6.2 configuration of 16-bit time r/event counter 00..................................................................... 185 6.3 registers controlling 16-bit time r/event counter 00 ............................................................ 190 6.4 operation of 16-bit timer/event counter 00 ............. .............................................................. 199 6.4.1 interval timer oper ation ................................................................................................ ..................199 6.4.2 square wave output op eration ............................................................................................ ...........202 6.4.3 external event counter operatio n ........................................................................................ ...........205 6.4.4 operation in clear & start mode entered by ti 000 pin valid ed ge input..........................................209 6.4.5 free-runni ng timer oper ation............................................................................................ ..............222 6.4.6 ppg out put operat ion.................................................................................................... .................231 6.4.7 one-shot pul se output operatio n ......................................................................................... ...........234 6.4.8 pulse width m easurement operatio n ....................................................................................... .......239 6.4.9 external 24-bit ev ent counter operation ................................................................................. ........247 6.4.10 cautions for exter nal 24-bit ev ent counter ............................................................................. ......251 6.5 special use of tm00....................................................................................................... ............ 253 6.5.1 rewriting cr010 during tm00 operatio n ................................................................................... ....253 6.5.2 setting l vs00 and lvr00 ................................................................................................. ............253 6.6 cautions for 16-bit timer/event counter 00........... ................................................................. 255 chapter 7 8-bit timer/event counters 50, 51, and 52................................................... 260 7.1 functions of 8-bit timer/event counters 50, 51, and 52........................................................ 260 7.2 configuration of 8-bit timer/ event counters 50, 51, and 52 ................................................. 260 7.3 registers controlling 8-bit ti mer/event counters 50, 51, and 52 ......................................... 264 user?s manual u18329ej4v0ud 11 7.4 operations of 8-bit timer/even t counters 50, 51, and 52............... ....................................... 272 7.4.1 operation as interval timer............................................................................................. ................272 7.4.2 operation as ex ternal event count er ..................................................................................... .........274 7.4.3 square-wave output op eration ............................................................................................ ...........275 7.4.4 pwm out put operat ion .................................................................................................... ...............276 7.5 cautions for 8-bit timer/event counters 50, 51, and 52........................................................ 279 chapter 8 8-bit timers h0, h1, and h2.................................................................................. 282 8.1 functions of 8-bit timers h0, h1, and h2 ................ ............................................................... 282 8.2 configuration of 8-bit timers h0 , h1, and h2 ......................................................................... 282 8.3 registers controlling 8-bit timers h0, h1, and h2 .. .............................................................. 287 8.4 operation of 8-bit timers h0, h1 and h2.................. ............................................................... 29 4 8.4.1 operation as interv al timer/squar e-wave output .......................................................................... ..294 8.4.2 operatio n as pw m out put................................................................................................. .............297 8.4.3 carrier generator operat ion (8-bit ti mer h1 only) ....................................................................... ....303 8.4.4 control of number of ca rrier clocks by timer 51 count er................................................................. 310 chapter 9 real-time counter ................................................................................................ .. 311 9.1 functions of real-time counter................................ ............................................................ ... 311 9.2 configuration of real-time counter ......................... ............................................................... 311 9.3 registers controlling real-time counter ............................................................................... 313 9.4 real-time counter operation .................................... ........................................................... .... 327 9.4.1 starting operation of real-tim e coun ter................................................................................. ..........327 9.4.2 shifting to stop m ode after starti ng operat ion .......................................................................... ...328 9.4.3 reading/writi ng real-tim e count er ....................................................................................... ...........329 9.4.4 setting alarm of real-tim e count er ...................................................................................... ............331 9.4.5 1 hz output of real-tim e counter........................................................................................ .............332 9.4.6 32.768 khz output of real-tim e coun ter .................................................................................. ........332 9.4.7 512 hz, 16.384 khz out put of real-t ime c ounter .......................................................................... ...333 9.4.8 example of watch error co rrection of real -time co unter.................................................................. 334 chapter 10 watchdog timer .................................................................................................. ... 339 10.1 functions of watchdog timer .................................. ............................................................ .. 339 10.2 configuration of watchdog time r .......................................................................................... 340 10.3 register controlling watchdog time r ................................................................................... 341 10.4 operation of watchdog timer................................... ........................................................... ... 342 10.4.1 controlling oper ation of wa tchdog ti mer................................................................................ .......342 10.4.2 setting overflow time of wa tchdog ti mer ................................................................................ ......343 10.4.3 setting window open pe riod of watc hdog ti mer........................................................................... .344 chapter 11 clock output/buzzer output controller............................................... 346 11.1 functions of clock output/buzze r output controller ....................... ................................... 346 11.2 configuration of clock output /buzzer output controller ................................................... 347 11.3 registers controlling clock output/buzzer output controller........................................... 347 11.4 operations of clock output/b uzzer output controller ........................................................ 350 11.4.1 operation as clock output .............................................................................................. ..............350 11.4.2 operation as buzzer output............................................................................................. .............350 user?s manual u18329ej4v0ud 12 chapter 12 10-bit successive appr oximation type a/d converter ( pd78f048x and 78f049x only) ................................................................................................................ 35 1 12.1 function of 10-bit successive approximation type a/d converte r................................... 351 12.2 configuration of 10-bit successive approxim ation type a/d converter .......................... 352 12.3 registers used in 10-bit successive approxim ation type a/d converter ........................ 354 12.4 10-bit successive approximati on type a/d converter operations ................................... 362 12.4.1 basic operations of a/d c onverter...................................................................................... ..........362 12.4.2 input voltage and conversion results................................................................................... .........364 12.4.3 a/d converte r operati on mode ........................................................................................... ..........365 12.5 how to read successive approximation type a/d converter characteristics table ...... 367 12.6 cautions for 10-bit successive approximation type a/d converter.................................... 369 chapter 13 16-bit ? type a/d converter ( pd78f049x only) ............................................ 373 13.1 function of 16-bit ? type a/d converter............................................................................. 373 13.2 configuration of 16-bit ? type a/d converter .................................................................... 374 13.3 registers used in 16-bit ? type a/d converter.................................................................. 376 13.4 circuit configurat ion example of 16-bit ? type a/d converter ........................................ 386 13.5 16-bit ? type a/d converter operations ............................................................................. 387 13.5.1 basic operations of 16-bit ? type a/d conv erter .........................................................................387 13.5.2 operation mode of 16-bit ? type a/d conv erter ..........................................................................387 13.6 how to read ? type a/d converter characteristics table . ............................................... 390 13.7 cautions for 16-bit ? type a/d converter ........................................................................... 394 chapter 14 serial interface uart0 ...................................................................................... 397 14.1 functions of serial interface uart0 ........................ .............................................................. 397 14.2 configuration of serial inte rface uart0 ............................................................................... 398 14.3 registers controlling serial interface uart0......... .............................................................. 401 14.4 operation of serial interface uart0 ........................ .............................................................. 407 14.4.1 operat ion stop mode.................................................................................................... ................407 14.4.2 asynchronous serial interface (u art) mode .............................................................................. .408 14.4.3 dedicated ba ud rate g enerat or.......................................................................................... ...........414 14.4.4 calculation of baud rate ....................................................................................................... ........415 chapter 15 serial interface uart6 ...................................................................................... 419 15.1 functions of serial interface uart6 ........................ .............................................................. 419 15.2 configuration of serial inte rface uart6 ............................................................................... 423 15.3 registers controlling serial interface uart6......... .............................................................. 426 15.4 operation of serial interface uart6 ........................ .............................................................. 437 15.4.1 operat ion stop mode.................................................................................................... ................437 15.4.2 asynchronous serial interface (u art) mode .............................................................................. .438 15.4.3 dedicated ba ud rate g enerat or.......................................................................................... ...........452 15.4.4 calculation of baud rate ....................................................................................................... ........454 chapter 16 serial interface csi10 ........................................................................................ 4 60 16.1 functions of serial interface csi10 ....................... ............................................................... .. 460 16.2 configuration of serial inte rface csi10 ................................................................................. 4 60 user?s manual u18329ej4v0ud 13 16.3 registers controlling serial interface csi10.......... ............................................................... 462 16.4 operation of serial interface csi10 ...................... ................................................................ .. 466 16.4.1 operat ion stop mode .................................................................................................... ...............466 16.4.2 3-wire se rial i/o mode................................................................................................. .................466 chapter 17 serial interface csia0 ....................................................................................... 47 6 17.1 functions of serial interface csia0 .............................. ......................................................... 476 17.2 configuration of serial interface csia0................................................................................. 477 17.3 registers controlling serial interfac e csia0 ........................................................................ 479 17.4 operation of serial interface csia0 ........................... ............................................................ 488 17.4.1 operation st op m ode ............................................................................................................ .......488 17.4.2 3-wire serial i/o mode ......................................................................................................... .........489 17.4.3 3-wire serial i/o mode with automati c transmit/receive functi on ..................................................494 chapter 18 lcd controller/driver....................................................................................... 509 18.1 functions of lcd controller/driver ......................... .............................................................. 509 18.2 configuration of lcd controller/driver ................... .............................................................. 51 1 18.3 registers controlling lcd controller/driver .......... .............................................................. 513 18.4 setting lcd controller/driver .................................. .......................................................... ..... 521 18.4.1 setting method when not using s egment key scan func tion (kson = 0).....................................521 18.4.2 setting method when using segm ent key scan functi on (kson = 1)...........................................522 18.5 lcd display data memory .................................................................................................. .... 524 18.6 common and segment signals .............................................................................................. 5 25 18.7 display modes ............................................................................................................ .............. 535 18.7.1 static di splay ex ample ................................................................................................. ................535 18.7.2 two-time-slic e display example ......................................................................................... ..........538 18.7.3 three-time-slic e display example....................................................................................... ..........543 18.7.4 four-time-slic e display example ........................................................................................ ..........551 18.7.5 eight-time-slic e display example....................................................................................... ...........556 18.8 operation of segment key scan function ............................................................................ 561 18.8.1 circuit conf iguration example.......................................................................................... .............561 18.8.2 example of proc edure for using segment key scan fu nction ........................................................562 18.9 cautions when using segment key scan function ............................................................ 565 18.10 supplying lcd drive voltages v lc0 , v lc1 , v lc2 , and v lc3 .................................................. 567 18.10.1 internal resist ance divisi on met hod................................................................................... .........567 18.10.2 external resist ance divisi on met hod................................................................................... ........569 chapter 19 manchester code generator ......................................................................... 571 19.1 functions of manchester code ge nerator ............................................................................ 571 19.2 configuration of manchester c ode generator...................................................................... 571 19.3 registers controlling manchester code generator ............................................................. 574 19.4 operation of manchester code generator ............................................................................ 577 19.4.1 operat ion stop mode .................................................................................................... ...............577 19.4.2 manchester code genera tor mode ......................................................................................... ......578 19.4.3 bit sequent ial buffe r mode ............................................................................................. ..............587 user?s manual u18329ej4v0ud 14 chapter 20 remote controller receiver ......................................................................... 596 20.1 remote controller receiver functions........................ .......................................................... 596 20.2 remote controller receiver co nfiguration ........................................................................... 596 20.3 registers to control remote controller receiver ................................................................ 604 20.4 operation of remote controll er receiver ............................................................................. 607 20.4.1 format of ty pe a recept ion mode ........................................................................................ .........607 20.4.2 operation flow of type a rec eption mode ................................................................................ .....607 20.4.3 format of type b receptio n mode ................................................................................................ .609 20.4.4 operation flow of type b rec eption mode ................................................................................ .....609 20.4.5 format of ty pe c recept ion mode........................................................................................ .........611 20.4.6 operation flow of type c rec eption mode ................................................................................ .....611 20.4.7 timi ng ................................................................................................................. .........................613 20.4.8 compare r egister setting............................................................................................... ...............617 20.4.9 error interrupt generati on timing...................................................................................... .............619 20.4.10 noise eliminat ion..................................................................................................... ...................625 chapter 21 interrupt functions ............................................................................................ 6 28 21.1 interrupt function types ................................................................................................. ........ 628 21.2 interrupt sources and configur ation ..................................................................................... 6 28 21.3 registers controlling interrupt functions............................................................................. 633 21.4 interrupt servicing operat ions ........................................................................................... .... 641 21.4.1 maskable interr upt acknow ledgment...................................................................................... ......641 21.4.2 software interrupt request ack nowledg ment .............................................................................. ..643 21.4.3 multiple in terrupt se rvicing ........................................................................................... ................644 21.4.4 interrupt request hold ................................................................................................. ..................647 chapter 22 key interrupt function ..................................................................................... 648 22.1 functions of key interrupt ............................................................................................... ....... 648 22.2 configuration of key interrupt .................................. ......................................................... ..... 648 22.3 register controlling key interrupt ........................... ............................................................ .. 649 chapter 23 standby function ................................................................................................ .. 650 23.1 standby function and co nfiguration ..................................................................................... 65 0 23.1.1 standby func tion ....................................................................................................... ...................650 23.1.2 registers contro lling standby function................................................................................. .........651 23.2 standby function operation ............................................................................................... .... 653 23.2.1 ha lt m ode .............................................................................................................. ....................653 23.2.2 st op m ode .............................................................................................................. ...................658 chapter 24 reset function.................................................................................................. ...... 664 24.1 register for confirming reset source ......................... .......................................................... 67 3 user?s manual u18329ej4v0ud 15 chapter 25 power-on-clear circuit ..................................................................................... 674 25.1 functions of power-on-clear circuit ....................... .............................................................. 6 74 25.2 configuration of power-on-clear circuit ............................................................................... 675 25.3 operation of power-on-clear circuit....................... ............................................................... 675 25.4 cautions for power-on-clear circuit ....................... ............................................................... 678 chapter 26 low-voltage detector ....................................................................................... 680 26.1 functions of low-voltage detector ........................... ............................................................ 6 80 26.2 configuration of low-voltage de tector ................................................................................. 681 26.3 registers controlling low-voltage detector .......... .............................................................. 681 26.4 operation of low-voltage detector.......................... .............................................................. 684 26.4.1 when us ed as re set ..................................................................................................... ................685 26.4.2 when used as interrupt................................................................................................. ...............690 26.5 cautions for low-voltage detector .......................... .............................................................. 695 chapter 27 option byte..................................................................................................... .......... 698 27.1 functions of option bytes .................................... ............................................................ ...... 698 27.2 format of option byte .................................................................................................... ......... 700 chapter 28 flash memory.................................................................................................... ...... 703 28.1 internal memory size switching register............... ............................................................... 703 28.2 internal expansion ram size switching register .. .............................................................. 704 28.3 writing with flash memory pr ogrammer............................................................................... 705 28.4 programming environment.................................................................................................. ... 708 28.5 communication mode....................................................................................................... ....... 708 28.6 connection of pins on board.............................................................................................. .... 710 28.6.1 fl md0 pin .............................................................................................................. .....................710 28.6.2 serial interfac e pins .................................................................................................. ...................710 28.6.3 r eset pin .............................................................................................................. .....................712 28.6.4 po rt pins.............................................................................................................. .........................712 28.6.5 re gc pin............................................................................................................... ......................712 28.6.6 other signal pins ...................................................................................................... ....................712 28.6.7 powe r suppl y ........................................................................................................... ....................712 28.7 programming method ....................................................................................................... ....... 713 28.7.1 controlli ng flash memory ............................................................................................... ..............713 28.7.2 flash memory programmi ng mode .......................................................................................... ....713 28.7.3 selecting communicati on mode ........................................................................................... ........714 28.7.4 communi cation co mmands ................................................................................................. ........715 28.8 security settings........................................................................................................ .............. 716 28.9 processing time for each command when pg-f p5 is used (reference) ........................ 718 28.10 flash memory programming by self-programming .. ......................................................... 721 28.10.1 boot swap func tion.................................................................................................... .................729 user?s manual u18329ej4v0ud 16 chapter 29 on-chip debug function ..................................................................................... 731 29.1 connecting qb-mini2 to 78k0/lf3 .................................... ..................................................... 731 29.2 reserved area used by qb-mini2 .......................................................................................... 732 chapter 30 instruction set................................................................................................. ...... 733 30.1 conventions used in operation list ........................ .............................................................. 7 33 30.1.1 operand identifiers and specificat ion me thods.......................................................................... ...733 30.1.2 description of operation column........................................................................................ ...........734 30.1.3 description of flag operati on colu mn ................................................................................... .........734 30.2 operation list ........................................................................................................... ................ 735 30.3 instructions listed by addressing type...................... .......................................................... 743 chapter 31 electrical specifications (standard products) .................................. 746 chapter 32 package drawings ................................................................................................ 770 chapter 33 recommended soldering conditions........................................................... 772 chapter 34 cautions for wait.............................................................................................. ... 773 34.1 cautions for wait........................................................................................................ .............. 773 34.2 peripheral hardware that gene rates wait ............................................................................ 774 appendix a development tools............................................................................................... 775 a.1 software package .......................................................................................................... ............ 778 a.2 language processing software ....................................... ....................................................... . 778 a.3 control software .......................................................................................................... .............. 779 a.4 flash memory writing tools................................................................................................ ..... 780 a.4.1 when using flash memory programmer pg-fp5 and fl-p r5....................................................... 780 a.4.2 when using on-chip debug emulator with programm ing function qb-mini2 .................................780 a.5 debugging tools (hardware)............................................ .................................................... .... 781 a.5.1 when using in-circu it emulator qb-78k0lx3............................................................................... ..781 a.5.2 when using on-chip debug emulator with programm ing function qb-mini2 .................................782 a.6 debugging tools (software)................................................ ................................................ ..... 782 appendix b revision history ................................................................................................ ..... 783 b.1 major revisions in this edition ........................................................................................... .... 783 b.2 revision history up to previous editions ................. .............................................................. 786 user?s manual u18329ej4v0ud 17 chapter 1 outline 1.1 features { minimum instruction execution time can be changed from high speed (0.2 s: @ 10 mhz operation with high- speed system clock) to ultra low-speed (122 s: @ 32.768 khz operation with subsystem clock) { general-purpose register: 8 bits 32 registers (8 bits 8 registers 4 banks) { rom, ram capacities data memory item part number program memory (rom) internal high- speed ram note 1 internal expansion ram note 1 lcd display ram pd78f0471, 78f0481, 78f0491 16 kb 768 bytes pd78f0472, 78f0482, 78f0492 24 kb pd78f0473, 78f0483, 78f0493 32 kb ? pd78f0474, 78f0484, 78f0494 48 kb pd78f0475, 78f0485, 78f0495 flash memory note 1 60 kb 1 kb 1 kb < pd78f047x, 78f048x> 40 4 bits (36 8 bits) [36 4 bits (32 8 bits) ] note 2 < pd78f049x> 32 4 bits (28 8 bits) [28 4 bits (24 8 bits) ] note 2 notes 1. the internal flash memory, internal high-spee d ram capacities, and internal expansion ram capacities can be changed using the internal memory size switching register (ims) and the internal expansion ram size switching register (ixs). 2. the items in parentheses are applicable when 8com is used. the items in square brackets are applicable when using the uart6 pins (rxd6, txd6) on the bottom side. { on-chip single-power-supply flash memory { self-programming (with boot swap function) { on-chip debug function { on-chip power-on-clear (poc) circuit and low-voltage detector (lvi) { on-chip watchdog timer (operable with internal low-speed oscillation clock) { lcd controller/driver (external resistance division and internal resistance division are switchable) pd78f047x: segment signals: 36, common signals: 8 (1/4 bias) : segment signals: 40, common signals: 4 (1/3 bias) : segment signals: 40, common signals: 3 (1/3, 1/2 bias) : segment signals: 40, common signals: 2 (1/2 bias) : segment signals: 40, common signals: 1 (static) pd78f048x: segment signals: 36, common signals: 8 (1/4 bias) : segment signals: 40, common signals: 4 (1/3 bias) : segment signals: 40, common signals: 3 (1/3, 1/2 bias) : segment signals: 40, common signals: 2 (1/2 bias) : segment signals: 40, common signals: 1 (static) pd78f049x: segment signals: 28, common signals: 8 (1/4 bias) : segment signals: 32, common signals: 4 (1/3 bias) : segment signals: 32, common signals: 3 (1/3, 1/2 bias) : segment signals: 32, common signals: 2 (1/2 bias) : segment signals: 32, common signals: 1 (static) chapter 1 outline user?s manual u18329ej4v0ud 18 { on-chip segment key scan function: 8 channels { on-chip key interrupt function: 8 channels { on-chip clock output/buzzer output controller { i/o ports: 62 { timer: 9 channels ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 3 channels ? 8-bit timer: 3 channels ? real-time counter (rtc): 1 channel ? watchdog timer: 1 channel { serial interface: 3 channels ? uart (lin (local interconnect network)-bus supported): 1 channel ? csi/uart note : 1 channel ? csi with automatic transmit/r eceive function: 1 channel note select either of the functions of these alternate-function pins. { 16-bit ? type a/d converter note : 3 channels ( pd78f049x only) { 10-bit successive approximation type a/d converter: 8 channels ( pd78f048x and 78f049x only) { remote controller receiver { manchester code generator { power supply voltage: v dd = 1.8 to 5.5 v { operating ambient temperature: t a = ? 40 to +85 c note the specifications of the 16-bit ? a/d converter may have been changed. for details of the specifications , contact an nec electronics sales representative or authorized dealer. 1.2 applications digital cameras, av equipments, household electrical app liances, utility meters, health care equipments, and measurement equipment, etc. chapter 1 outline user?s manual u18329ej4v0ud 19 1.3 ordering information ? flash memory version (lead-free products) part number package pd78f0471gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0472gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0473gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0474gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0475gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0471gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0472gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0473gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0474gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0475gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0481gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0482gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0483gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0484gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0485gc-gad-ax 80-pin plastic lqfp (14 14) pd78f0481gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0482gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0483gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0484gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0485gk-gak-ax 80-pin plasti c lqfp (fine pitch) (12 12) pd78f0491gc-gad-ax note 80-pin plastic lqfp (14 14) pd78f0492gc-gad-ax note 80-pin plastic lqfp (14 14) pd78f0493gc-gad-ax note 80-pin plastic lqfp (14 14) pd78f0494gc-gad-ax note 80-pin plastic lqfp (14 14) pd78f0495gc-gad-ax note 80-pin plastic lqfp (14 14) pd78f0491gk-gak-ax note 80-pin plastic lqfp (fine pitch) (12 12) pd78f0492gk-gak-ax note 80-pin plastic lqfp (fine pitch) (12 12) pd78f0493gk-gak-ax note 80-pin plastic lqfp (fine pitch) (12 12) pd78f0494gk-gak-ax note 80-pin plastic lqfp (fine pitch) (12 12) pd78f0495gk-gak-ax note 80-pin plastic lqfp (fine pitch) (12 12) note under development chapter 1 outline user?s manual u18329ej4v0ud 20 1.4 pin configuration (top view) (1) pd78f0471, 78f0472, 78f 0473, 78f0474, 78f0475 ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p10/pcl p120/intp0/exlvi p47/kr7 p46/kr6 p45/kr5 p44/kr4/ti50/to50 p43/kr3/ti51/to51 p42/kr2 p41/kr1/rin p40/kr0/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk/ocd0b p121/x1/ocd0a regc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p11/sck10 p12/si10/rxd0 p13/so10/txd0 p14/scka0/intp4 p15/sia0/ chapter 1 outline user?s manual u18329ej4v0ud 21 (2) pd78f0481, 78f0482, 78f 0483, 78f0484, 78f0485 ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p10/pcl p120/intp0/exlvi p47/kr7 p46/kr6 p45/kr5 p44/kr4/ti50/to50 p43/kr3/ti51/to51 p42/kr2 p41/kr1/rin p40/kr0/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk/ocd0b p121/x1/ocd0a regc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 av ss av ref com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 p80/seg4 p81/seg5 p82/seg6 p83/seg7 p90/seg8 p91/seg9 p92/seg10 p93/seg11 p100/seg12 p101/seg13 p11/sck10 p12/si10/rxd0 p13/so10/txd0 p14/scka0/intp4 p15/sia0/ chapter 1 outline user?s manual u18329ej4v0ud 22 (3) pd78f0491, 78f0492, 78f 0493, 78f0494, 78f0495 ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p10/pcl p120/intp0/exlvi p47/kr7 p46/kr6 p45/kr5 p44/kr4/ti50/to50 p43/kr3/ti51/to51 p42/kr2 p41/kr1/rin p40/kr0/v lc3 v lc2 v lc1 v lc0 reset p124/xt2 p123/xt1 flmd0 p122/x2/exclk/ocd0b p121/x1/ocd0a regc 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 av ss av ref com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 p80/seg4 p81/seg5 p82/seg6 p83/seg7 p90/seg8 p91/seg9 p92/seg10 p93/seg11 p100/seg12 p101/seg13 p11/sck10 p12/si10/rxd0 p13/so10/txd0 p14/scka0/intp4 p15/sia0/ chapter 1 outline user?s manual u18329ej4v0ud 23 pin identification ani0 to ani7 note 1 : analog input av ref note 1 : analog reference voltage av ss note 1 : analog ground buz: buzzer output com0 to com7: common output ds0+ to ds2+ note 2 : ? analog input (+) ds0 ? to ds2 ? note 2 : ? analog input ( ? ) exclk: external clock input (main system clock) exlvi: external potential input for low-voltage detector flmd0: flash programming mode intp0 to intp5: external interrupt input kr0 to kr7: key return mcgo: manchester code generator output ocd0a, ocd0b: on chip debug input/output p10 to p17: port 1 p20 to p27: port 2 p30 to p34: port 3 p40 to p47: port 4 p80 to p83: port 8 p90 to p93: port 9 p100 to p103: port 10 p110 to p113: port 11 p120 to p124: port 12 p130 to p133: port 13 p140 to p143: port 14 p150 to p153: port 15 pcl: programmable clock output regc regulator capacitance reset: reset rxd0, rxd6: receive data ref+ note 2 : ? analog reference voltage (+) ref ? note 2 : ? analog reference voltage ( ? ) rin: remote control input rtc1hz: real-time counter correction clock (1 hz) output rtccl: real-time counter clock (32.768 khz original oscillation) output rtcdiv: real-time counter clock (32.768 khz divided frequency) output seg0 to seg31: segment output seg32 to seg39 note 3 : segment output seg24 (ks0) to seg31 (ks7): segment key scan sck10: serial clock input/output scka0: serial clock input/output si10: serial data input sia0: serial data input so10: serial data output soa0: serial data output ti000, ti010: timer input ti50, ti51, ti52: timer input to00: timer output to50, to51: timer output toh0, toh1: timer output txd0, txd6: transmit data v dd : power supply v ss : ground v lc0 to v lc3 : lcd power supply x1, x2: crystal oscillator (main system clock) xt1, xt2: crystal oscillator (subsystem clock) notes 1. pd78f048x and 78f049x only. 2. pd78f049x only. 3. pd78f047x and 78f048x only. chapter 1 outline user?s manual u18329ej4v0ud 24 1.5 78k0/lx3 microcontroller series lineup 78k0/lc3 78k0/ld3 78k0/le3 78k0/lf3 rom ram 48 pins 52 pins 64 pins 80 pins 60 kb 2 kb ? ? pd78f0465 pd78f0455 pd78f0445 pd78f0495 pd78f0485 pd78f0475 48 kb 2 kb ? ? pd78f0464 pd78f0454 pd78f0444 pd78f0494 pd78f0484 pd78f0474 32 kb 1 kb pd78f0413 pd78f0403 pd78f0433 pd78f0423 pd78f0463 pd78f0453 pd78f0443 pd78f0493 pd78f0483 pd78f0473 24 kb 1 kb pd78f0412 pd78f0402 pd78f0432 pd78f0422 pd78f0462 pd78f0452 pd78f0442 pd78f0492 pd78f0482 pd78f0472 16 kb 768 b pd78f0411 pd78f0401 pd78f0431 pd78f0421 pd78f0461 pd78f0451 pd78f0441 pd78f0491 pd78f0481 pd78f0471 8 kb 512 b pd78f0410 pd78f0400 pd78f0430 pd78f0420 ? ? chapter 1 outline user?s manual u18329ej4v0ud 25 the list of functions in the 78k0/lx3 mi crocontrollers is shown below. (1/3) 78k0/lc3 78k0/ld3 pd78f040x pd78f041x pd78f042x pd78f043x part number item 48 pins 52 pins flash memory (kb) 8 16 24 32 8 16 24 32 8 16 24 32 8 16 24 32 ram (kb) 0.5 0.75 1 1 0.5 0.75 1 1 0.5 0.75 1 1 0.5 0.75 1 1 power supply voltage v dd = 1.8 to 5.5 v regulator provided minimum instruction execution time 0.2 s (10 mhz: v dd = 2.7 to 5.5 v)/ 0.4 s (5 mhz: v dd = 1.8 to 5.5 v) high-speed system clock 10 mhz: v dd = 2.7 to 5.5 v/5 mhz: v dd = 1.8 to 5.5 v main internal high-speed oscillation clock 8 mhz (typ.): v dd = 1.8 to 5.5 v subclock 32.768 khz (typ.): v dd = 1.8 to 5.5 v clock internal low-speed oscillation clock 240 khz (typ.): v dd = 1.8 to 5.5 v port total 30 34 16 bits (tm0) 1 ch 8 bits (tm5) 3 ch 8 bits (tmh) 3 ch rtc 1 ch timer wdt 1 ch 3-wire csi ? 1 ch note 1 uart 1 ch 1 ch note 1 serial interface uart supporting lin- bus 1 ch note 2 1 ch note 3 type external resistance division and intern al resistance division are switchable. segment signal 22 (18) [20 (16)] note 4, 5 24 (20) [21 (17)] note 4, 5 lcd common signal 4 (8) note 4 10-bit successive approximation type a/d ? 6 ch ? 6 ch 16-bit ? type a/d ? external 5 interrupt internal 17 18 19 20 segment key source signal output 8 ch 8 ch key interrupt 3 ch 5 ch reset pin provided poc 1.59 v 0.15 v (time for rising up to 1.8 v : 3.6 ms (max.)) lvi the detection level of the supply voltage is selectable in 16 steps. reset wdt provided clock output ? buzzer output provided remote controller receiver ? provided mcg provided on-chip debug function provided operating ambient temperature t a = ? 40 to +85 c notes 1. since 3-wire csi and uart are used as alternate-function pins, they must be assigned to either of the functions for use. 2. the lin-bus supporting uart pins can be changed to the uart pins (pin numbers 47 and 48). 3. the lin-bus supporting uart pins can be changed to the 3-wire csi/uart pins (pin numbers 50 and 51). 4. the values in parentheses are the number of signal outputs when 8com is used. 5. the values in square brackets are the number of signal outputs when using the uart6 pins (rxd6, txd6) on the bottom side. chapter 1 outline user?s manual u18329ej4v0ud 26 (2/3) 78k0/le3 pd78f044x pd78f045x pd78f046x part number item 64 pins flash memory (kb) 16 24 32 48 60 16 24 32 48 60 16 24 32 48 60 ram (kb) 0.75 1 1 2 2 0.75 1 1 2 2 0.75 1 1 2 2 power supply voltage v dd = 1.8 to 5.5 v regulator provided minimum instruction execution time 0.2 s (10 mhz: v dd = 2.7 to 5.5 v)/ 0.4 s (5 mhz: v dd = 1.8 to 5.5 v) high-speed system clock 10 mhz: v dd = 2.7 to 5.5 v/5 mhz: v dd = 1.8 to 5.5 v main internal high-speed oscillation clock 8 mhz (typ.): v dd = 1.8 to 5.5 v subclock 32.768 khz (typ.): v dd = 1.8 to 5.5 v clock internal low-speed oscillation clock 240 khz (typ.): v dd = 1.8 to 5.5 v port total 46 16 bits (tm0) 1 ch 8 bits (tm5) 3 ch 8 bits (tmh) 3 ch rtc 1 ch timer wdt 1 ch 3-wire csi/uart note 1 1 ch serial interface uart supporting lin- bus note 2 1 ch type external resistance division and intern al resistance division are switchable. segment signal 32 (28) [28 (24)] note 3, 4 24 (20) [20 (16)] note 3, 4 lcd common signal 4 (8) note 3 10-bit successive approximation type a/d ? 8 ch 16-bit ? type a/d ? 3 ch external 6 interrupt internal 19 20 21 segment key source signal output 8 ch key interrupt 5 ch reset pin provided poc 1.59 v 0.15 v (time for rising up to 1.8 v : 3.6 ms (max.)) lvi the detection level of the supply voltage is selectable in 16 steps. reset wdt provided clock output ? buzzer output provided remote controller receiver provided mcg provided on-chip debug function provided operating ambient temperature t a = ? 40 to +85 c notes 1. select either of the functions of these alternate-function pins. 2. the lin-bus supporting uart pins can be changed to the 3-wire csi/uart pins (pin numbers 62 and 63). 3. the values in parentheses are the number of signal outputs when 8com is used. 4. the values in square brackets are the number of signal outputs when using the uart6 pins (rxd6, txd6) on the bottom side. chapter 1 outline user?s manual u18329ej4v0ud 27 (3/3) 78k0/lf3 pd78f047x pd78f048x pd78f049x part number item 80 pins flash memory (kb) 16 24 32 48 60 16 24 32 48 60 16 24 32 48 60 ram (kb) 0.75 1 1 2 2 0.75 1 1 2 2 0.75 1 1 2 2 power supply voltage v dd = 1.8 to 5.5 v regulator provided minimum instruction execution time 0.2 s (10 mhz: v dd = 2.7 to 5.5 v)/ 0.4 s (5 mhz: v dd = 1.8 to 5.5 v) high-speed system clock 10 mhz: v dd = 2.7 to 5.5 v/5 mhz: v dd = 1.8 to 5.5 v main internal high-speed oscillation clock 8 mhz (typ.): v dd = 1.8 to 5.5 v subclock 32.768 khz (typ.): v dd = 1.8 to 5.5 v clock internal low-speed oscillation clock 240 khz (typ.): v dd = 1.8 to 5.5 v port total 62 16 bits (tm0) 1 ch 8 bits (tm5) 3 ch 8 bits (tmh) 3 ch rtc 1 ch timer wdt 1 ch 3-wire csi/uart note 1 1 ch automatic transmit/ receive 3-wire csi 1 ch serial interface uart supporting lin- bus note 2 1 ch type external resistance division and intern al resistance division are switchable. segment signal 40 (36) [36 (32)] note 3, 4 32 (28) [28 (24)] note 3, 4 lcd common signal 4 (8) note 3 10-bit successive approximation type a/d ? 8 ch 16-bit ? type a/d ? 3 ch external 7 interrupt internal 20 21 22 segment key source signal output 8 ch key interrupt 8 ch reset pin provided poc 1.59 v 0.15 v (time for rising up to 1.8 v : 3.6 ms (max.)) lvi the detection level of the supply voltage is selectable in 16 steps. reset wdt provided clock output/ buzzer output provided remote controller receiver provided mcg provided on-chip debug function provided operating ambient temperature t a = ? 40 to +85 c notes 1. select either of the functions of these alternate-function pins. 2. the lin-bus supporting uart pins can be changed to the automatic transmit/receive 3-wire csi/uart pins (pin numbers 75 and 76). 3. the values in parentheses are the number of signal outputs when 8com is used. 4. the values in square brackets are the number of signal outputs when using the uart6 pins (rxd6, txd6) on the bottom side. chapter 1 outline user?s manual u18329ej4v0ud 28 1.6 block diagram flmd0 port 14 p140 to p143 4 port 15 p150 to p153 4 buzzer output buz/p33 clock output control segment key scan pcl/p10 manchester code generator mcgo/p32 rtcdiv/rtccl/p33 rtc1hz/p34 rin/p41 voltage regulator regc ani0/p20 to ani7/p27 interrupt control 8 av ref av ss internal high-speed ram internal expansion ram 78k/0 cpu core flash memory toh1/p31 8-bit timer h0 toh0/p32 8-bit timer h2 8-bit timer h1 ti50/to50/p44 8-bit timer/ event counter 50 rxd0/p12 txd0/p13 serial interface uart0 watchdog timer rxd6/p113 txd6/p112 rxd6/p15 txd6/p16 serial interface uart6 ti51/to51/p43 8-bit timer/ event counter 51 ti52/p34 8-bit timer/ event counter 52 serial interface csi10 so10/p13 si10/p12 sck10/p11 16-bit timer/ event counter 00 to00/ti010/p34 ti000/p33 power on clear/ low voltage indicator poc/lvi control reset control key return 8 kr0/p40 to kr7/p47 exlvi/p120 system control reset x1/p121 x2/exclk/p122 internal high-speed oscillator xt1/p123 xt2/p124 on-chip debug linsel port 1 p10 to p17 port 2 p20 to p27 8 port 3 p30 to p34 5 port 4 port 8 8 port 9 p90 to p93 4 port 10 p100 to p103 port 11 p110 to p113 port 12 4 p40 to p47 8 p80 to p83 4 port 13 p130 to p133 4 4 serial interface csia0 soa0/p16 sia0/p15 scka0/p14 ocd0a/x1 ocd0b/x2 lcd controller driver com0 to com7 8 seg24(ks0)-seg31(ks7) 8 ram space for lcd data 16-bit a/d converter note1 10-bit a/d converter note2 seg32 to seg39 note3 seg0 to seg31 v ss v dd v lc0 to v lc3 internal low-speed oscillator remote control signal receiver real time counter temperature sensor intp0/p120 intp1/p34 intp2/p33 intp3/p31 intp5/p30 rxd6/p113, rxd6/p15 (linsel) intp4/p14 ref-/p26 ds2-/p24 ds1-/p22 ds0-/p20 ref+/p27 ds2+/p25 ds1+/p23 ds0+/p21 40 rxd6/p113, rxd6/p15 (linsel) p121 to p124 4 p120 notes 1. pd78f049x only. 2. pd78f048x and 78f049x only. 3. pd78f047x and 78f048x only. chapter 1 outline user?s manual u18329ej4v0ud 29 1.7 outline of functions ( pd78f047x) (1/2) item pd78f0471 pd78f0472 pd78f0473 pd78f0474 pd78f0475 flash memory (self-programming supported) note 16 kb 24 kb 32 kb 48 kb 60 kb high-speed ram note 768 bytes 1 kb expansion ram note ? 1 kb internal memory lcd display ram 40 4 bits (with 4 com) or 36 8 bits (with 8 com) memory space 64 kb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 2 to 10 mhz: v dd = 2.7 to 5.5 v, 2 to 5 mhz: v dd = 1.8 to 5.5 v main system clock (oscillation frequency) internal high-speed oscillation clock internal oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v subsystem clock (oscillation frequency) xt1 (crystal) oscillation 32.768 khz (typ.): v dd = 1.8 to 5.5 v internal low-speed oscillation clock (for tmh1, wdt) internal oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) 0.2 s (high-speed system clock: @ f xh = 10 mhz operation) 0.25 s (internal high-speed oscillation clock: @ f rh = 8 mhz (typ.) operation) minimum instruction execution time 122 s (subsystem clock: @ f sub = 32.768 khz operation) instruction set ? 8-bit operation and 16-bit operation ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o ports total: 62 cmos i/o: 58 cmos input: 4 timers ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 3 channels (out of which 2 channels can perform pwm output) ? 8-bit timer: 3 channels (out of which 2 channels can perform pwm output) ? real-time counter: 1 channel ? watchdog timer: 1 channel timer outputs 5 (pwm output: 4 and ppg output: 1) rtc outputs 2 ? 1 hz (subsystem clock: f sub = 32.768 khz) ? 512 hz or 16.384 khz or 32.768 khz (subsystem clock: f sub = 32.768 khz) clock output ? 156.25 khz, 312.5 khz, 625 khz, 1.25 mhz, 5 mhz, 10 mhz (peripheral hardware clock: @ f prs = 10 mhz operation) ? 32.768 khz (subsystem clock: @ f sub = 32.768 khz operation) buzzer output ? 1.22 khz, 2.44 khz, 4.88 khz, 9.77 mhz (peripheral hardware clock: @ f prs = 10 mhz operation) note the internal flash memory capacity, internal high- speed ram capacity, and internal expansion ram capacity can be changed using the internal memory size switch ing register (ims) and the internal expansion ram size switching register (ixs). chapter 1 outline user?s manual u18329ej4v0ud 30 (2/2) item pd78f0471 pd78f0472 pd78f0473 pd78f0474 pd78f0475 10-bit successive approximation type a/d converter ? 16-bit ? type a/d converter ? serial interface ? uart supporting lin-bus note 1 : 1 channel ? 3-wire serial i/o/uart note 2 : 1 channel ? automatic transmit/receive 3-wire csi: 1 channel lcd controller/driver ? external resistance divisi on and internal resistance division are switchable. ? segment signal outputs: 40 (36) [36 (32)] note 3, 4 ? common signal outputs: 4 (8) note 3 remote controller receiver provided m anchester code generator provided internal 20 vectored interrupt sources external 7 segment key source signal outpu t segment key source signal out puts: 8 (seg24(ks0)-seg31(ks7)) key interrupt key interrupt (intkr) occurs by det ecting falling edge of key input pins (kr0 to kr7). reset ? reset using reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector on-chip debug function provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c package ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) notes 1. the lin-bus supporting uart pins can be changed to the automatic trans mit/receive 3-wire csi pins (pin numbers 75 and 76). 2. select either of the functions of these alternate-function pins. 3. the values in parentheses are the number of signal outputs when 8com is used. 4. the values in square brackets are the number of si gnal outputs when using the uart6 pins (rxd6, txd6) on the bottom side. chapter 1 outline user?s manual u18329ej4v0ud 31 an outline of the timer is shown below. 16-bit timer/ event counters 00 8-bit timer/ event counters 50, 51, and 52 8-bit timers h0, h1, and h2 tm00 tm50 tm51 tm52 tmh0 tmh1 tmh2 real-time counter watchdog timer interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 c hannel note 1 ? external event counter 1 channel note 2 1 channel 1 channel 1 channel note 2 ? ? ? note 2 ? ? ppg output 1 output ? ? ? ? ? ? ? ? pwm output ? 1 output 1 output ? 1 output 1 output ? ? ? pulse width measurement 2 inputs ? ? ? ? ? ? ? ? square-wave output 1 output 1 output 1 output ? 1 output 1 output ? ? ? carrier generator ? ? ? note 3 ? ? 1 output note 3 ? ? ? calendar function ? ? ? ? ? ? ? 1 channel note 1 rtc output ? ? ? ? ? ? ? 2 outputs note 4 ? function watchdog timer ? ? ? ? ? ? ? ? 1 channel interrupt source 2 1 1 1 1 1 1 1 ? notes 1. in the real-time counter, the interval timer function and calendar function can be used simultaneously. 2. tm52 and tm00 can be connected in cascade to be used as a 24-bit counter. also, the external event input of tm52 can be input enable-controlled via tmh2. 3. tm51 and tmh1 can be used in combination as a carrier generator mode. 4. a 1 hz output can be used as one output and a 512 hz, 16.384 khz, or 32.768 khz output can be used as one output. chapter 1 outline user?s manual u18329ej4v0ud 32 1.8 outline of functions ( pd78f048x) (1/2) item pd78f0481 pd78f0482 pd78f0483 pd78f0484 pd78f0485 flash memory (self-programming supported) note 16 kb 24 kb 32 kb 48 kb 60 kb high-speed ram note 768 bytes 1 kb expansion ram note ? 1 kb internal memory lcd display ram 40 4 bits (with 4 com) or 36 8 bits (with 8 com) memory space 64 kb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 2 to 10 mhz: v dd = 2.7 to 5.5 v, 2 to 5 mhz: v dd = 1.8 to 5.5 v main system clock (oscillation frequency) internal high-speed oscillation clock internal oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v subsystem clock (oscillation frequency) xt1 (crystal) oscillation 32.768 khz (typ.): v dd = 1.8 to 5.5 v internal low-speed oscillation clock (for tmh1, wdt) internal oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) 0.2 s (high-speed system clock: @ f xh = 10 mhz operation) 0.25 s (internal high-speed oscillation clock: @ f rh = 8 mhz (typ.) operation) minimum instruction execution time 122 s (subsystem clock: @ f sub = 32.768 khz operation) instruction set ? 8-bit operation and 16-bit operation ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o ports total: 62 cmos i/o: 58 cmos input: 4 timers ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 3 channels (out of which 2 channels can perform pwm output) ? 8-bit timer: 3 channels (out of which 2 channels can perform pwm output) ? real-time counter: 1 channel ? watchdog timer: 1 channel timer outputs 5 (pwm output: 4 and ppg output: 1) rtc outputs 2 ? 1 hz (subsystem clock: f sub = 32.768 khz) ? 512 hz or 16.384 khz or 32.768 khz (subsystem clock: f sub = 32.768 khz) clock output ? 156.25 khz, 312.5 khz, 625 khz, 1.25 mhz, 5 mhz, 10 mhz (peripheral hardware clock: @ f prs = 10 mhz operation) ? 32.768 khz (subsystem clock: @ f sub = 32.768 khz operation) buzzer output ? 1.22 khz, 2.44 khz, 4.88 khz, 9.77 mhz (peripheral hardware clock: @ f prs = 10 mhz operation) note the internal flash memory capacity, internal high- speed ram capacity, and internal expansion ram capacity can be changed using the internal memory size switch ing register (ims) and the internal expansion ram size switching register (ixs). chapter 1 outline user?s manual u18329ej4v0ud 33 (2/2) item pd78f0481 pd78f0482 pd78f0483 pd78f0484 pd78f0485 10-bit successive approximation type a/d converter 10-bit resolution 8 channels (av ref = 2.3 to 5.5 v) 16-bit ? type a/d converter ? serial interface ? uart supporting lin-bus note 1 : 1 channel ? 3-wire serial i/o/uart note 2 : 1 channel ? automatic transmit/receive 3-wire csi: 1 channel lcd controller/driver ? external resistance divisi on and internal resistance division are switchable. ? segment signal outputs: 40 (36) [36 (32)] note 3 4 ? common signal outputs: 4 (8) note 3 remote controller receiver provided m anchester code generator provided internal 21 vectored interrupt sources external 7 segment key source signal outpu t segment key source signal out puts: 8 (seg24(ks0)-seg31(ks7)) key interrupt key interrupt (intkr) occurs by det ecting falling edge of key input pins (kr0 to kr7). reset ? reset using reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector on-chip debug function provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c package ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) notes 1. the lin-bus supporting uart pins can be changed to th e automatic transmit/receive 3-wire csi pins (pin numbers 75 and 76). 2. select either of the functions of these alternate-function pins. 3. the values in parentheses are the number of signal outputs when 8com is used. 4. the values in square brackets are the number of si gnal outputs when using the uart6 pins (rxd6, txd6) on the bottom side. chapter 1 outline user?s manual u18329ej4v0ud 34 an outline of the timer is shown below. 16-bit timer/ event counters 00 8-bit timer/ event counters 50, 51, and 52 8-bit timers h0, h1, and h2 tm00 tm50 tm51 tm52 tmh0 tmh1 tmh2 real-time counter watchdog timer interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 c hannel note 1 ? external event counter 1 channel note 2 1 channel 1 channel 1 channel note 2 ? ? ? note 2 ? ? ppg output 1 output ? ? ? ? ? ? ? ? pwm output ? 1 output 1 output ? 1 output 1 output ? ? ? pulse width measurement 2 inputs ? ? ? ? ? ? ? ? square-wave output 1 output 1 output 1 output ? 1 output 1 output ? ? ? carrier generator ? ? ? note 3 ? ? 1 output note 3 ? ? ? calendar function ? ? ? ? ? ? ? 1 channel note 1 rtc output ? ? ? ? ? ? ? 2 outputs note 4 ? function watchdog timer ? ? ? ? ? ? ? ? 1 channel interrupt source 2 1 1 1 1 1 1 1 ? notes 1. in the real-time counter, the interval timer function and calendar function can be used simultaneously. 2. tm52 and tm00 can be connected in cascade to be used as a 24-bit counter. also, the external event input of tm52 can be input enable-controlled via tmh2. 3. tm51 and tmh1 can be used in combination as a carrier generator mode. 4. a 1 hz output can be used as one output and a 512 hz, 16.384 khz, or 32.768 khz output can be used as one output. chapter 1 outline user?s manual u18329ej4v0ud 35 1.9 outline of functions ( pd78f049x) (1/2) item pd78f0491 pd78f0492 pd78f0493 pd78f0494 pd78f0495 flash memory (self-programming supported) note 16 kb 24 kb 32 kb 48 kb 60 kb high-speed ram note 768 bytes 1 kb expansion ram note ? 1 kb internal memory lcd display ram 32 4 bits (with 4 com) or 28 8 bits (with 8 com) memory space 64 kb high-speed system clock x1 (crystal/ceramic) oscillation, extern al main system clock input (exclk) 2 to 10 mhz: v dd = 2.7 to 5.5 v, 2 to 5 mhz: v dd = 1.8 to 5.5 v main system clock (oscillation frequency) internal high-speed oscillation clock internal oscillation 8 mhz (typ.): v dd = 1.8 to 5.5 v subsystem clock (oscillation frequency) xt1 (crystal) oscillation 32.768 khz (typ.): v dd = 1.8 to 5.5 v internal low-speed oscillation clock (for tmh1, wdt) internal oscillation 240 khz (typ.): v dd = 1.8 to 5.5 v general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) 0.2 s (high-speed system clock: @ f xh = 10 mhz operation) 0.25 s (internal high-speed oscillation clock: @ f rh = 8 mhz (typ.) operation) minimum instruction execution time 122 s (subsystem clock: @ f sub = 32.768 khz operation) instruction set ? 8-bit operation and 16-bit operation ? bit manipulate (set, reset, test, and boolean operation) ? bcd adjust, etc. i/o ports total: 62 cmos i/o: 58 cmos input: 4 timers ? 16-bit timer/event counter: 1 channel ? 8-bit timer/event counter: 3 channels (out of which 2 channels can perform pwm output) ? 8-bit timer: 3 channels (out of which 2 channels can perform pwm output) ? real-time counter: 1 channel ? watchdog timer: 1 channel timer outputs 5 (pwm output: 4 and ppg output: 1) rtc outputs 2 ? 1 hz (subsystem clock: f sub = 32.768 khz) ? 512 hz or 16.384 khz or 32.768 khz (subsystem clock: f sub = 32.768 khz) clock output ? 156.25 khz, 312.5 khz, 625 khz, 1.25 mhz, 5 mhz, 10 mhz (peripheral hardware clock: @ f prs = 10 mhz operation) ? 32.768 khz (subsystem clock: @ f sub = 32.768 khz operation) buzzer output ? 1.22 khz, 2.44 khz, 4.88 khz, 9.77 mhz (peripheral hardware clock: @ f prs = 10 mhz operation) note the internal flash memory capacity, internal high- speed ram capacity, and internal expansion ram capacity can be changed using the internal memory size switch ing register (ims) and the internal expansion ram size switching register (ixs). chapter 1 outline user?s manual u18329ej4v0ud 36 (2/2) item pd78f0491 pd78f0492 pd78f0493 pd78f0494 pd78f0495 10-bit successive approximation type a/d converter 10-bit resolution 8 channels (av ref = 2.3 to 5.5 v) 16-bit ? type note 1 a/d converter 16-bit resolution 3 channels (av ref = 2.7 to 5.5 v) serial interface ? uart supporting lin-bus note 2 : 1 channel ? 3-wire serial i/o/uart note 3 : 1 channel ? automatic transmit/receive 3-wire csi: 1 channel lcd controller/driver ? external resistance divisi on and internal resistance division are switchable. ? segment signal outputs: 32 (28) [28 (24)] note 4, 5 ? common signal outputs: 4 (8) note 4 remote controller receiver provided m anchester code generator provided internal 22 vectored interrupt sources external 7 segment key source signal outpu t segment key source signal out puts: 8 (seg24(ks0)-seg31(ks7)) key interrupt key interrupt (intkr) occurs by det ecting falling edge of key input pins (kr0 to kr7). reset ? reset using reset pin ? internal reset by watchdog timer ? internal reset by power-on-clear ? internal reset by low-voltage detector on-chip debug function provided power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to +85 c package ? 80-pin plastic lqfp (14 14) ? 80-pin plastic lqfp (fine pitch) (12 12) notes 1. the specifications of the 16-bit ? a/d converter may have been changed. for details of the specifications , contact an nec electronics sales representative or authorized dealer. 2. the lin-bus supporting uart pins can be changed to the automatic trans mit/receive 3-wire csi pins (pin numbers 75 and 76). 3. select either of the functions of these alternate-function pins. 4. the values in parentheses are the number of signal outputs when 8com is used. 5. the values in square brackets are the number of si gnal outputs when using the uart6 pins (rxd6, txd6) on the bottom side. chapter 1 outline user?s manual u18329ej4v0ud 37 an outline of the timer is shown below. 16-bit timer/ event counters 00 8-bit timer/ event counters 50, 51, and 52 8-bit timers h0, h1, and h2 tm00 tm50 tm51 tm52 tmh0 tmh1 tmh2 real-time counter watchdog timer interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 c hannel note 1 ? external event counter 1 channel note 2 1 channel 1 channel 1 channel note 2 ? ? ? note 2 ? ? ppg output 1 output ? ? ? ? ? ? ? ? pwm output ? 1 output 1 output ? 1 output 1 output ? ? ? pulse width measurement 2 inputs ? ? ? ? ? ? ? ? square-wave output 1 output 1 output 1 output ? 1 output 1 output ? ? ? carrier generator ? ? ? note 3 ? ? 1 output note 3 ? ? ? calendar function ? ? ? ? ? ? ? 1 channel note 1 rtc output ? ? ? ? ? ? ? 2 outputs note 4 ? function watchdog timer ? ? ? ? ? ? ? ? 1 channel interrupt source 2 1 1 1 1 1 1 1 ? notes 1. in the real-time counter, the interval timer function and calendar function can be used simultaneously. 2. tm52 and tm00 can be connected in cascade to be used as a 24-bit counter. also, the external event input of tm52 can be input enable-controlled via tmh2. 3. tm51 and tmh1 can be used in combination as a carrier generator mode. 4. a 1 hz output can be used as one output and a 512 hz, 16.384 khz, or 32.768 khz output can be used as one output. user?s manual u18329ej4v0ud 38 chapter 2 pin functions 2.1 pin function list there are three types of pin i/o buffer power supplies: av ref note 1 , v lc0 , and v dd . the relationship between these power supplies and the pins is shown below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref note 1 p20 to p27 v lc0 com0 to com7, seg0 to seg31, seg32 to seg39 note 2 , v lc0 to v lc3 v dd pins other than above notes 1. pd78f048x and 78f049x only. the power supply is v dd with pd78f047x. 2. pd78f047x and 78f048x only. (1) port pins (1/3) function name i/o function after reset alternate function p10 pcl p11 sck10 p12 si10/rxd0 p13 so10/txd0 p14 scka0/intp4 p15 sia0/ chapter 2 pin functions user?s manual u18329ej4v0ud 39 (1) port pins (2/3) function name i/o function after reset alternate function p20 seg39 note 1 /ani0 note 2 / ds0 ? note 3 p21 seg38 note 1 /ani1 note 2 / ds0+ note3 p22 seg37 note 1 /ani2 note 2 / ds1 ? note3 p23 seg36 note 1 /ani3 note 2 / ds1+ note3 p24 seg35 note 1 /ani4 note 2 / ds2 ? note 3 p25 seg34 note 1 /ani5 note 2 / ds2+ note 3 p26 seg33 note 1 /ani6 note 2 / ref ? note 3 p27 i/o port 2. 8-bit i/o port. input/output can be specified in 1-bit units. digital input port seg32 note 1 /ani7 note 2 / ref+ note 3 p30 intp5 p31 toh1/intp3 p32 toh0/mcgo p33 ti000/rtcdiv/ rtccl/buz/intp2 p34 i/o port 3. 5-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port ti52/ti010/to00/ rtc1hz/intp1 p40 v lc3 /kr0 p41 rin/kr1 p42 kr2 p43 to51/ti51/kr3 p44 to50/ti50/kr4 p45 to p47 i/o port 4. 8-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port kr5 to kr7 p80 to p83 i/o port 8. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg4 to seg7 p90 to p93 i/o port 9. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg8 to seg11 notes 1. pd78f047x and 78f048x only. 2. pd78f048x and 78f049x only. 3. pd78f049x only. chapter 2 pin functions user?s manual u18329ej4v0ud 40 (1) port pins (3/3) function name i/o function after reset alternate function p100 to p103 i/o port 10. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg12 to seg15 p110, p111 seg16, seg17 p112 seg18/txd6 p113 i/o port 11. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg19/rxd6 p120 i/o intp0/exlvi p121 x1/ocd0a p122 x2/exclk/ocd0b p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 to p133 i/o port 13. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg20 to seg23 p140 to p143 i/o port 14. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg24 (ks0) to seg27 (ks3) p150 to p153 i/o port 15. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg28 (ks4) to seg31 (ks7) chapter 2 pin functions user?s manual u18329ej4v0ud 41 (2) non-port pins (1/4) function name i/o function after reset alternate function ani0 note 2 p20/seg39 note 1 / ds0 ? note 3 ani1 note 2 p21/seg38 note 1 / ds0+ note 3 ani2 note 2 p22/seg37 note 1 / ds1 ? note 3 ani3 note 2 p23/seg36 note 1 / ds1+ note 3 ani4 note 2 p24/seg35 note 1 / ds2 ? note 3 ani5 note 2 p25/seg34 note 1 / ds2+ note 3 ani6 note 2 p26/seg33 note 1 / ref ? note 3 ani7 note 2 input 10-bit successive approximation type a/d converter analog input. digital input port p27/seg32 note 1 / ref+ note 3 ds0 ? note 3 p20 /ani0 note 2 ds0+ note 3 p21/ani1 note 2 ds1 ? note 3 p22/ani2 note 2 ds1+ note 3 p23/ani3 note 2 ds2 ? note 3 p24/ani4 note 2 ds2+ note 3 16-bit ? type a/d converter analog input. p25/ani5 note 2 ref ? note 3 16-bit ? type a/d converter reference voltage input. make the same potential as v ss and av ss . p26/ani6 note 2 ref+ note 3 input 16-bit ? type a/d converter reference voltage input. make the same potential as av ref . digital input port p27/ani7 note 2 av ref note 2 input 10-bit successive approximation type a/d converter reference voltage input, positive power supply for port 2, and 16-bit ? type a/d converter note3 ? ? av ss note 2 ? a/d converter ground potential. make the same potential as v ss . ? ? notes 1. pd78f047x and 78f048x only. 2. pd78f048x and 78f049x only. 3. pd78f049x only. chapter 2 pin functions user?s manual u18329ej4v0ud 42 (2) non-port pins (2/4) function name i/o function after reset alternate function seg0 to seg3 output com4 to com7 seg4 to seg7 p80 to p83 seg8 to seg11 p90 to p93 seg12 to seg15 p100 to p103 seg16, seg17 p110, p111 seg18 p112/txd6 seg19 p113/rxd6 seg20 to seg23 lcd controller/driver segment signal outputs p130 to p133 seg24 (ks0) to seg27 (ks3) p140 to p143 seg28 (ks4) to seg31 (ks7) lcd controller/driver segment signal outputs. segment key source signal can be simultaneously output. input port p150 to p153 seg32 note 1 p27/ani7 note 2 seg33 note 1 p26/ani6 note 2 seg34 note 1 p25/ani5 note 2 seg35 note 1 p24/ani4 note 2 seg36 note 1 p23/ani3 note 2 seg37 note 1 p22/ani2 note 2 seg38 note 1 p21/ani1 note 2 seg39 note 1 output lcd controller/driver segment signal outputs digital input port p20/ani0 note 2 com0 to com3 ? com4 to com7 output lcd controller/driver common signal outputs output seg0 to seg3 v lc0 to v lc2 ? ? v lc3 ? lcd drive voltage input port p40/kr0 notes 1. pd78f047x and 78f048x only. 2. pd78f048x and 78f049x only. chapter 2 pin functions user?s manual u18329ej4v0ud 43 (2) non-port pins (3/4) function name i/o function after reset alternate function buz output buzzer output input port p33/ti000/rtcdiv /rtccl/intp2 intp0 p120/exlvi intp1 p34/ti52/ti010/ to00/rtc1hz intp2 p33/ti000/rtcdiv /rtccl/buz intp3 p31/toh1 intp4 p14/scka0 intp5 input external interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input port p30 kr0 p40/v lc3 kr1 p41/rin kr2 p42 kr3 p43/to51/ti51 kr4 p44/to50/ti50 kr5 to kr7 input key interrupt input or segment key scan input input port p45 to p47 mcgo output manchester code output input port p32/toh0 pcl output clock output input port p10 regc ? connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect to v ss via a capacitor (0.47 to 1 f: recommended). ? ? reset input system reset input ? ? rin input remote control reception data input input port p41/kr1 rtcdiv output real-time counter clock ( 32 khz divided frequency) output input port p33/ti000/rtccl /buz/intp2 rtccl output real-time counter clock (32 khz original oscillation) output input port p33/ti000/rtcdiv /buz/intp2 rtc1hz output real-time counter clock (1 hz) output input port p34/ti52/ti010/ to00/intp1 rxd0 p12/si10 rxd6 p113/seg19 chapter 2 pin functions user?s manual u18329ej4v0ud 44 (2) non-port pins (4/4) function name i/o function after reset alternate function ti000 external count clock input to 16-bit timer/event counter 00 capture trigger input to captur e registers (cr000, cr010) of 16-bit timer/event counter 00 p33/rtcdiv/ rtccl/buz/ intp2 ti010 input capture trigger input to capture register (cr000) of 16-bit timer/event counter 00 input port p34/ti52/to00/ rtc1hz/intp1 ti50 external count clock input to 8- bit timer/event counter 50 p44/to50/kr4 ti51 external count clock input to 8- bit timer/event counter 51 p43/to51/kr3 ti52 input external count clock input to 8-bit timer/event counter 52 input port p34/ti010/to00/ rtc1hz/intp1 to00 output 16-bit timer/event counter 00 output input port p34/ti52/ti010/ rtc1hz/intp1 to50 8-bit timer/event counter 50 output p44/ti50/kr4 to51 output 8-bit timer/event counter 51 output input port p43/ti51/kr3 toh0 8-bit timer h0 output p32/mcgo toh1 output 8-bit timer h1 output input port p31/intp3 txd0 p13/so10 txd6 p112/seg18 chapter 2 pin functions user?s manual u18329ej4v0ud 45 2.2 description of pin functions 2.2.1 p10 to p17 (port 1) p10 to p17 function as an 8-bit i/o port. t hese pins also function as pins for ex ternal interrupt re quest input, serial interface data i/o, clock i/o, and clock output. p13 and p16 can be selected to function as pins, using port function register 1 (pf1) (see figure 4-30). the following operation modes can be specified in 1-bit units. (1) port mode p10 to p17 function as an 8-bit i/o port. p10 to p17 can be set to input or output por t in 1-bit units using port mode register 1 (pm1). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 1 (pu1). (2) control mode p10 to p17 function as external interrupt request in put, serial interface data i/o, clock i/o, and clock output. (a) si10, sia0 these are serial interface serial data input pins. (b) so10, soa0 these are serial interface serial data output pins. (c) sck10, scka0 these are serial interfac e serial clock i/o pins. (d) rxd0, rxd6 these are the serial data input pins of the asynchronous serial interface. (e) txd0, txd6 these are the serial data output pins of the asynchronous serial interface. (f) pcl this is a clock output pin. (g) intp4 this is an external interrupt request input pin for whic h the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. chapter 2 pin functions user?s manual u18329ej4v0ud 46 2.2.2 p20 to p27 (port 2) p20 to p27 function as an 8-bit i/o port. these pins also function as pins for segment signal output pins for the lcd controller/driver, 10-bit successive approx imation type a/d converter analog input ( pd78f048x and 78f049x only), 16-bit ? type a/d converter analog input, and reference voltage input ( pd78f049x only). either i/o port function or segment signal output function can be se lected using port function register 2 (pf2). the following operation modes can be specified in 1-bit units. (1) port mode p20 to p27 function as an 8-bit i/o port. p20 to p27 can be set to input or output por t in 1-bit units using port mode register 2 (pm2). (2) control mode p20 to p27 function as segment signal output for the lcd c ontroller/driver, 10-bit successive approximation type a/d converter analog input ( pd78f048x and 78f049x only), 16-bit ? type a/d converter analog input ( pd78f049x only), and reference voltage input. (a) seg32 to seg39 these pins are the segment signal output pins for the lcd controller/driver. (b) ani0 to ani7 ( pd78f048x and 78f049x only) these are 10-bit successive approximation type a/d converte r analog input pins. when using these pins as analog input pins, see (5) ani0/seg39/p20 to ani 7/seg32/p27 pins ( pd78f048x), ani0/ds0 ? /p20 to ani7/ref+/p27 pins ( pd78f049x) in 12.6 cautions for 10-bit suc cessive approximation type a/d converter . (c) ds0 ? , ds0+, ds1 ? , ds1+, ds2 ? , ds2+, ref ? , and ref+ ( pd78f049x only) these are 16-bit ? type a/d converter analog input pins, and reference voltage input pins. set ref ? to the same potential as v ss and av ss . set ref+ to the same potential as av ref . caution p20 to p27 are set in the analog input mode after release of reset. 2.2.3 p30 to p34 (port 3) p30 to p34 function as a 5-bit i/o port. these pins also function as pins for external interrupt request input, timer i/o, buzzer output, real-time counter output, and manchester code output. the following operation modes can be specified in 1-bit units. (1) port mode p30 to p34 function as a 5-bit i/o port. p30 to p34 can be set to input or output port in 1-bit units using port mode register 3 (pm3). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 3 (pu3). (2) control mode p30 to p34 function as external interrupt request inpu t, timer i/o, buzzer output, real -time counter output, and manchester code output. chapter 2 pin functions user?s manual u18329ej4v0ud 47 (a) intp1 to intp3 and intp5 these are the external interrupt request input pins fo r which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) to00, toh0, toh1 these are timer output pin. (c) ti000 this is a pin for inputting an external count clock to 16-bit timer/event counters 00 and is also for inputting a capture trigger signal to the capt ure registers (cr000 or cr010) of 16-bit timer/event counters 00. (d) ti010 this is a pin for inputting a capture trigger signal to the capture register (cr000) of 16-bit timer/event counters 00. (e) ti52 this is the pin for inputting an external c ount clock to 8-bit timer/event counter 52. (f) buz this is a buzzer output pin. (g) rtcdiv this is a real-time counter clo ck (32 khz, divided) output pin. (h) rtccl this is a real-time counter clock (32 kh z, original oscillation) output pin. (i) rtc1hz this is a real-time counter correction clock (1 hz) output pin. (j) mcgo this is a manchester code output pin. 2.2.4 p40 to p47 (port 4) p40 to p47 function as an 8-bit i/o port. these pins also function as pins for key interrupt input, segment key scan input, timer i/o, remote control re ceive data input, and power supply voltage for driving the lcd. the following operation modes can be specified in 1-bit units. (1) port mode p40 to p47 function as an 8-bit i/o port. p40 and p47 can be set to input port or output port in 1-bit units using port mode register 4 (pm4). use of an on-chip pull-up resi stor can be specified by pull- up resistor option register 4 (pu4). (2) control mode p40 and p47 function as key interrupt input, segment ke y scan input, timer i/o, remote control receive data input, and power supply voltage for driving the lcd. chapter 2 pin functions user?s manual u18329ej4v0ud 48 (a) kr0 to kr7 these are the key interrupt input or segment key scan input pins. (b) to50, to51 these are the timer output pin from 8-bit timer/event counter 50 and 51. (c) ti50, ti51 these are the pins for inputting an external count clock to 8-bit timer/event counter 50 and 51. (d) rin this is the data input pin of the remote controller receiver. (e) v lc3 this is the power supply volt age pins for driving the lcd. 2.2.5 p80 to p83 (port 8) p80 to p83 function as a 4-bit i/o port. these pins also function as segment signal output pins for the lcd controller/driver. either i/o port func tion or segment signal output function c an be selected using port function register all (pfall). (1) port mode p80 to p83 function as a 4-bit i/o port. p80 to p83 can be set to input or output port in 1-bit units using port mode register 8 (pm8). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 8 (pu8). (2) control mode p80 to p83 function as segment signal output for the lcd controller/driver. (a) seg4 to seg7 these pins are the segment signal output pins for the lcd controller/driver. 2.2.6 p90 to p93 (port 9) p90 to p93 function as a 4-bit i/o port. these pins also function as segment signal output pins for the lcd controller/driver. either i/o port func tion or segment signal output function c an be selected using port function register all (pfall). (1) port mode p90 to p93 function as a 4-bit i/o port. p90 to p93 can be set to input or output port in 1-bit units using port mode register 9 (pm9). use of an on -chip pull-up resistor can be specified by pull-up resistor option register 9 (pu9). (2) control mode p90 to p93 function as segment signal output for the lcd controller/driver. (a) seg8 to seg11 these pins are the segment signal output pins for the lcd controller/driver. chapter 2 pin functions user?s manual u18329ej4v0ud 49 2.2.7 p100 to p103 (port 10) p100 to p103 function as a 4-bit i/o port. these pins also function as segment signal output pins for the lcd controller/driver. either i/o port func tion or segment signal output function c an be selected using port function register all (pfall). (1) port mode p100 to p103 function as a 4-bit i/o port. p100 to p103 can be set to input or output por t in 1-bit units using port mode register 10 (pm10). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 10 (pu10). (2) control mode p100 to p103 function as segment signal output for the lcd controller/driver. (a) seg12 to seg15 these pins are the segment signal output pins for the lcd controller/driver. 2.2.8 p110 to p113 (port 11) p110 to p113 function as a 4-bit i/o port. these pins al so function as pins for segm ent signal output for the lcd controller/driver and serial interface data i/o. either i/o po rt function (other than segment signal output) or segment signal output function can be selected usin g port function register all (pfall). (1) port mode p110 to p113 function as a 4-bit i/o port. p110 to p113 can be set to input or output por t in 1-bit units using port mode register 11 (pm11). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 11 (pu11). (2) control mode p110 to p113 function as segment signal output for the lcd controller/driver and serial interface data i/o. (a) seg16 to seg19 these pins are the segment signal output pins for the lcd controller/driver. (b) rxd6 this is a serial data input pi n of serial interface uart6. (c) txd6 this is a serial data output pin of serial interface uart6. 2.2.9 p120 to p124 (port 12) p120 functions as a 1-bit i/o port. p121 to p124 function as a 4-bit input port. these pins also function as pins for external interrupt request input, potential input for extern al low-voltage detection, resonator for main system clock connection, resonator for subsystem clock connection, and external clock input. the following operation modes can be specified in 1-bit units. (1) port mode p120 functions as a 1-bit i/o port and p121 to p124 function as a 4-bit input port. only for p120, can be set to input or output port using port mode re gister 12 (pm12). only for p120, us e of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). chapter 2 pin functions user?s manual u18329ej4v0ud 50 (2) control mode p120 to p124 function as an external interrupt request in put, potential input for external low-voltage detection, resonator for main system clock connec tion, resonator for subsystem clock connection, and external clock input. (a) intp0 this functions as an external interrupt request inpu t (intp0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) exlvi this is a potential input pin for external low-voltage detection. (c) x1, x2 these are the pins for connecting a resonator for main system clock. (d) exclk this is an external clock inpu t pin for main system clock. (e) xt1, xt2 these are the pins for connecting a resonator for subsystem clock. remark x1 and x2 can be used as on-chip debug mode setti ng pins (ocd0a, ocd0b) when the on-chip debug function is used. for detail, see chapter 29 on-chip debug function. 2.2.10 p130 to p133 (port 13) p130 to p133 function as a 4-bit i/o port. these pins also function as pins for segment signal output pins for the lcd controller/driver and serial interface data i/o. either i/o port function or segment signal output function can be selected using port function register all (pfall). (1) port mode p130 to p133 function as a 4-bit i/o port. p130 to p133 can be set to input or output por t in 1-bit units using port mode register 13 (pm13). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 13 (pu13). (2) control mode p130 to p133 function as segment signal output for the lcd controller/driver. (a) seg20 to seg23 these pins are the segment signal output pins for the lcd controller/driver. 2.2.11 p140 to p143 (port 14) p140 to p143 function as a 4-bit i/o port. these pins also function as pins fo r segment signal output and simultaneous output of segment key source signal for the lcd controller/driver. eit her i/o port function or segment signal output function can be selected usin g port function register all (pfall). (1) port mode p140 to p143 function as a 4-bit i/o port. p140 to p143 can be set to input or output por t in 1-bit units using port mode register 14 (pm14). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (pu14). chapter 2 pin functions user?s manual u18329ej4v0ud 51 (2) control mode p140 to p143 function as segment signal output and simu ltaneous output of segment key source signal for the lcd controller/driver. (a) seg24 (ks0) to seg27 (ks3) these pins are the segment signal output pins for the lcd controller/driver. the segment key source signal output can be simult aneously used by setting the lcd mode register (lcdmd). 2.2.12 p150 to p153 (port 15) p150 to p153 function as a 4-bit i/o port. these pins also function as pins fo r segment signal output and simultaneous output of segment key source signal for the lcd controller/driver. eit her i/o port function or segment signal output function can be selected usin g port function register all (pfall). (1) port mode p150 to p153 function as a 4-bit i/o port. p150 to p153 can be set to input or output por t in 1-bit units using port mode register 15 (pm15). use of an on-chip pull-up resistor can be specified by pull-up resistor option register 15 (pu15). (2) control mode p150 to p153 function as segment signal output and simu ltaneous output of segment key source signal for the lcd controller/driver. (a) seg28 (ks4) to seg31 (ks7) these pins are the segment signal output pins for the lcd controller/driver. the segment key source signal output can be simult aneously used by setting the lcd mode register (lcdmd). 2.2.13 av ref ( pd78f048x and 78f049x only) this is the 10-bit successive approximation type a/d conver ter reference voltage input pin and the positive power supply pin of port 2 and 16-bit ? type a/d converter. when the a/d converter is not used, connect this pin directly to v dd note . note when one or more of the pins of por t 2 is used as the digital port pins or for segment output, make av ref the same potential as v dd . 2.2.14 av ss ( pd78f048x and 78f049x only) this is the a/d converter ground potenti al pin. even when the a/d converter is not used, always use this pin with the same potential as the v ss pin. 2.2.15 com0 to com7 these pins are the common signal output pins for the lcd controller/driver. 2.2.16 v lc0 to v lc3 these pins are the power supply vo ltage pins for driving the lcd. 2.2.17 reset this is the active-low system reset input pin. chapter 2 pin functions user?s manual u18329ej4v0ud 52 2.2.18 regc this is the pin for connecting regulator output (2.4 v) stabilization capacitance for internal operation. connect this pin to v ss via a capacitor (0.47 to 1 f: recommended). regc v ss caution keep the wiring length as short as possible in the ar ea enclosed by the broken lines in the above figures. 2.2.19 v dd this is the positive power supply pin. 2.2.20 v ss this is the ground potential pin. 2.2.21 flmd0 this is a pin for setting flash memory programming mode. connect flmd0 to v ss in the normal operation mode. in flash memory programming mode, connect this pin to the flash memory programmer. chapter 2 pin functions user?s manual u18329ej4v0ud 53 2.3 pin i/o circuits and recommended connection of unused pins table 2-2 shows the types of pin i/o circuits and the recommended connections of unused pins. see figure 2-1 for the configuration of the i/o circuit of each type. table 2-2. pin i/o circuit types (1/2) pin name i/o circuit type i/o recommended connection of unused pins p10/pcl 5-ag p11/sck10 p12/si10/rxd0 p13/so10/txd0 p14/scka0/intp4 p15/sia0/ chapter 2 pin functions user?s manual u18329ej4v0ud 54 table 2-2. pin i/o circuit types (2/2) pin name i/o circuit type i/o recommended connection of unused pins p110/seg16, p111/seg17 p112/seg18/txd6 17-p p113/seg19/rxd6 17-q chapter 2 pin functions user?s manual u18329ej4v0ud 55 figure 2-1. pin i/o circuit list (1/2) type 2 type 5-ao schmitt-triggered input with hysteresis characteristics in pullup enable data output disable input enable p-ch p-ch in/out v dd v dd v ss n -ch v lc3 type 5-ag type 17-p pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch v ss p-ch n-ch seg data p-ch n-ch p-ch p-ch n-ch pullup enable data output disable input enable p-ch p-ch in/out p-ch n-ch n-ch v lc0 v lc1 v lc2 v dd v dd n -ch v lc3 v ss v ss type 5-ah type 17-q pull-up enable data output disable input enable v dd p-ch v dd p-ch in/out n -ch v ss p-ch n-ch seg data p-ch n-ch p-ch n-ch pullup enable data output disable input enable p-ch p-ch in/out p-ch n-ch n-ch v lc0 v lc1 v lc2 v dd v dd n -ch v lc3 v ss chapter 2 pin functions user?s manual u18329ej4v0ud 56 figure 2-1. pin i/o circuit list (2/2) type 17-r type 18-f p-ch n-ch seg data p-ch n-ch n-ch p-ch p-ch n-ch data dsn/ref output disable input enable p-ch p-ch in/out p-ch n-ch n-ch ani av ref av ss av ss av ref + _ n-ch p-ch av ss v lc0 v lc1 v lc2 n -ch v lc3 v ss comparator p-ch com data p-ch n-ch p-ch n-ch n-ch n-ch p-ch p-ch n-ch p-ch n-ch out p-ch n-ch seg data p-ch n-ch p-ch n-ch p-ch n-ch n-ch v lc0 v lc1 v lc2 v lc3 v ss v lc0 v lc1 v lc2 v lc3 v ss type 18-e type 37-a p-ch com data p-ch n-ch out p-ch n-ch n-ch n-ch p-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 v lc3 v ss x1, xt1 input enable input enable p-ch n-ch x2, xt2 type 38 user?s manual u18329ej4v0ud 57 chapter 3 cpu architecture 3.1 memory space each products in the 78k0/lf3 can access a 64 kb memory space. figures 3-1 to 3-10 show the memory maps. caution regardless of the internal memory capacity, the initial valu es of the internal memory size switching register (ims) and intern al expansion ram size switching register (ixs) of all products in the 78k0/lf3 are fixed (ims = cfh, ixs = 0 ch). therefore, set the value corresponding to each product as indicated below. table 3-1. set values of internal memo ry size switching register (ims) and internal expansion ram si ze switching register (ixs) flash memory version (78k0/lf3) ims ixs rom capacity internal high-speed ram capacity internal expansion ram capacity pd78f0471, 78f0481, 78f0491 04h 16 kb 768 bytes pd78f0472, 78f0482, 78f0492 c6h 24 kb pd78f0473, 78f0483, 78f0493 c8h 0ch 32 kb ? pd78f0474, 78f0484, 78f0494 cch 48 kb pd78f0475, 78f0485, 78f0495 cfh 0ah 60 kb 1 kb 1 kb chapter 3 cpu architecture user?s manual u18329ej4v0ud 58 figure 3-1. memory map ( pd78f0471, 78f0481) special function registers (sfr) 256 x 8 bits internal high-speed ram 768 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 16384 x 8 bits program memory space data memory space ffffh ff00h feffh fee0h fedfh fc00h fbffh 4000h 3fffh 0000h 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area 3fffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits fa68h fa67h lcd display ram 40 8 bits fa40h fa3fh reserved fa20h fa1fh fa00h f9ffh reserved buffer ram 32 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 0fh 1 kb 3fffh 07ffh 0000h 0400h 03ffh 3c00h 3bffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 59 figure 3-2. memory map ( pd78f0491) special function registers (sfr) 256 x 8 bits internal high-speed ram 768 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 16384 x 8 bits program memory space data memory space ffffh ff00h feffh fee0h fedfh fc00h fbffh 4000h 3fffh 0000h 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area 3fffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits fa60h fa5fh lcd display ram 32 8 bits fa40h fa3fh reserved note 3 fa20h fa1fh fa00h f9ffh reserved buffer ram 32 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). 3. however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 0fh 1 kb 3fffh 07ffh 0000h 0400h 03ffh 3c00h 3bffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 60 figure 3-3. memory map ( pd78f0472, 78f0482) special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits flash memory 24576 x 8 bits program memory space data memory space ffffh ff00h feffh fee0h fedfh fb00h faffh 6000h 5fffh 0000h 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area 5fffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fa68h fa67h lcd display ram 40 8 bits fa40h fa3fh reserved fa20h fa1fh fa00h f9ffh reserved buffer ram 32 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 17h 1 kb 5fffh 07ffh 0000h 0400h 03ffh 5c00h 5bffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 61 figure 3-4. memory map ( pd78f0492) special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits flash memory 24576 x 8 bits program memory space data memory space ffffh ff00h feffh fee0h fedfh fb00h faffh 6000h 5fffh 0000h 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area 5fffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fa60h fa5fh lcd display ram 32 8 bits fa40h fa3fh reserved note 3 fa20h fa1fh fa00h f9ffh reserved buffer ram 32 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). 3. however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 17h 1 kb 5fffh 07ffh 0000h 0400h 03ffh 5c00h 5bffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 62 figure 3-5. memory map ( pd78f0473, 78f0483) special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits flash memory 32768 x 8 bits program memory space data memory space ffffh ff00h feffh fee0h fedfh fb00h faffh 8000h 7fffh 0000h 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area 7fffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fa68h fa67h lcd display ram 40 8 bits fa40h fa3fh reserved fa20h fa1fh fa00h f9ffh reserved buffer ram 32 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 1fh 1 kb 7fffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 63 figure 3-6. memory map ( pd78f0493) special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits flash memory 32768 x 8 bits program memory space data memory space ffffh ff00h feffh fee0h fedfh fb00h faffh 8000h 7fffh 0000h 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area 7fffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fa60h fa5fh lcd display ram 32 8 bits fa40h fa3fh reserved note 3 fa20h fa1fh fa00h f9ffh reserved buffer ram 32 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). 3. however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 1fh 1 kb 7fffh 07ffh 0000h 0400h 03ffh 7c00h 7bffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 64 figure 3-7. memory map ( pd78f0474, 78f0484) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 1024 8 bits buffer ram 32 8 bits reserved general-purpose registers 32 8 bits reserved reserved ffffh ff00h feffh fee0h fedfh fa40h fa3fh f800h f7ffh fa00h f9ffh fa20h fa1fh f400h f3ffh c000h bfffh 0000h program memory space data memory space flash memory 49152 8 bits ram space in which instruction can be fetched program ram area 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area bfffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fb00h faffh fa68h fa67h lcd display ram 40 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 2fh 1 kb bfffh 07ffh 0000h 0400h 03ffh bc00h bbffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 65 figure 3-8. memory map ( pd78f0494) special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 1024 8 bits buffer ram 32 8 bits reserved general-purpose registers 32 8 bits reserved reserved note 3 ffffh ff00h feffh fee0h fedfh fa40h fa3fh f800h f7ffh fa00h f9ffh fa20h fa1fh f400h f3ffh c000h bfffh 0000h program memory space data memory space flash memory 49152 8 bits ram space in which instruction can be fetched program ram area 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area bfffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fb00h faffh fa60h fa5fh lcd display ram 32 8 bits notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). 3. however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 2fh 1 kb bfffh 07ffh 0000h 0400h 03ffh bc00h bbffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 66 figure 3-9. memory map ( pd78f0475, 78f0485) buffer ram 32 8 bits reserved reserved fa00h f9ffh fa20h fa1fh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 1024 8 bits general-purpose registers 32 8 bits flash memory 61440 8 bits ffffh ff00h feffh fee0h fedfh fa40h fa3fh f800h f7ffh 0000h program memory space data memory space program ram area ram space in which instruction can be fetched 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area efffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fb00h faffh fa68h fa67h lcd display ram 40 8 bits reserved f400h f3ffh f000h efffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 3bh 1 kb efffh 07ffh 0000h 0400h 03ffh ec00h ebffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 67 figure 3-10. memory map ( pd78f0495) buffer ram 32 8 bits reserved reserved note 3 fa00h f9ffh fa20h fa1fh special function registers (sfr) 256 8 bits internal high-speed ram 1024 8 bits internal expansion ram 1024 8 bits general-purpose registers 32 8 bits flash memory 61440 8 bits ffffh ff00h feffh fee0h fedfh fa40h fa3fh f800h f7ffh 0000h program memory space data memory space program ram area ram space in which instruction can be fetched 0800h 07ffh 1000h 0fffh 0040h 003fh 0000h 0085h 0084h program area 1905 8 bits program area efffh program area 0080h 007fh 1080h 107fh 008fh 008eh 1085h 1084h 108fh 108eh vector table area 64 8 bits callt table area 64 8 bits option byte area note 1 5 8 bits on-chip debug security id setting area note 1 10 8 bits option byte area note 1 5 8 bits callf entry area 2048 8 bits 1fffh boot cluster 0 note 2 boot cluster 1 on-chip debug security id setting area note 1 10 8 bits reserved fb00h faffh fa60h fa5fh lcd display ram 32 8 bits reserved f400h f3ffh f000h efffh notes 1. when boot swap is not used: set the option bytes to 0080h to 0084h, and the on-chip debug security ids to 0085h to 008eh. when boot swap is used: set the option bytes to 0080h to 0084h and 1080h to 1084h, and the on-chip debug security ids to 0085h to 008eh and 1085h to 108eh. 2. writing boot cluster 0 can be prohibited depending on the setting of security (see 28.8 security setting ). 3. however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). remark the flash memory is divided into blocks (one block = 1 kb). for the address values and block numbers, see table 3-2 correspondence between address va lues and block numbers in flash memory . block 00h block 01h block 3bh 1 kb efffh 07ffh 0000h 0400h 03ffh ec00h ebffh chapter 3 cpu architecture user?s manual u18329ej4v0ud 68 correspondence between the address values and block numbers in the flash memory are shown below. table 3-2. correspondence between address values and block number s in flash memory address value block number address value block number address value block number address value block number 0000h to 03ffh 00h 4000h to 43ffh 10h 8000h to 83ffh 20h c000h to c3ffh 30h 0400h to 07ffh 01h 4400h to 47ffh 11h 8400h to 87ffh 21h c400h to c7ffh 31h 0800h to 0bffh 02h 4800h to 4bffh 12h 8800h to 8bffh 22h c800h to cbffh 32h 0c00h to 0fffh 03h 4c00h to 4fffh 13h 8c00h to 8fffh 23h cc00h to cfffh 33h 1000h to 13ffh 04h 5000h to 53ffh 14h 9000h to 93ffh 24h d000h to d3ffh 34h 1400h to 17ffh 05h 5400h to 57ffh 15h 9400h to 97ffh 25h d400h to d7ffh 35h 1800h to 1bffh 06h 5800h to 5bffh 16h 9800h to 9bffh 26h d800h to dbffh 36h 1c00h to 1fffh 07h 5c00h to 5fffh 17h 9c00h to 9fffh 27h dc00h to dfffh 37h 2000h to 23ffh 08h 6000h to 63ffh 18h a000h to a3ffh 28h e000h to e3ffh 38h 2400h to 27ffh 09h 6400h to 67ffh 19h a400h to a7ffh 29h e400h to e7ffh 39h 2800h to 2bffh 0ah 6800h to 6bffh 1ah a800h to abffh 2ah e800h to ebffh 3ah 2c00h to 2fffh 0bh 6c00h to 6fffh 1bh ac00h to afffh 2bh ec00h to efffh 3bh 3000h to 33ffh 0ch 7000h to 73ffh 1ch b000h to b3ffh 2ch 3400h to 37ffh 0dh 7400h to 77ffh 1dh b400h to b7ffh 2dh 3800h to 3bffh 0eh 7800h to 7bffh 1eh b800h to bbffh 2eh 3c00h to 3fffh 0fh 7c00h to 7fffh 1fh bc00h to bfffh 2fh remark pd78f0471, 78f0481, 78f0491: block numbers 00h to 0fh pd78f0472, 78f0482, 78f0492: block numbers 00h to 17h pd78f0473, 78f0483, 78f0493: block numbers 00h to 1fh pd78f0474, 78f0484, 78f0494: block numbers 00h to 2fh pd78f0475, 78f0485, 78f0495: block numbers 00h to 3bh chapter 3 cpu architecture user?s manual u18329ej4v0ud 69 3.1.1 internal program memory space the internal program memory space stores the program and table data. normally, it is addressed with the program counter (pc). 78k0/lf3 products incorporate internal rom (flash memory), as shown below. table 3-3. intern al rom capacity internal rom part number structure capacity pd78f0471, 78f0481, 78f0491 16384 8 bits (0000h to 3fffh) pd78f0472, 78f0482, 78f0492 24576 8 bits (0000h to 5fffh) pd78f0473, 78f0483, 78f0493 32768 8 bits (0000h to 7fffh) pd78f0474, 78f0484, 78f0494 49152 8 bits (0000h to bfffh) pd78f0475, 78f0485, 78f0495 flash memory 61440 8 bits (0000h to efffh) the internal program memory space is divided into the following areas. (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vect or table area. the program start addresses for branch upon reset or generation of each interrupt reques t are stored in the vector table area. of the 16-bit address, the lower 8 bits are stored at ev en addresses and the higher 8 bits are stored at odd addresses. table 3-4. vector table vector table address interrupt source vector table address interrupt source 0000h reset input, poc, lvi, wdt 0022h inttm010 0004h intlvi 0024h note 1 intad note 1 0006h intp0 0026h intsr0 0008h intp1 0028h intrtc 000ah intp2 002ah inttm51 000ch intp3 002ch intkr 000eh intp4 002eh intrtci 0010h intp5 0030h note 2 intdsad note 2 0012h intsre6 0032h inttm52 0014h intsr6 0034h inttmh2 0016h intst6 0036h intmcg 0018h intcsi10/intst0 0038h intrin 001ah inttmh1 003ah intrerr/intgp/intrend /intdfull 001ch inttmh0 003ch intacsi 001eh inttm50 003eh brk 0020h inttm000 notes 1. pd78f048x and 78f049x only. 2. pd78f049x only. chapter 3 cpu architecture user?s manual u18329ej4v0ud 70 (2) callt instruction table area the 64-byte area 0040h to 007fh can st ore the subroutine entry address of a 1-byte call instruction (callt). (3) option byte area a 5-byte area of 0080h to 0084h and 1080h to 1084h can be used as an option byte ar ea. set the option byte at 0080h to 0084h when the boot swap is not used, and at 0080h to 0084h and 1080h to 1084h when the boot swap is used. for details, see chapter 27 option byte . (4) callf instruction entry area the area 0800h to 0fffh can perform a direct subrout ine call with a 2-byte ca ll instruction (callf). (5) on-chip debug security id setting area a 10-byte area of 0085h to 008eh and 1085h to 108eh can be used as an on-chip debug security id setting area. set the on-chip debug security id of 10 bytes at 0085h to 008eh when the boot swap is not used and at 0085h to 008eh and 1085h to 108eh when the boot swap is used. for details, see chapter 29 on-chip debug function . chapter 3 cpu architecture user?s manual u18329ej4v0ud 71 3.1.2 internal data memory space 78k0/lf3 products incorporate the following rams. (1) internal high-speed ram table 3-5. internal high-speed ram capacity part number internal high-speed ram pd78f0471, 78f0481, 78f0491 768 8 bits (fc00h to feffh) pd78f0472, 78f0482, 78f0492 pd78f0473, 78f0483, 78f0493 pd78f0474, 78f0484, 78f0494 pd78f0475, 78f0485, 78f0495 1024 8 bits (fb00h to feffh) this area cannot be used as a program area in which instructions are written and executed. the internal high-speed ram can also be used as a stack memory. (2) internal expansion ram table 3-6. internal expansion ram capacity part number internal expansion ram pd78f0471, 78f0481, 78f0491 pd78f0472, 78f0482, 78f0492 pd78f0473, 78f0483, 78f0493 ? pd78f0474, 78f0484, 78f0494 pd78f0475, 78f0485, 78f0495 1024 8 bits (f400h to f7ffh) the internal expansion ram can also be used as a normal data area similar to the internal high-speed ram, as well as a program area in which inst ructions can be written and executed. the internal expansion ram cannot be used as a stack memory. (3) lcd display ram lcd display ram is incorporated in the lcd cont roller/driver (see figure 18-5 lcd display ram). table 3-7. lcd display ram capacity part number internal expansion ram pd78f047x, 78f048x 40 8 bits (fa40h to fa67h) pd78f049x 32 8 bits (fa40h to fa5fh) 3.1.3 special function register (sfr) area on-chip peripheral hard ware special function registers (sfrs) ar e allocated in the area ff00h to ffffh (see table 3-8 special function register list in 3.2.3 special func tion registers (sfrs) ). caution do not access addresses to which sfrs are not assigned. chapter 3 cpu architecture user?s manual u18329ej4v0ud 72 3.1.4 data memory addressing addressing refers to the method of specifying the address of the instruction to be ex ecuted next or the address of the register or memory relevant to the execution of instructions. several addressing modes are provided for addressing the memo ry relevant to the executi on of instructions for the 78k0/lf3, based on operabilit y and other considerations. for areas cont aining data memory in particular, special addressing methods designed for the functions of special function registers (sfr) and general-purpose registers are available for use. figures 3-11 to 3-20 show corresponde nce between data memory and addressing. for details of each addressing mode, see 3.4 operand address addressing . figure 3-11. correspondence between data memory and addressing ( pd78f0471, 78f0481) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 768 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 16384 x 8 bits ffffh ff00h feffh fee0h fedfh 4000h 3fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing fa68h fa67h lcd display ram 40 8 bits fa40h fa3fh fa20h fa1fh fa00h f9ffh buffer ram 32 8 bits reserved fc00h fbffh reserved chapter 3 cpu architecture user?s manual u18329ej4v0ud 73 figure 3-12. correspondence between data memory and addressing ( pd78f0491) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 768 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 16384 x 8 bits ffffh ff00h feffh fee0h fedfh 4000h 3fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing fa60h fa5fh lcd display ram 32 8 bits fa40h fa3fh fa20h fa1fh fa00h f9ffh buffer ram 32 8 bits reserved note fc00h fbffh reserved note however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). chapter 3 cpu architecture user?s manual u18329ej4v0ud 74 figure 3-13. correspondence between data memory and addressing ( pd78f0472, 78f0482) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 24576 x 8 bits ffffh ff00h feffh fee0h fedfh 6000h 5fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing fa68h fa67h lcd display ram 40 8 bits fa40h fa3fh fa20h fa1fh fa00h f9ffh buffer ram 32 8 bits reserved fb00h faffh reserved chapter 3 cpu architecture user?s manual u18329ej4v0ud 75 figure 3-14. correspondence between data memory and addressing ( pd78f0492) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 24576 x 8 bits ffffh ff00h feffh fee0h fedfh 6000h 5fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing fa60h fa5fh lcd display ram 32 8 bits fa40h fa3fh fa20h fa1fh fa00h f9ffh buffer ram 32 8 bits reserved note fb00h faffh reserved note however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). chapter 3 cpu architecture user?s manual u18329ej4v0ud 76 figure 3-15. correspondence between data memory and addressing ( pd78f0473, 78f0483) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits ffffh ff00h feffh fee0h fedfh 8000h 7fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing fa68h fa67h lcd display ram 40 8 bits fa40h fa3fh fa20h fa1fh fa00h f9ffh buffer ram 32 8 bits reserved fb00h faffh reserved chapter 3 cpu architecture user?s manual u18329ej4v0ud 77 figure 3-16. correspondence between data memory and addressing ( pd78f0493) sfr addressing direct addressing register indirect addressing based addressing based indexed addressing special function registers (sfr) 256 x 8 bits internal high-speed ram 1024 x 8 bits general-purpose registers 32 x 8 bits reserved flash memory 32768 x 8 bits ffffh ff00h feffh fee0h fedfh 8000h 7fffh 0000h ff20h ff1fh fe20h fe1fh register addressing short direct addressing fa60h fa5fh lcd display ram 32 8 bits fa40h fa3fh fa20h fa1fh fa00h f9ffh buffer ram 32 8 bits reserved note fb00h faffh reserved note however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). chapter 3 cpu architecture user?s manual u18329ej4v0ud 78 figure 3-17. correspondence between data memory and addressing ( pd78f0474, 78f0484) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh c000h bfffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits reserved reserved flash memory 49152 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh fa00h f9ffh f400h f3ffh fb40h fa3fh fa20h fa1fh internal expansion ram 1024 8 bits reserved fb00h faffh fa68h fa67h lcd display ram 40 8 bits reserved chapter 3 cpu architecture user?s manual u18329ej4v0ud 79 figure 3-18. correspondence between data memory and addressing ( pd78f0494) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh c000h bfffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits reserved note reserved flash memory 49152 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh fa00h f9ffh f400h f3ffh fb40h fa3fh fa20h fa1fh internal expansion ram 1024 8 bits reserved fb00h faffh fa60h fa5fh lcd display ram 32 8 bits reserved note however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). chapter 3 cpu architecture user?s manual u18329ej4v0ud 80 figure 3-19. correspondence between data memory and addressing ( pd78f0475, 78f0485) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh f000h efffh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits reserved reserved flash memory 61440 8 bits register addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh fa00h f9ffh f400h f3ffh fb40h fa3fh fa20h fa1fh internal expansion ram 1024 8 bits reserved fb00h faffh fa68h fa67h lcd display ram 40 8 bits reserved chapter 3 cpu architecture user?s manual u18329ej4v0ud 81 figure 3-20. correspondence between data memory and addressing ( pd78f0495) special function registers (sfr) 256 8 bits short direct addressing sfr addressing ffffh ff20h ff1fh 0000h ff00h feffh fee0h fedfh fe20h fe1fh internal high-speed ram 1024 8 bits general-purpose registers 32 8 bits buffer ram 32 8 bits reserved note reserved register addressing direct addressing register indirect addressing based addressing based indexed addressing f800h f7ffh fa00h f9ffh f400h f3ffh fb40h fa3fh fa20h fa1fh internal expansion ram 1024 8 bits reserved fb00h faffh fa60h fa5fh lcd display ram 32 8 bits reserved f000h efffh flash memory 61440 8 bits note however, fa26h and fa27h can be used (see 13.3 registers used in 16-bit ? type a/d converter ). chapter 3 cpu architecture user?s manual u18329ej4v0ud 82 3.2 processor registers the 78k0/lf3 products incorporate t he following processor registers. 3.2.1 control registers the control registers control the program sequence, statuses and stack memory. the control registers consist of a program counter (pc), a program status word (psw) and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit regist er that holds the address information of the next program to be executed. in normal operation, pc is automatically incremented acco rding to the number of byte s of the instruction to be fetched. when a branch instruction is execut ed, immediate data and regi ster contents are set. reset signal generation sets the reset vector table va lues at addresses 0000h and 0001h to the program counter. figure 3-21. format of program counter 15 pc pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0 (2) program status word (psw) the program status word is an 8-bit r egister consisting of various flags set/reset by instruction execution. program status word contents are stored in the stack area upon vector interrupt request acknowledgment or push psw instruction execution and are restored upon ex ecution of the retb, reti and pop psw instructions. reset signal generation sets psw to 02h. figure 3-22. format of program status word ie z rbs1 ac rbs0 isp cy 70 0 psw (a) interrupt enable flag (ie) this flag controls the interrupt reques t acknowledge operations of the cpu. when 0, the ie flag is set to the interrupt disabled (di) state, and all maskable interrupt requests are disabled. when 1, the ie flag is set to the interrupt enabled (ei) state and interrupt request acknowledgment is controlled with an in-service priority flag (isp), an in terrupt mask flag for various interrupt sources, and a priority specification flag. the ie flag is reset (0) upon di instruction executi on or interrupt acknowledgment and is set (1) upon ei instruction execution. chapter 3 cpu architecture user?s manual u18329ej4v0ud 83 (b) zero flag (z) when the operation result is zero, this flag is se t (1). it is reset (0 ) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information that indicates t he register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bi t 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable ma skable vectored interrupts. when this flag is 0, low- level vectored interrupt requests specified by a priority specification flag register (pr0l, pr0h, pr1l, pr1h) (see 21.3 (3) priority specifi cation flag registers (pr0l, pr0h, pr1l, pr1h) ) can not be acknowledged. actual request acknowledgment is contro lled by the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) stack pointer (sp) this is a 16-bit register to hold the start address of t he memory stack area. only the internal high-speed ram area can be set as the stack area. figure 3-23. format of stack pointer 15 sp sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0 the sp is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. each stack operation saves/restores dat a as shown in figures 3-24 and 3-25. caution since reset signal genera tion makes the sp contents undefined, be sure to initialize the sp before using the stack. chapter 3 cpu architecture user?s manual u18329ej4v0ud 84 figure 3-24. data to be saved to stack memory (a) push rp instruction (when sp = fee0h) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) call, callf, callt instructions (when sp = fee0h) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) interrupt, brk instruct ions (when sp = fee0h) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u18329ej4v0ud 85 figure 3-25. data to be restored from stack memory (a) pop rp instruction (when sp = fedeh) register pair lower fee0h sp sp fee0h fedfh fedeh register pair higher fedeh (b) ret instruction (when sp = fedeh) pc15 to pc8 fee0h sp sp fee0h fedfh fedeh pc7 to pc0 fedeh (c) reti, retb instructions (when sp = feddh) pc15 to pc8 psw fedfh fee0h sp sp fee0h fedeh feddh pc7 to pc0 feddh chapter 3 cpu architecture user?s manual u18329ej4v0ud 86 3.2.2 general-purpose registers general-purpose registers are mapp ed at particular addresses (fee0h to feffh) of the data memory. the general-purpose registers consists of 4 bank s, each bank consisting of eight 8-bit r egisters (x, a, c, b, e, d, l, and h). each register can be used as an 8-bit register, and two 8-bit r egisters can also be used in a pair as a 16-bit register (ax, bc, de, and hl). these registers can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instructi on execution are set by the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program ca n be created by switching between a register for normal processing and a register for interrupts for each bank. figure 3-26. configuration of general-purpose registers (a) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h (b) absolute name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fef0h fee8h chapter 3 cpu architecture user?s manual u18329ej4v0ud 87 3.2.3 special function registers (sfrs) unlike a general-purpose register, each special f unction register has a special function. sfrs are allocated to the ff00h to ffffh areas in the cpu, and are allo cated to the 00h to 03h areas of lcdctl in the lcd controller/driver. special function registers can be manipulated like general -purpose registers, using o peration, transfer, and bit manipulation instructions. the manipulatable bit units, 1, 8, and 16, depend on the spec ial function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved by the assembler fo r the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved by the assembler fo r the 16-bit manipulation instruction operand (sfrp). when specifying an address, describe an even address. table 3-8 gives a list of the special f unction registers. the meanings of items in the table are as follows. ? symbol symbol indicating the address of a special function regist er. it is a reserved word in the ra78k0, and is defined as an sfr variable using the #pragma sfr directive in the cc78k0. when using the ra78k0, id78k0-qb, and sm+, symbols can be written as an instruction operand. ? r/w indicates whether the corresponding special f unction register can be read or written. r/w: read/write enable r: read only w: write only ? manipulatable bit units indicates the manipulatable bit unit (1, 8, or 16). ? ? ? indicates a bit unit for which manipulation is not possible. ? after reset indicates each register status upon reset signal generation. chapter 3 cpu architecture user?s manual u18329ej4v0ud 88 table 3-8. special function register list (1/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h receive buffer register 6 rxb6 r ? ? ffh ff01h port register 1 p1 r/w ? 00h ff02h port register 2 p2 r/w ? 00h ff03h port register 3 p3 r/w ? 00h ff04h port register 4 p4 r/w ? 00h ff05h transmit buffer register 6 txb6 r/w ? ? ffh ff06h 10-bit a/d conver sion result register note adcr r ? ? 0000h ff07h 8-bit a/d conversion result register h note adcrh r ? ? 00h ff08h port register 8 p8 r/w ? 00h ff09h port register 9 p9 r/w ? 00h ff0ah port register 10 p10 r/w ? 00h ff0bh port register 11 p11 r/w ? 00h ff0ch port register 12 p12 r/w ? 00h ff0dh port register 13 p13 r/w ? 00h ff0eh port register 14 p14 r/w ? 00h ff0fh port register 15 p15 r/w ? 00h ff10h ff11h 16-bit timer counter 00 tm00 r ? ? 0000h ff12h ff13h 16-bit timer capture/compare register 000 cr000 r/w ? ? 0000h ff14h ff15h 16-bit timer capture/compare register 010 cr010 r/w ? ? 0000h ff16h 8-bit timer counter 50 tm50 r ? ? 00h ff17h 8-bit timer compare register 50 cr50 r/w ? ? 00h ff18h 8-bit timer h compare register 00 cmp00 r/w ? ? 00h ff19h 8-bit timer h compare register 10 cmp10 r/w ? ? 00h ff1ah 8-bit timer h compare register 01 cmp01 r/w ? ? 00h ff1bh 8-bit timer h compare register 11 cmp11 r/w ? ? 00h ff1fh serial i/o shift register 10 sio10 r ? ? 00h ff20h port function register 1 pf1 r/w ? 00h ff21h port mode register 1 pm1 r/w ? ffh ff22h port mode register 2 pm2 r/w ? ffh ff23h port mode register 3 pm3 r/w ? ffh ff24h port mode register 4 pm4 r/w ? ffh ff28h port mode register 8 pm8 r/w ? ffh ff29h port mode register 9 pm9 r/w ? ffh ff2ah port mode register 10 pm10 r/w ? ffh ff2bh port mode register 11 pm11 r/w ? ffh ff2ch port mode register 12 pm12 r/w ? ffh ff2dh port mode register 13 pm13 r/w ? ffh ff2eh port mode register 14 pm14 r/w ? ffh ff2fh port mode register 15 pm15 r/w ? ffh note pd78f048x and 78f049x only. chapter 3 cpu architecture user?s manual u18329ej4v0ud 89 table 3-8. special function register list (2/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff30h internal high-speed oscillation trimming register hiotrm r/w ? ? 10h ff31h pull-up resistor option register 1 pu1 r/w ? 00h ff33h pull-up resistor option register 3 pu3 r/w ? 00h ff34h pull-up resistor option register 4 pu4 r/w ? 00h ff38h pull-up resistor option register 8 pu8 r/w ? 00h ff39h pull-up resistor option register 9 pu9 r/w ? 00h ff3ah pull-up resistor option register 10 pu10 r/w ? 00h ff3bh pull-up resistor option register 11 pu11 r/w ? 00h ff3ch pull-up resistor option register 12 pu12 r/w ? 00h ff3dh pull-up resistor option register 13 pu13 r/w ? 00h ff3eh pull-up resistor option register 14 pu14 r/w ? 00h ff3fh pull-up resistor option register 15 pu15 r/w ? 00h ff40h clock output selection register cks r/w ? 00h ff41h 8-bit timer compare register 51 cr51 r/w ? ? 00h ff42h 8-bit timer h mode register 2 tmhmd2 r/w ? 00h ff43h 8-bit timer mode control register 51 tmc51 r/w ? 00h ff44h 8-bit timer h compare register 02 cmp02 r/w ? ? 00h ff45h 8-bit timer h compare register 12 cmp12 r/w ? ? 00h ff47h mcg status register mc0str r ? 00h ff48h external interrupt risi ng edge enable register egp r/w ? 00h ff49h external interrupt fa lling edge enable register egn r/w ? 00h ff4ah mcg transmit buffer register mc0tx r/w ? ? ffh ff4bh mcg transmit bit count specification register mc0bit r/w ? ? 07h ff4ch mcg control register 0 mc0ctl0 r/w ? 10h ff4dh mcg control register 1 mc0ctl1 r/w ? ? 00h ff4eh mcg control register 2 mc0ctl2 r/w ? ? 1fh ff4fh input switch control register isc r/w ? 00h ff50h asynchronous serial interface operation mode register 6 asim6 r/w ? 01h ff51h 8-bit timer counter 52 tm52 r ? ? 00h ff53h asynchronous serial inte rface reception error status register 6 asis6 r ? ? 00h ff54h real-time counter clock selection register rtccl r/w ? 00h ff55h asynchronous serial in terface transmission status register 6 asif6 r ? ? 00h ff56h clock selection register 6 cksr6 r/w ? ? 00h ff57h baud rate generator control register 6 brgc6 r/w ? ? ffh ff58h asynchronous serial interface control register 6 asicl6 r/w ? 16h ff59h 8-bit timer compare register 52 cr52 r/w ? ? 00h ff5bh timer clock selection register 52 tcl52 r/w ? 00h ff5ch 8-bit timer mode control register 52 tmc52 r/w ? 00h chapter 3 cpu architecture user?s manual u18329ej4v0ud 90 table 3-8. special function register list (3/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff60h ff61h sub-count register rsubc r ? ? 0000h ff62h second count register sec r/w ? ? 00h ff63h minute count register min r/w ? ? 00h ff64h hour count register hour r/w ? ? 12h ff65h week count register week r/w ? ? 00h ff66h day count register day r/w ? ? 01h ff67h month count register month r/w ? ? 01h ff68h year count register year r/w ? ? 00h ff69h 8-bit timer h mode register 0 tmhmd0 r/w ? 00h ff6ah timer clock selection register 50 tcl50 r/w ? 00h ff6bh 8-bit timer mode control register 50 tmc50 r/w ? 00h ff6ch 8-bit timer h mode register 1 tmhmd1 r/w ? 00h ff6dh 8-bit timer h carrier control register 1 tmcyc1 r/w ? 00h ff6eh key return mode register krm r/w ? 00h ff6fh 8-bit timer counter 51 tm51 r ? ? 00h ff70h asynchronous serial interface operation mode register 0 asim0 r/w ? 01h ff71h baud rate generator control register 0 brgc0 r/w ? ? 1fh ff72h receive buffer register 0 rxb0 r ? ? ffh ff73h asynchronous serial inte rface reception error status register 0 asis0 r ? ? 00h ff74h transmit shift register 0 txs0 w ? ? ffh ff75h 16-bit ? a/d conversion end channel register note 1 addstr r ? ? 00h ff7ch ? a/d converter control register 0 note 1 addctl0 r/w ? 00h ff7dh ? a/d converter control register 1 note 1 addctl1 r/w ? 00h ff7eh 16-bit ? a/d conversion result register note 1 addcr r ? ? 0000h ff7fh 8-bit ? a/d conversion result register note 1 addcrh r ? ? 00h ff80h serial operation mode register 10 csim10 r/w ? 00h ff81h serial clock selection register 10 csic10 r/w ? 00h ff82h watch error correction register subcud r/w ? 00h ff84h transmit buffer register 10 sotb10 r/w ? ? 00h ff86h alarm minute register alarmwm r/w ? ? 00h ff87h alarm hour register alarmwh r/w ? ? 12h ff88h alarm week r egister alarmww r/w ? ? 00h ff89h real-time counter control register 0 rtcc0 r/w ? 00h ff8ah real-time counter control register 1 rtcc1 r/w ? 00h ff8bh real-time counter control register 2 rtcc2 r/w ? 00h ff8ch timer clock selection register 51 tcl51 r/w ? 00h ff8dh a/d converter mode register note 2 adm r/w ? 00h ff8eh analog input channel specification register note 2 ads r/w ? 00h ff8fh a/d port configuration register 0 note 2 adpc0 r/w ? 08h notes 1. pd78f049x only. 2. pd78f048x and 78f049x only. chapter 3 cpu architecture user?s manual u18329ej4v0ud 91 table 3-8. special function register list (4/5) address special function register (sfr) name symbol r/w manipulatable bit unit after reset ff90h serial operation mode specification register 0 csima0 r/w ? 00h ff91h serial status register 0 csis0 r/w ? 00h ff92h serial trigger register 0 csit0 r/w ? 00h ff93h division value selecti on register 0 brgca0 r/w ? ? 03h ff94h automatic data transfer address point specification register 0 adtp0 r/w ? ? 00h ff95h automatic data transfer interval specification register 0 adti0 r/w ? ? 00h ff96h serial i/o shift register 0 sioa0 r/w ? ? 00h ff97h automatic data transfer address count register 0 adtc0 r ? ? 00h ff99h watchdog timer enable register wdte r/w ? ? note 1 1ah/9ah ff9ah remote controller receive control register rmcn r/w ? 00h ff9bh remote controller receive data register rmdr r ? ? 00h ff9ch remote controller shift register receive counter register rmscr r ? ? 00h ff9fh clock operation mode select register oscctl r/w ? 00h ffa0h internal oscillation mode register rcm r/w ? 80h note 2 ffa1h main clock mode register mcm r/w ? 00h ffa2h main osc control register moc r/w ? 80h ffa3h oscillation stabilization time counter status register ostc r ? 00h ffa4h oscillation stabilization time select register osts r/w ? ? 05h ffa5h remote controller receive gphs compare register rmgphs r/w ? ? 00h ffa6h remote controller receive gphl compare register rmgphl r/w ? ? 00h ffa7h remote controller receive dls compare register rmdls r/w ? ? 00h ffa8h remote controller receive dll compare register rmdll r/w ? ? 00h ffa9h remote controller receive dh0s compare register rmdh0s r/w ? ? 00h ffaah remote controller receive dh0l compare register rmdh0l r/w ? ? 00h ffabh remote controller receive shift register rmsr r ? ? 00h ffach reset control flag register resf r ? ? 00h note 3 ffadh remote controller receive dh1s compare register rmdh1s r/w ? ? 00h ffaeh remote controller receive dh1l compare register rmdh1l r/w ? ? 00h ffafh remote controller receive end width select register rmer r/w ? ? 00h notes 1. the reset value of wdte is determined by the setting of the option byte. 2. the value of this register is 00h immediately after a reset release but automatically changes to 80h after oscillation accuracy stabilization of high-s peed internal oscillator has been waited. 3. the reset value of resf varies depending on the reset source. chapter 3 cpu architecture user?s manual u18329ej4v0ud 92 table 3-8. special function register list (5/5) manipulatable bit unit address special function regist er (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ffb0h lcd mode register lcdmd r/w ? 00h ffb1h lcd display mode register lcdm r/w ? 00h ffb2h lcd clock control register 0 lcdc0 r/w ? 00h ffb5h port function register 2 note 1 pf2 r/w ? 00h ffb6h port function register all pfall r/w ? 00h ffbah 16-bit timer mode control register 00 tmc00 r/w ? 00h ffbbh prescaler mode register 00 prm00 r/w ? 00h ffbch capture/compare control register 00 crc00 r/w ? 00h ffbdh 16-bit timer output control register 00 toc00 r/w ? 00h ffbeh low-voltage detection register lvim r/w ? 00h note 2 ffbfh low-voltage detection level selection register lvis r/w ? 00h note 2 ffe0h interrupt request flag register 0l if0 if0l r/w 00h ffe1h interrupt request flag register 0h if0h r/w 00h ffe2h interrupt request flag register 1l if1 if1l r/w 00h ffe3h interrupt request flag register 1h if1h r/w 00h ffe4h interrupt mask flag register 0l mk0 mk0l r/w ffh ffe5h interrupt mask flag register 0h mk0h r/w ffh ffe6h interrupt mask flag register 1l mk1 mk1l r/w ffh ffe7h interrupt mask flag register 1h mk1h r/w ffh ffe8h priority specification flag register 0l pr0 pr0l r/w ffh ffe9h priority specification flag register 0h pr0h r/w ffh ffeah priority specification flag register 1l pr1 pr1l r/w ffh ffebh priority specification flag register 1h pr1h r/w ffh fff0h internal memory size switching register note 3 ims r/w ? ? cfh fff4h internal expansion ram size switching register note 3 ixs r/w ? ? 0ch fff9h remote controller receive interrupt status register ints r ? 00h fffah remote controller receive interrupt status clear register intc r/w ? 00h fffbh processor clock control register pcc r/w ? 01h notes 1. pd78f047x and 78f048x only. 2. the reset values of lvim and lvis vary depending on the reset source. 3. regardless of the internal memory capacity, the init ial values of the internal memory size switching register (ims) and internal expansion ram size switchi ng register (ixs) of all products in the 78k0/lf3 are fixed (ims = cfh, ixs = 0ch). therefore, set the value corresponding to each product as indicated below. flash memory version (78k0/lf3) ims ixs rom capacity internal high-speed ram capacity internal expansion ram capacity pd78f0471, 78f0481, 78f0491 04h 16 kb 768 bytes pd78f0472, 78f0482, 78f0492 c6h 24 kb pd78f0473, 78f0483, 78f0493 c8h 0ch 32 kb ? pd78f0474, 78f0484, 78f0494 cch 48 kb pd78f0475, 78f0485, 78f0495 cfh 0ah 60 kb 1 kb 1 kb chapter 3 cpu architecture user?s manual u18329ej4v0ud 93 3.3 instruction address addressing an instruction address is determined by contents of the program counter (pc), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. when a branch instruction is executed, the branch destination information is set to pc and branched by the following addressing (for details of instructions, refer to the 78k/0 series instructions user?s manual (u12326e) ). 3.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displ acement value: jdisp8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data ( ? 128 to +127) and bit 7 becomes a sign bit. in other words, relative addressing consists of relati ve branching from the start address of the following instruction to the ? 128 to +127 range. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc + 15 0 876 s 15 0 pc jdisp8 when s = 0, all bits of are 0. when s = 1, all bits of are 1. pc indicates the start address of the instruction after the br instruction. ... chapter 3 cpu architecture user?s manual u18329ej4v0ud 94 3.3.2 immediate addressing [function] immediate data in the instruction word is tran sferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can be branched to the entire memory space. the callf !addr11 instruction is branc hed to the 0800h to 0fffh area. [illustration] in the case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr. in the case of callf !addr11 instruction 15 0 pc 87 70 fa 10?8 11 10 00001 643 callf fa 7?0 chapter 3 cpu architecture user?s manual u18329ej4v0ud 95 3.3.3 table indirect addressing [function] table contents (branch destinat ion address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation co de are transferred to the progr am counter (pc) and branched. this function is carried out when the ca llt [addr5] instruction is executed. this instruction references the address stored in the me mory table from 40h to 7fh, and allows branching to the entire memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4?0 operation code 15 1 addr5 01 00000000 65 0 0 ta 4?0 ... the value of the effective address is the same as that of addr5. 3.3.4 register addressing [function] register pair (ax) contents to be spec ified with an instruction word are trans ferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 chapter 3 cpu architecture user?s manual u18329ej4v0ud 96 3.4 operand address addressing the following methods are available to specify the r egister and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 implied addressing [function] the register that functions as an accumulator (a and ax) among the general-purpose registers is automatically (implicitly) addressed. of the 78k0/lf3 instruction word s, the following instructions employ implied addressing. instruction register to be s pecified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric va lues that become decimal correction targets ror4/rol4 a register for storage of di git data that undergoes digit rotation [operand format] because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit 8-bit multiply instruction, the pr oduct of the a register and x regi ster is stored in ax. in this example, the a and ax registers are specified by implied addressing. chapter 3 cpu architecture user?s manual u18329ej4v0ud 97 3.4.2 register addressing [function] the general-purpose register to be specified is accesse d as an operand with the regi ster bank select flags (rbs0 to rbs1) and the register s pecify codes of an operation code. register addressing is carried out when an instruction wi th the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described by absolute names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting c register as r operation code 0 1 1 0 0 0 1 0 register specify code incw de; when selecting de register pair as rp operation code 1 0 0 0 0 1 0 0 register specify code chapter 3 cpu architecture user?s manual u18329ej4v0ud 98 3.4.3 direct addressing [function] the memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op c ode 00000000 00h 11111110 feh [illustration] memory 0 7 addr16 (lower) addr16 (upper) op code chapter 3 cpu architecture user?s manual u18329ej4v0ud 99 3.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit data in an instruction word. this addressing is applied to the 256-byte space fe20h to ff1fh. internal high-speed ram and special function registers (sfrs) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressing is applied is a part of the overall sfr area. ports that are frequently accessed in a program and compare and capture regi sters of the timer/event counter are mapped in this area, allowing sfrs to be mani pulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see the [illustration] shown below. [operand format] identifier description saddr immediate data that indicate label or fe20h to ff1fh saddrp immediate data that indicate label or fe20h to ff1fh (even address only) [description example] mov 0fe30h, a ; when transferring the val ue of a register to the saddr (fe30h) operation code 1 1 1 1 0 0 1 0 op code 0 0 1 1 0 0 0 0 30h (saddr-offset) [illustration] 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0 when 8-bit immediate data is 00h to 1fh, = 1 chapter 3 cpu architecture user?s manual u18329ej4v0ud 100 3.4.5 special function register (sfr) addressing [function] a memory-mapped special function register (sfr) is addre ssed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffff h. however, the sfrs mapped at ff00h to ff1fh can be ac cessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special func tion register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 1 1110110 op c ode 0 0100000 20h (sfr-offset) [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 chapter 3 cpu architecture user?s manual u18329ej4v0ud 101 3.4.6 register indirect addressing [function] register pair contents specified by a register pair spec ify code in an instruction word and by a register bank select flag (rbs0 and rbs1) serve as an operand address for addressing the memory. this addressing can be carried out for all of the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 1 0 0 0 0 1 0 1 [illustration] 16 0 8 d 7 e 0 7 7 0 a de the contents of the memory addressed are transferred. memory the memory address specified with the register pair de chapter 3 cpu architecture user?s manual u18329ej4v0ud 102 3.4.7 based addressing [function] 8-bit immediate data is added as offset data to the content s of the base register, that is , the hl register pair in the register bank specifie d by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is performed by expanding the offs et data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all of the memory spaces. [operand format] identifier description ? [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 [illustration] 16 0 8 h 7 l 0 7 7 0 a hl the contents of the memory addressed are transferred. memory +10h chapter 3 cpu architecture user?s manual u18329ej4v0ud 103 3.4.8 based indexed addressing [function] the b or c register contents specified in an instruction word are added to the contents of the base register, that is, the hl register pair in the register bank specified by the register bank select flag (rbs0 and rbs1), and the sum is used to address the memory. addition is perform ed by expanding the b or c register contents as a positive number to 16 bits. a carry from the 16th bit is ignored. this addr essing can be carried out for all of the memory spaces. [operand format] identifier description ? [hl + b], [hl + c] [description example] mov a, [hl +b]; when selecting b register operation code 1 0 1 0 1 0 1 1 [illustration] 16 0 h 7 8 l 0 7 b + 0 7 7 0 a hl the contents of the memory addressed are transferred. memory chapter 3 cpu architecture user?s manual u18329ej4v0ud 104 3.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is sa ved/reset upon generation of an interrupt request. with stack addressing, only the internal high-speed ram area can be accessed. [description example] push de; when saving de register operation code 10110101 [illustration] e fee0h sp sp fee0h fedfh fedeh d memory 0 7 fedeh user?s manual u18329ej4v0ud 105 chapter 4 port functions 4.1 port functions there are two types of pin i/o buffer power supplies: av ref note and v dd . the relationship between these power supplies and the pins is shown below. table 4-1. pin i/o buffer power supplies power supply corresponding pins av ref note p20 to p27 v dd port pins other than p20 to p27 note pd78f048x and 78f049x only. the power supply is v dd with pd78f047x. 78k0/lf3 products are provid ed with the ports shown in figure 4-1, whic h enable variety of control operations. the functions of each port are shown in table 4-2. in addition to the func tion as digital i/o ports, these ports have several alternate f unctions. for details of the alternate functions, see chapter 2 pin functions . figure 4-1. port types port 1 p10 p17 p20 port 2 p27 port 9 p90 p93 port 10 p100 p103 port 13 p130 p133 port 14 p140 p143 port 15 p150 p153 port 11 p110 p113 p120 port 12 p124 p40 port 4 p47 p80 port 8 p83 p30 port 3 p34 chapter 4 port functions user?s manual u18329ej4v0ud 106 table 4-2. port functions (1/2) function name i/o function after reset alternate function p10 pcl p11 sck10 p12 si10/rxd0 p13 so10/txd0 p14 scka0/intp4 p15 sia0/ chapter 4 port functions user?s manual u18329ej4v0ud 107 table 4-2. port functions (2/2) function name i/o function after reset alternate function p80 to p83 i/o port 8. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg4 to seg7 p90 to p93 i/o port 9. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg8 to seg11 p100 to p103 i/o port 10. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg12 to seg15 p110, p111 seg16, seg17 p112 seg18/txd6 p113 i/o port 11. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg19/rxd6 p120 i/o intp0/exlvi p121 x1/ocd0a p122 x2/exclk/ocd0b p123 xt1 p124 input port 12. 1-bit i/o port and 4-bit input port. only for p120, use of an on-chip pull-up resistor can be specified by a software setting. input port xt2 p130 to p133 i/o port 13. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg20 to seg23 p140 to p143 i/o port 14. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg24 (ks0) to seg27 (ks3) p150 to p153 i/o port 15. 4-bit i/o port. input/output can be specified in 1-bit units. use of an on-chip pull-up resistor can be specified by a software setting. input port seg28 (ks4) to seg31 (ks7) chapter 4 port functions user?s manual u18329ej4v0ud 108 4.2 port configuration ports include the following hardware. table 4-3. port configuration item configuration control registers port mode register (pm1 to pm4, pm8 to pm15) port register (p1 to p4, p8 to p15) pull-up resistor option register (pu1, pu3, pu4, pu8 to pu15) port function register 1 (pf1) port function register 2 (pf2) note 1 port function register all (pfall) a/d port configuration register 0 (adpc0) note 2 port total: 62 pull-up resistor total: 50 notes 1. pd78f047x and 78f048x only 2. pd78f048x and 78f049x only chapter 4 port functions user?s manual u18329ej4v0ud 109 4.2.1 port 1 port 1 is an 8-bit i/o port with an output latch. port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (pm1). when the p10 to p17 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (pu1). this port can also be used for serial clock i/o, serial interface data i/o, and maskable external interrupt input. reset signal generation sets port 1 to input mode. figures 4-2 to 4-7 show block diagrams of port 1. caution to use p11/sck10, p12/si10/rxd0, and p 13/so10/txd0 as general-purpose ports, set serial operation mode register 10 (csim10) and serial clock selection register 10 (csic10) to the default status (00h). figure 4-2. block diagram of p10 p10/pcl wr pu rd wr port wr pm pu10 pm10 v dd p-ch pu1 pm1 p1 output latch (p10) internal bus alternate function selector p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 110 figure 4-3. block diagram of p11 and p14 p11/sck10, p14/scka0/intp4 wr pu rd wr port wr pm pu11, pu14 pm11, pm14 v dd p-ch pu1 pm1 p1 output latch (p11, p14) internal bus alternate function selector alternate function p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 111 figure 4-4. block diagram of p12 and p15 wr pu rd pu1 pm1 wr port wr pm v dd p-ch p1 pu12, pu15 pm12, pm15 p12/si10/rxd0, p15/sia0/ chapter 4 port functions user?s manual u18329ej4v0ud 112 figure 4-5. block diagram of p13 p13/so10/txd0 wr pu rd wr port wr pm pu13 pm13 v dd p-ch pu1 pm1 p1 pf13 pf1 wr pf internal bus output latch (p13) serial interface csi10 serial interface uart0 selector selector p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 pf1: port function register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 113 figure 4-6. block diagram of p16 p16/soa0/ chapter 4 port functions user?s manual u18329ej4v0ud 114 figure 4-7. block diagram of p17 rd p17 p-ch wr pu wr port wr pm pu17 pm17 v dd pu1 pm1 p1 output latch (p17) internal bus selector p1: port register 1 pu1: pull-up resistor option register 1 pm1: port mode register 1 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 115 4.2.2 port 2 port 2 is an 8-bit i/o port with an output latch. port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (pm2). this port can also be used for 10-bit successi ve approximation type a/d converter, 16-bit ? type a/d converter analog input, and segment output. to use p20/ani0/ds0 ? , p21/ani1/ds0+, p22/ani2/ds1 ? , p23/ani3/ds1+, p24/ani4/ds2 ? , p25/ani5/ds2+, p26/ani6/ref ? , and p27/ani7/ref+ as digital input pins, set them to port function (other than segment output) by using the port function register 2 (pf2), to digital i/o by using adpc0, and to input mode by using pm2. use these pins starting from the lower bit. p20/ani0/ds0 ? , p21/ani1/ds0+, p22/ani2/ds1 ? , p23/ani3/ds1+, p24/ani4/ds2 ? , p25/ani5/ds2+, p26/ani6/ref ? , and p27/ani7/ref+ as digital output pins, set them to port function (other than segment output) by using the port function register 2 (pf2 ), to digital i/o by using adpc0, and to output mode by using pm2. use these pins starting from the lower bit. reset signal generation sets port 1 to input mode. figure 4-8 shows block diagrams of port 2. table 4-4. setting functions of p20/seg39 note 1 /ani0 note 2 /ds0 ? note 3 to p27/seg32 note 1 /ani7 note 2 /ref+ note 3 pins pf2 adpc0 pm2 ads addctl0 p20/seg39 note 1 /ani0 note 2 /ds0 ? note 3 to p27/seg32 note 1 /ani7 note 2 /ref+ note 3 pins does not select ani. does not select dsn . analog input (not to be converted) selects ani. does not select dsn . analog input (to be converted by successive approximation type a/d converter) does not select ani. selects dsn . analog input (to be converted by ? type a/d converter) input mode selects ani. selects dsn . setting prohibited analog input selection output mode ? setting prohibited input mode ? digital input digital/analog selection digital i/o selection output mode ? digital output seg output selection note 1 ? ? ? segment output note 1 notes 1. pd78f047x and 78f048x only. 2. pd78f048x and 78f049x only. 3. pd78f049x only. remark n = 0 to 2 chapter 4 port functions user?s manual u18329ej4v0ud 116 figure 4-8. block diagram of p20 to p27 p20/seg39/ani0/ds0- to p27/seg32/ani7/ref+ rd wr port wr pm output latch (p20 to p27) pm20 to pm27 pm2 wr pf pf2 lcd controller/driver selector selector internal bus p2 a/d converter pf20 to pf27 p2: port register 2 pm2: port mode register 2 pf2: port function register 2 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 117 4.2.3 port 3 port 3 is a 5-bit i/o port with an output latch. port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (pm3). when the p30 to p34 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (pu3). this port can also be used for external interrupt request input, timer i/o, manchester code generator output, real- time counter output, and buzzer output. reset signal generation sets port 3 to input mode. figures 4-9 and 4-11 show block diagrams of port 3. figure 4-9. block diagram of p30 p30/intp5 wr pu rd wr port wr pm pu30 pm30 v dd p-ch pu3 pm3 p3 output latch (p30) internal bus selector alternate function p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 118 figure 4-10. block diag ram of p31, p33, p34 wr pu rd wr port wr pm v dd p-ch pu3 pm3 p3 p31/toh1/intp3, p33/ti000/rtcdiv/rtccl/buz/intp2, p34/ti52/ti010/to00/rtc1hz/intp1 pu31, pu33, pu34 pm31, pm33, pm34 output latch (p31, p33, p34) internal bus selector alternate function alternate function p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 119 figure 4-11. blo ck diagram of p32 p32/toh0/mcgo wr pu rd wr port wr pm pu32 pm32 v dd p-ch pu3 pm3 p3 output latch (p32) internal bus selector alternate function p3: port register 3 pu3: pull-up resistor option register 3 pm3: port mode register 3 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 120 4.2.4 port 4 port 4 is an 8-bit i/o port with an output latch. port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (pm4). when the p40 to p47 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (pu4). this port can also be used for key interrupt input, segm ent key scan input, timer i/o, remote control receive data input, and power supply voltage for driving the lcd. reset signal generation sets port 4 to input mode. figures 4-12 to 4-14 show a block diagram of port 4. figure 4-12. block diagram of p40 p40/v lc3 /kr0 wr pu rd wr port wr pm pu40 alternate function output latch (p40) pm40 v dd p-ch selector internal bus pu4 pm4 p4 selector v lc3 lcdm lcdm0 to lcdm2 p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 lcdm: lcd display mode register rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 121 figure 4-13. block diagram of p41, p42, p45 to p47 wr pu rd pu4 pm4 wr port wr pm v dd p-ch p4 p41/rin/kr1, p42/kr2, p45/kr5 to p47/kr7 pu41, pu42, pu45-pu47 output latch (p41, p42, p45 to p47) pm41, pm42, pm45-pm47 internal bus selector alternate function p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 122 figure 4-14. block diagram of p43 and p44 wr pu rd wr port wr pm v dd p-ch pu4 pm4 p4 pu43, pu44 pm43, pm44 p43/to51/ti51/kr3, p44/to50/ti50/kr4 internal bus selector alternate function alternate function output latch (p43, p44) p4: port register 4 pu4: pull-up resistor option register 4 pm4: port mode register 4 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 123 4.2.5 port 8 port 8 is a 4-bit i/o port with an output latch. port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (pm8). when the p80 to p83 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 8 (pu8). this port can also be used for segment output. reset signal generation sets port 8 to input mode. figure 4-15 shows a block diagram of port 8. figure 4-15. block diag ram of p80 to p83 p80/seg4 to p83/seg7 rd wr port wr pm output latch (p80 to p83) pm80 to pm83 pm8 wr pu pu80 to pu83 p-ch pu8 selector selector internal bus p8 lcd controller/driver wr pf pf08all pfall v dd p8: port register 8 pu8: pull-up resistor option register 8 pm8: port mode register 8 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 124 4.2.6 port 9 port 9 is a 4-bit i/o port with an output latch. port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (pm9). when the p90 to p93 pi ns are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 9 (pu9). this port can also be used for segment output. reset signal generation sets port 9 to input mode. figure 4-16 shows block diagrams of port 9. figure 4-16. block diag ram of p90 to p93 p90/seg8 to p93/seg11 rd wr port wr pm output latch (p90 to p93) pm90 to pm93 pm9 wr pu pu90 to pu93 p-ch pu9 selector selector internal bus p9 v dd wr pf pf09all pfall lcd controller/driver p9: port register 9 pu9: pull-up resistor option register 9 pm9: port mode register 9 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 125 4.2.7 port 10 port 10 is a 4-bit i/o port with an output latch. port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (pm10). when the p100 to p1 03 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 10 (pu10). this port can also be used for segment output. reset signal generation sets port 10 to input mode. figure 4-17 shows a block diagram of port 10. figure 4-17. block di agram of p100 to p103 p100/seg12 to p103/seg15 rd wr port wr pm output latch (p100 to p103) pm100 to pm103 pm10 wr pu pu100 to pu103 p-ch pu10 selector selector internal bus p10 v dd wr pf pf10all pfall lcd controller/driver p10: port register 10 pu10: pull-up resistor option register 10 pm10: port mode register 10 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 126 4.2.8 port 11 port 11 is a 4-bit i/o port with an output latch. port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (pm11). when the p110 to p1 13 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 11 (pu11). this port can also be used for segment output and serial interface data i/o. reset signal generation sets port 11 to input mode. figures 4-18 to 4-20 show a block diagram of port 11. figure 4-18. block di agram of p110 and p111 p110/seg16, p111/seg17 rd wr port wr pm output latch (p110, p111) pm110, pm111 pm11 wr pu pu110, pu111 p-ch pu11 selector selector internal bus p11 v dd lcd controller/driver wr pf pf11all pfall p11: port register 11 pu11: pull-up resistor option register 11 pm11: port mode register 11 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 127 figure 4-19. blo ck diagram of p112 p112/seg18/txd6 rd wr port wr pm output latch (p112) pm112 pm11 wr pu pu112 p-ch pu11 selector selector internal bus p11 v dd alternate function lcd controller/driver wr pf pf11all pfall p11: port register 11 pu11: pull-up resistor option register 11 pm11: port mode register 11 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 128 figure 4-20. blo ck diagram of p113 p113/seg19/rxd6 rd wr port wr pm output latch (p113) pm113 pm11 wr pu pu113 p-ch pu11 selector selector internal bus p11 alternate function wr pf pf11all pfall lcd controller/driver v dd p11: port register 11 pu11: pull-up resistor option register 11 pm11: port mode register 11 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 129 4.2.9 port 12 port 12 is a 1-bit i/o port with an output latch and a 4-bit i nput port. only p120 can be set to the input mode or output mode in 1-bit units using port mode register 12 (pm12). when used as an input port only for p120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (pu12). this port can also be used as pins for external interru pt request input, potential input for external low-voltage detection, connecting resonator for main system clock, c onnecting resonator for subsystem clock, and external clock input for main system clock. reset signal generation sets port 12 to input mode. figures 4-21 to 4-23 show block diagrams of port 12. caution when using the p121 to p124 pins to connect a resonator for th e main system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an ext ernal clock for the main system clock (exclk), the x1 oscillation mode, xt1 osc illation mode, or external clock input mode must be set by using the clock operation mode select register (oscctl) (for details, see 5.3 (1) clock operation mode select register (oscctl) and (3) setting of operation mode for subsystem clock pin). the reset value of oscctl is 00h (all of the p121 to p124 pins are input port pins). remark p121 and p122 can be used as on-chip debug mode setting pins (ocd0a, ocd0b) when the on-chip debug function is used. for detail, see chapter 29 on-chip debug function. chapter 4 port functions user?s manual u18329ej4v0ud 130 figure 4-21. blo ck diagram of p120 wr pu rd pu12 pm12 wr port wr pm v dd p-ch p12 pu120 pm120 p120/intp0/exlvi output latch (p120) internal bus selector alternate function p12: port register 12 pu12: pull-up resistor option register 12 pm12: port mode register 12 rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 131 figure 4-22. block di agram of p121 and p122 p122/x2/exclk/ocd0b rd exclk, oscsel oscctl oscsel oscctl p121/x1/ocd0a rd internal bus oscctl: clock operation mode select register rd: read signal chapter 4 port functions user?s manual u18329ej4v0ud 132 figure 4-23. block di agram of p123 and p124 p124/xt2 rd oscsels oscctl oscsels oscctl p123/xt1 rd internal bus oscctl: clock operation mode select register rd: read signal chapter 4 port functions user?s manual u18329ej4v0ud 133 4.2.10 port 13 port 13 is a 4-bit i/o port with an output latch. port 13 can be set to the input mode or output mode in 1-bit units using port mode register 13 (pm13). when the p130 to p1 33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 13 (pu13). this port can also be used for segment output. reset signal generation sets port 13 to input mode. figure 4-24 shows a block diagram of port 13. figure 4-24. block di agram of p130 to p133 p130/seg20 to p133/seg23 rd wr port wr pm output latch (p130 to p133) pm130 to pm133 pm13 wr pu pu130 to pu133 p-ch pu13 selector selector internal bus p13 v dd lcd controller/driver wr pf pf13all pfall p13: port register 13 pu13: pull-up resistor option register 13 pm13: port mode register 13 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 134 4.2.11 port 14 port 14 is a 4-bit i/o port with an output latch. port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (pm14). when the p140 to p1 43 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (pu14). this port can also be used for segment output. reset signal generation sets port 14 to input mode. figure 4-25 shows a block diagram of port 14. figure 4-25. block di agram of p140 and p143 p140/seg24 (ks0) to p143/seg27 (ks3) rd wr port wr pm output latch (p140 to p143) pm140 to pm143 pm14 wr pu pu140 to pu143 p-ch pu14 selector selector internal bus p14 v dd lcd controller/driver wr pf pf14all pfall p14: port register 14 pu14: pull-up resistor option register 14 pm14: port mode register 14 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 135 4.2.12 port 15 port 15 is a 4-bit i/o port with an output latch. port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (pm15). when the p150 to p1 53 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 15 (pu15). this port can also be used for segment output. reset signal generation sets port 15 to input mode. figure 4-26 shows a block diagram of port 15. figure 4-26. block di agram of p150 and p153 p150/seg28 (ks4) to p153/seg31 (ks7) rd wr port wr pm output latch (p150 to p153) pm150 to pm153 pm15 wr pu pu150 to pu153 p-ch pu15 selector selector internal bus p15 v dd lcd controller/driver wr pf pf15all pfall p15: port register 15 pu15: pull-up resistor option register 15 pm15: port mode register 15 pfall: port function register all rd: read signal wr : write signal chapter 4 port functions user?s manual u18329ej4v0ud 136 4.3 registers controlling port function port functions are controlled by the following seven types of registers. ? port mode registers (pm1 to pm4, pm8 to pm15) ? port registers (p1 to p4, p8 to p15) ? pull-up resistor option registers (pu1, pu3, pu4, pu8 to pu15) ? port function register 1 (pf1) ? port function register 2 (pf2) note 1 ? port function register all (pfall) ? a/d port configuration register 0 (adpc0) note 2 notes 1. pd78f047x and 78f048x only 2. pd78f048x and 78f049x only (1) port mode registers (pm1 to pm4, pm8 to pm15) these registers specify input or output mode for the port in 1-bit units. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. when port pins are used as alternate-function pi ns, set the port mode register by referencing 4.5 settings of pfall, pf2, pf1, isc, port mode register, and output latch when using alternate function . chapter 4 port functions user?s manual u18329ej4v0ud 137 figure 4-27. format of port mode register 7 pm17 symbol pm1 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 address ff21h after reset ffh r/w r/w pm27 pm2 pm26 pm25 pm24 pm47 pm46 pm45 pm44 1111 1111 pm23 pm22 pm21 pm20 ff22h ffh r/w 1 pm3 1 1 pm34 pm33 pm32 pm31 pm30 ff23h ffh r/w pm4 pm43 pm42 pm41 pm40 ff24h ffh r/w pm8 pm83 pm82 pm81 pm80 ff28h ffh r/w pm9 pm93 pm92 pm91 pm90 ff29h ffh r/w 1 pm10 1 1 1 pm103 pm102 1 1 pm143 pm142 pm101 pm100 ff2ah ffh r/w 1 pm12 1 1 1 1 1 1 pm120 ff2ch ffh r/w 1 pm14 1 pm141 pm140 ff2eh ffh r/w 1 pm11 1 1 1 pm113 pm112 pm111 pm110 ff2bh ffh r/w 1 pm13 1 1 1 pm133 pm132 pm131 pm130 ff2dh ffh r/w 1 1 pm153 pm152 1 pm15 1 pm151 pm150 ff2fh ffh r/w pmmn pmn pin i/o mode selection (m = 1 to 4, 8 to 15; n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) caution be sure to set bits 5 to 7 of pm3, bits 4 to 7 of pm8, bits 4 to 7 of pm9, bits 4 to 7 of pm10, bits 4 to 7 of pm11, bits 1 to 7 of pm12, bits 4 to 7 of pm13, bits 4 to 7 of pm14, and bits 4 and 7 of pm15 to ?1?. chapter 4 port functions user?s manual u18329ej4v0ud 138 (2) port registers (p1 to p4, p8 to p15) these registers write the data t hat is output from the chip when data is output from a port. if the data is read in the input mode, the pin level is read. if it is read in the output mode, the output latch value is read. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-28. format of port register 7 p17 symbol p1 6 p16 5 p15 4 p14 3 p13 2 p12 1 p11 0 p10 address ff01h after reset 00h (output latch) r/w r/w r/w p27 p2 p26 p25 p24 p47 p46 p45 p44 0000 0000 p23 p22 p21 p20 ff02h 00h (output latch) 0 p3 0 0 p34 p33 p32 p31 p30 ff03h 00h (output latch) r/w p4 p43 p42 p41 p40 ff04h 00h (output latch) r/w p8 p83 p82 p81 p80 ff08h 00h (output latch) r/w p9 p93 p92 p91 p90 ff09h 00h (output latch) r/w 0 p10 0 0 0 p103 p102 pk141 note 3 pk140 note 3 p143 p142 p101 p100 ff0ah 00h (output latch) r/w 0 p12 00 p124 note 2 p123 note 2 p122 note 2 p121 note 2 p120 ff0ch 00h note 1 (output latch) r/w note 1 0 p13 0 0 0 p133 p132 p131 p130 ff0dh 00h (output latch) r/w pk143 note 3 p14 pk142 note 3 p141 p140 ff0eh 00h (output latch) r/w 0 p11 0 0 0 p113 p112 p111 p110 ff0bh 00h (output latch) r/w pk151 note 3 pk150 note 3 p153 p152 pk153 note 3 p15 pk152 note 3 p151 p150 ff0fh 00h (output latch) r/w m = 1 to 4, 8 to 15; n = 0 to 7 pmn output data control (in output mode) input data read (in input mode) 0 output 0 input low level 1 output 1 input high level notes 1. p121 to p124 are read-only. these become undefined at reset. 2. when the operation mode of the pin is t he clock input mode, 0 is always read. 3. this bit is used for the segment key scan function. for details, see 18.3 registers controlling lcd controller/driver . chapter 4 port functions user?s manual u18329ej4v0ud 139 (3) pull-up resistor option register s (pu1, pu3, pu4, pu8 to pu15) these registers specify whether the on-ch ip pull-up resistors of p10 to p17, p 30 to p34, p40 to p47, p80 to p83, p90 to p93, p100 to p103, p110 to p113, p120, p130 to p1 33, p140 to p143, or p150 to p153 are to be used or not. on-chip pull-up resistors can be used in 1-bit units onl y for the bits set to input m ode of the pins to which the use of an on-chip pull-up resistor has been specified in pu1, pu3, pu4, and pu8 to pu15. on-chip pull-up resistors cannot be connected to bits set to output mo de and bits used as alternate-function output pins, regardless of the settings of pu1, pu3, pu4, and pu8 to pu15. these registers can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 4-29. format of pull-up resistor option register 7 pu17 symbol pu1 6 pu16 5 pu15 4 pu14 3 pu13 2 pu12 1 pu11 0 pu10 address ff31h after reset 00h r/w r/w pu47 note pu46 note pu45 note pu44 note 0000 0000 0 pu3 0 0 pu34 pu33 pu32 pu31 pu30 ff33h 00h r/w pu4 pu43 note pu42 note pu41 note pu40 note ff34h 00h r/w pu8 pu83 pu82 pu81 pu80 ff38h 00h r/w pu9 pu93 pu92 pu91 pu90 ff39h 00h r/w 0 pu10 0 0 0 pu103 pu102 0 0 pu143 pu142 pu101 pu100 ff3ah 00h r/w 0 pu12 0 0 0 0 0 0 pu120 ff3ch 00h r/w 0 pu14 0 pu141 pu140 ff3eh 00h r/w 0 pu13 0 0 0 pu133 pu132 pu131 pu130 ff3dh 00h r/w 0 0 pu153 pu152 0 pu15 0 pu151 pu150 ff3fh 00h r/w 0 pu11 0 0 0 pu113 pu112 pu111 pu110 ff3bh 00h r/w pumn pmn pin on-chip pull-up resistor selection (m = 1, 3, 4, 8 to 15; n = 0 to 7) 0 on-chip pull-up resistor not connected 1 on-chip pull-up resistor connected note for setting when using the segment key scan function, see 18.3 registers controlling lcd controller/driver . chapter 4 port functions user?s manual u18329ej4v0ud 140 (4) port function register 1 (pf1) this register sets the pin functions of p13/so10/txd0 and p16/soa0/txd6 pins. pf1 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pf1 to 00h. figure 4-30. format of port function register 1 (pf1) address: ff20h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pf1 0 pf16 0 0 pf13 0 0 0 pf16 port (p16), csia0, and uart6 output specification 0 used as p16 or soa0 1 used as txd6 pf13 port (p13), csi10, and uart0 output specification 0 used as p13 or so10 1 used as txd0 (5) port function register 2 (pf2) ( pd78f047x and 78f048x only) this register sets whether to use pins p20 to p27 as port pins (other than segm ent output pins) or segment output pins. pf2 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pf2 to 00h. figure 4-31. format of port function register 2 (pf2) address: ffb5h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pf2 pf27 pf26 pf25 pf 24 pf23 pf22 pf21 pf20 pf2n port/segment output specification 0 used as port (other than segment output) 1 used as segment output remark n = 0 to 7 chapter 4 port functions user?s manual u18329ej4v0ud 141 (6) port function register all (pfall) this register sets whether to use pins p8 to p11 and p13 to p15 as port pins (other than segment output pins) or segment output pins. pfall is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pfall to 00h. figure 4-32. format of port function register all (pfall) address: ffb6h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pfall 0 pf15all pf14all pf13all pf11all pf10all pf09all pf08all pfnall port/segment output specification 0 used as port (other than segment output) 1 used as segment output remark n = 08 to 11, 13 to 15 chapter 4 port functions user?s manual u18329ej4v0ud 142 (7) a/d port configuration register 0 (adpc0) ( pd78f048x and 78f049x only) this register switches the p20/ani0 to p27/ani7 pins to analog in put of a/d converter or digital i/o of port. adpc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 08h. figure 4-33. format of a/d port configuration register 0 (adpc0) adpc00 adpc01 adpc02 adpc03 0 0 0 0 digital i/o (d)/analog input (a: successive setting prohibited adpc03 0 1 2 3 4 5 6 7 adpc0 address: ff8fh after reset: 08h r/w symbol p27/ ani7/ ref+ a/ a/ a/ a/ a/ a a a d p26/ ani6/ ref- a/ a/ a/ a/ a/ a a d d p25/ ani5/ ds2+ a/ a/ a/ a/ a/ a d d d p24/ ani4/ ds2- a/ a/ a/ a/ a/ d d d d p23/ ani3/ ds1+ a/ a/ a/ a d d d d d p22/ ani2/ ds1- a/ a/ a/ d d d d d d p21/ ani1/ ds0+ a/ a d d d d d d d p20/ ani0/ ds0- a/ d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc02 0 0 0 0 1 1 1 1 0 adpc01 0 0 1 1 0 0 1 1 0 adpc00 0 1 0 1 0 1 0 1 0 other than above approximation type, : ? type) switching cautions 1. set the channel used for a/d conversion to the input mode by using port mode register 2 (pm2). 2. the pin to be set as a digital i/o via adp c, must not be set via ads, adds1 or adds0. 3. if data is written to adpc0, a wait cycle is generated. do not write data to adpc0 when the cpu is operating on the subsystem clock and the peripheral hardware clo ck is stopped. for details, see chapter 34 cautions for wait. 4. if pins ani0/p20/seg39 to ani7/p27/seg32 are set to segment output via the pf2 register, output is set to segment output, regardless of the adpc0 setting (for pd78f048x only). chapter 4 port functions user?s manual u18329ej4v0ud 143 4.4 port function operations port operations differ depending on whether the inpu t or output mode is set, as shown below. caution in the case of 1-bit memory manipulation instru ction, although a single bit is manipulated, the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.1 writing to i/o port (1) output mode a value is written to the output latch by a transfer instruct ion, and the output latch content s are output from the pin. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is reta ined until data is written to the output latch again. 4.4.2 reading from i/o port (1) output mode the output latch contents ar e read by a transfer instruction. t he output latch content s do not change. (2) input mode the pin status is read by a transfer instruct ion. the output latch c ontents do not change. 4.4.3 operations on i/o port (1) output mode an operation is performed on the output latch contents, and the result is wr itten to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is reta ined until data is written to the output latch again. the data of the output latch is clear ed when a reset signal is generated. (2) input mode the pin level is read and an operation is performed on its cont ents. the result of the op eration is written to the output latch, but since the output buffer is off, the pin status does not change. 4.5 settings of pfall, pf2, pf1, isc, port mode register, and output latch when using alternate function to use the alternate function of a por t pin, set the pfall, pf2, pf1, isc, port mode register, and output latch as shown in table 4-5. chapter 4 port functions user?s manual u18329ej4v0ud 144 table 4-5. settings of pfall, pf2, pf1, isc, po rt mode register, and output latch when using alternate function (1/2) alternate function pin name function name i/o pfall, pf2 note 4 pf1 isc pm p p10 pcl output ? 0 0 input ? 1 p11 sck10 output ? 0 1 si10 input ? 1 p12 rxd0 input ? 1 so10 output ? pf13 = 0 0 0 p13 note 10 txd0 output ? pf13 = 1 0 input ? 1 scka0 output ? 0 1 p14 intp4 input ? 1 sia0 input ? 1 p15 chapter 4 port functions user?s manual u18329ej4v0ud 145 table 4-5. settings of pfall, pf2, pf1, isc, po rt mode register, and output latch when using alternate function (2/2) alternate function pin name function name i/o pfall, pf2 note 4 isc pm p kr0 input ? 1 p40 v lc3 note 9 input ? kr1 input ? 1 p41 rin input ? 1 p42 kr2 input ? 1 kr3 input ? 1 ti51 input ? 1 p43 to51 output ? 0 0 kr4 input ? 1 ti50 input ? 1 p44 to50 output ? 0 0 p45 kr5 input ? 1 p46 kr6 input ? 1 p47 kr7 input ? 1 p80 to p83 seg4 to seg7 output 1 p90 to p93 seg8 to seg11 output 1 p100 to p103 seg12 to seg15 output 1 p110 seg16 output 1 isc3 = 0 p111 seg17 output 1 isc3 = 0 seg18 output 1 isc3 = 0 p112 txd6 output 0 isc3 = 1, isc4 = isc5 = 0 0 1 seg19 output 1 isc3 = 0 p113 rxd6 input 0 isc3 = 1, isc4 = isc5 = 0 notes 5, 7 1 exlvi input ? 1 p120 intp0 input ? isc0 = 0 1 x1 note 3 ? ? p121 ocd0a ? ? x2 note 3 ? ? exclk note 3 input ? p122 ocd0b ? ? p123 xt1 note 3 ? ? p124 xt2 note 3 ? ? p130 to p133 seg20 to seg23 output 1 p140 to p143 seg24 (ks0) to seg27 (ks3) output 1 p150 to p153 seg28 (ks4) to seg31 (ks7) output 1 (note and remark are listed on the next page.) chapter 4 port functions user?s manual u18329ej4v0ud 146 notes 1. pd78f048x and 78f049x only. 2. the functions of the p20/ani0/ds0 ? , p21/ani1/ds0+, p22/ani2/ds1 ? , p23/ani3/ds1+, p24/ani4/ds2 ? , p25/ani5/ds2+, p26/ani6/ref ? , and p27/ani7/ref+ pins are determined according to the settings of port function register 2 (pf2), a/d port configuration register 0 (adpc0), port mode register 2 (pm2), analog input c hannel specification register (ads), and ? a/d converter mode register 0 (addctl0). table 4-6. setting functions of p20/seg39 note 1 /ani0 note 2 /ds0 ? note 3 to p27/seg32 note 1 /ani7 note 2 /ref+ note 3 pins pf2 note 1 adpc0 pm2 ads addctl0 p20/seg39 note 1 /ani0 note 2 /ds0 ? note 3 to p27/seg32 note 1 /ani7 note 2 /ref+ note 3 pins does not select ani. does not select dsn . analog input (not to be converted) selects ani. does not select dsn . analog input (to be converted by successive approximation type a/d converter) does not select ani. selects dsn . analog input (to be converted by 16-bit ? type a/d converter) input mode selects ani. selects dsn . setting prohibited analog input selection output mode ? setting prohibited input mode ? digital input digital/analog selection digital i/o selection output mode ? digital output seg output selection note 1 ? ? ? segment output note 1 notes 1. pd78f047x and 78f048x only. 2. pd78f048x and 78f049x only. 3. pd78f049x only. remark n = 0 to 2 3. when using the p121 to p124 pins to connect a re sonator for the main system clock (x1, x2) or subsystem clock (xt1, xt2), or to input an external clock for the main system clock (exclk), the x1 oscillation mode, xt1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (oscctl) (for details, see 5.3 (1) clock operation mode select register (oscctl) and (3) setting of operation mode for subsystem clock pin ). the reset value of oscctl is 00h (all of the p121 to p124 are input port pins). 4. targeted at registers corresponding to each port. 5. rxd6 can be set as the input source for ti000 by setting isc1 = 1. 6. input enable of tm52 via tmh2 can be controlled by setting isc2 = 1. 7. rxd6 can be set as the input source for intp0 by setting isc0 = 1. 8. pd78f049x only. 9. when the p40/kr0/v lc3 pin is set to the 1/4 bias method, it is used as v lc3 . when the pin is set to another bias method, it is used for the port func tion (p40) or the key interrupt function (kr0). 10. set pf13 = 0 when using as port function. 11. set pf16 = 0 when using as port function. 12. pd78f047x and 78f048x only. remarks 1. : don?t care ? : does not apply. pm : port mode register p : port output latch 2. the functions within arrowheads (< >) can be assigned by setting the input switch control register (isc). 3. x1, x2 pins can be used as on-chip debug mode setting pins (ocd1a, ocd1b) when the on-chip debug function is used. for detail, see chapter 29 on-chip debug function. user?s manual u18329ej4v0ud 147 chapter 5 clock generator 5.1 functions of clock generator the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following three kinds of system clo cks and clock oscillators are selectable. (1) main system clock <1> x1 oscillator this circuit oscillates a clock of f x = 2 to 10 mhz by connecting a resonator to x1 and x2. oscillation can be stopped by executing the stop inst ruction or using the main osc control register (moc). <2> internal high-speed oscillator this circuit oscillates a clock of f rh = 8 mhz (typ.). after a reset release, the cpu always starts operating with this internal high-speed oscillation clock. oscillation can be stopped by executing the stop instruction or using the internal oscillation mode register (rcm). an external main system clock (f exclk = 2 to 10 mhz) can also be supp lied from the ocd0b/exclk/x2/p122 pin. an external main system clock input can be dis abled by executing the stop instruction or using rcm. as the main system clock, a high-spee d system clock (x1 clock or external ma in system clock) or internal high- speed oscillation clock can be selected by using the main clock mode register (mcm). (2) subsystem clock ? subsystem clock oscillator this circuit oscillates at a frequency of f xt = 32.768 khz by connecting a 32.768 khz resonator across xt1 and xt2. oscillation can be stopped by using the pr ocessor clock control register (pcc) and clock operation mode select register (oscctl). remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f xt : xt1 clock oscillation frequency chapter 5 clock generator user?s manual u18329ej4v0ud 148 (3) internal low-speed oscillation clock (clock for watchdog timer) ? internal low-speed oscillator this circuit oscillates a clock of f rl = 240 khz (typ.). after a reset releas e, the internal low-speed oscillation clock always starts operating. oscillation can be stopped by using the internal oscill ation mode register (rcm) when ?internal low-speed oscillator can be stopped by software? is set by option byte. the internal low-speed oscillation clock cannot be us ed as the cpu clock. the following hardware operates with the internal low-speed oscillation clock. ? watchdog timer ? 8-bit timer h1 (if f rl , f rl /2 7 or f rl /2 9 is selected as the count clock) ? lcd controller/driver (if f rl /2 3 is selected as the lcd source clock) remark f rl : internal low-speed oscillation clock frequency 5.2 configuration of clock generator the clock generator includes the following hardware. table 5-1. configuration of clock generator item configuration control registers clock operation mode select register (oscctl) processor clock control register (pcc) internal oscillation mode register (rcm) main osc control register (moc) main clock mode register (mcm) oscillation stabilization time counter status register (ostc) oscillation stabilization time select register (osts) internal high-speed oscillation trimming register (hiotrm) oscillators x1 oscillator xt1 oscillator internal high-speed oscillator internal low-speed oscillator chapter 5 clock generator user?s manual u18329ej4v0ud 149 figure 5-1. block diag ram of clock generator option byte 1: cannot be stopped 0: can be stopped internal oscillation mode register (rcm) lsrstop rsts rstop internal high- speed oscillator (8 mhz (typ.)) internal low- speed oscillator (240 khz (typ.)) clock operation mode select register (oscctl) oscsels xt1/p123 xt2/p124 peripheral hardware clock (f prs ) watchdog timer, 8-bit timer h1, lcd controller/driver clock output 1/2 cpu clock (f cpu ) processor clock control register (pcc) css pcc2 cls pcc1 pcc0 prescaler main system clock switch peripheral hardware clock switch x1 oscillation stabilization time counter osts1 osts0 osts2 oscillation stabilization time select register (osts) 3 most 16 most 15 most 14 most 13 most 11 oscillation stabilization time counter status register (ostc) controller mcm0 xsel mcs mstop exclk oscsel clock operation mode select register (oscctl) 4 main clock mode register (mcm) main clock mode register (mcm) main osc control register (moc) internal bus internal bus high-speed system clock oscillator crystal/ceramic oscillation external input clock x1/p121 x2/exclk/ p122 crystal oscillation subsystem clock oscillator selector stop internal high-speed oscillation trimming register (hiotrm) ttrm3 ttrm2 ttrm4 ttrm1 ttrm0 5 f sub f rh f xh f x f exclk f xt f rl f xp f xp 2 f xp 2 2 f xp 2 3 f xp 2 4 f sub 2 chapter 5 clock generator user?s manual u18329ej4v0ud 150 remarks 1. f x : x1 clock oscillation frequency 2. f rh : internal high-speed oscillation clock frequency 3. f exclk : external main system clock frequency 4. f xh : high-speed system clock frequency 5. f xp : main system clock frequency 6. f prs : peripheral hardware clock frequency 7. f cpu : cpu clock frequency 8. f xt : xt1 clock oscillation frequency 9. f sub : subsystem clock frequency 10. f rl : internal low-speed oscillation clock frequency 5.3 registers controlling clock generator the following eight registers are us ed to control the clock generator. ? clock operation mode sele ct register (oscctl) ? processor clock control register (pcc) ? internal oscillation mode register (rcm) ? main osc control register (moc) ? main clock mode register (mcm) ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) ? internal high-speed oscillation trimming register (hiotrm) (1) clock operation mode select register (oscctl) this register selects the operation mo des of the high-speed system and s ubsystem clocks, and the gain of the on-chip oscillator. oscctl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. chapter 5 clock generator user?s manual u18329ej4v0ud 151 figure 5-2. format of clock operati on mode select register (oscctl) address: ff9fh after reset: 00h r/w symbol <7> <6> 5 <4> 3 2 1 0 oscctl exclk oscsel 0 oscsels 0 0 0 0 exclk oscsel high-speed system clock pin operation mode p121/x1 pin p122/x2/exclk pin 0 0 input port mode input port 0 1 x1 oscillation mode crystal/ceramic resonator connection 1 0 input port mode input port 1 1 external clock input mode input port external clock input caution to change the value of exclk and osc sel, be sure to confirm that bit 7 (mstop) of the main osc control register (moc) is 1 (the x1 oscillator stops or the external clock from the exclk pin is disabled). be sure to clear bits 0 to 3, and 5 to ?0?. remark f xh : high-speed system clock oscillation frequency chapter 5 clock generator user?s manual u18329ej4v0ud 152 (2) processor clock control register (pcc) this register is used to select t he cpu clock, the division ratio, and operation mode for subsystem clock. pcc is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pcc to 01h. figure 5-3. format of processor clock control register (pcc) address: fffbh after reset: 01h r/w note 1 symbol 7 6 <5> <4> 3 2 1 0 pcc 0 0 cls css 0 pcc2 pcc1 pcc0 cls cpu clock status 0 main system clock 1 subsystem clock note bit 5 is read-only. caution be sure to clear bi ts 3, 6, and 7 to ?0?. remarks 1. f xp : main system clock oscillation frequency 2. f sub : subsystem clock oscillation frequency the fastest instruction can be executed in 2 clocks of the cpu clock in the 78k 0/lf3. therefore, the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is as shown in table 5-2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 0 1 0 0 f xp /2 4 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 f sub /2 other than above setting prohibited chapter 5 clock generator user?s manual u18329ej4v0ud 153 table 5-2. relationship between cpu clo ck and minimum instruction execution time minimum instruction execution time: 2/f cpu main system clock high-speed system clock note internal high-speed oscillation clock note subsystem clock cpu clock (f cpu ) at 10 mhz operation at 8 mhz (typ.) operation at 32.768 khz operation f xp 0.2 s 0.25 s (typ.) ? f xp /2 0.4 s 0.5 s (typ.) ? f xp /2 2 0.8 s 1.0 s (typ.) ? f xp /2 3 1.6 s 2.0 s (typ.) ? f xp /2 4 3.2 s 4.0 s (typ.) ? f sub /2 ? ? 122.1 s note the main clock mode register (mcm) is used to set the main system clock supplied to cpu clock (high- speed system clock/internal high- speed oscillation clock) (see figure 5-6 ). (3) setting of operation mode for subsystem clock pin the operation mode for the subsystem clock pin can be set by using bit 4 (oscsels) of the clock operation mode select register (oscctl) in combination. table 5-3. setting of operati on mode for subsystem clock pin bit 4 of oscctl oscsels subsystem clock pin operation mode p123/xt1 pin p124/xt2 pin 0 input port mode input port 1 xt1 oscillation mode crystal resonator connection caution confirm that bit 5 (cls) of the processor clock cont rol register (pcc) is 0 (cpu is operating with main system clock) when changi ng the current values of oscsels. chapter 5 clock generator user?s manual u18329ej4v0ud 154 (4) internal oscillati on mode register (rcm) this register sets the operation mode of internal oscillator. rcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h note 1 . figure 5-4. format of internal oscillation mode register (rcm) address: ffa0h after reset: 80h note 1 r/w note 2 symbol <7> 6 5 4 3 2 <1> <0> rcm rsts 0 0 0 0 0 lsrstop rstop rsts status of internal high-speed oscillator 0 waiting for accuracy stabilizati on of internal high-speed oscillator 1 stability operating of internal high-speed oscillator lsrstop internal low-speed oscillator oscillating/stopped 0 internal low-speed oscillator oscillating 1 internal low-s peed oscillator stopped rstop internal high-speed oscillator oscillating/stopped 0 internal high-spe ed oscillator oscillating 1 internal high-speed oscillator stopped notes 1. the value of this register is 00h immedi ately after a reset release but automatically changes to 80h after internal high-speed oscillator has been stabilized. 2. bit 7 is read-only. caution when setting rstop to 1, be sure to confirm that the cpu operates with a clock other than the internal high -speed oscillation clock. sp ecifically, set under either of the following conditions. ? when mcs = 1 (when cpu operates with the high-speed system clock) ? when cls = 1 (when cpu opera tes with the subsystem clock) in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock before setting rstop to 1. chapter 5 clock generator user?s manual u18329ej4v0ud 155 (5) main osc control register (moc) this register selects the operati on mode of the high-speed system clock. this register is used to stop the x1 oscillator or to disable an external clock input from the exclk pin when the cpu operates with a clock other than the high-speed system clock. moc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 80h. figure 5-5. format of main osc control register (moc) address: ffa2h after reset: 80h r/w symbol <7> 6 5 4 3 2 1 0 moc mstop 0 0 0 0 0 0 0 control of high-speed system clock operation mstop x1 oscillation mode external clock input mode 0 x1 oscillator operating external clock from exclk pin is enabled 1 x1 oscillator stopped external clock from exclk pin is disabled cautions 1. when setting mstop to 1, be sure to confirm th at the cpu operates with a clock other than the high-speed system clock. specifically , set under either of the following conditions. ? when mcs = 0 (when cpu operates with the internal high-speed oscillation clock) ? when cls = 1 (when cpu operat es with the subsystem clock) in addition, stop peripheral hardware th at is operating on the high-speed system clock before setting mstop to 1. 2. do not clear mstop to 0 while bit 6 (oscsel) of the clock operation mode select register (oscctl) is 0 (i/o port mode). 3. the peripheral hardware cannot operate when the pe ripheral hardware clock is stopped. to resume the operation of the peripheral hardware after the peripheral hardware clock has been stopped, in itialize the peri pheral hardware. chapter 5 clock generator user?s manual u18329ej4v0ud 156 (6) main clock mode register (mcm) this register selects the main system clock supplied to cpu clock and clock supplied to peripheral hardware clock. mcm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 5-6. format of main clock mode register (mcm) address: ffa1h after reset: 00h r/w note symbol 7 6 5 4 3 <2> <1> <0> mcm 0 0 0 0 0 xsel mcs mcm0 selection of clock supplied to main system clock and peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) mcs main system clock status 0 operates with internal high-speed oscillation clock 1 operates with hi gh-speed system clock note bit 1 is read-only. cautions 1. xsel can be change d only once after a reset release. 2. a clock other than f prs is supplied to the following peripheral functions regardless of the se tting of xsel and mcm0. ? watchdog timer (operates with intern al low-speed oscillation clock) ? when ?f rl ?, ?f rl /2 7 ?, or ?f rl /2 9 ? is selected as the count clock for 8-bit timer h1 (operates with internal low-speed oscillation clock) ? when ?f rl /2 3 ? is selected as the lcd source cl ock for lcd controller/driver (operates with internal low-speed oscillation clock) ? peripheral hardware selects the ext ernal clock as the clock source (except when the external count clock of tm00 is selected (ti000 pin valid edge)) chapter 5 clock generator user?s manual u18329ej4v0ud 157 (7) oscillation stabilization time c ounter status register (ostc) this is the register that indicates t he count status of the x1 clock oscillati on stabilization time counter. when x1 clock oscillation starts with the intern al high-speed oscillation clock or su bsystem clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lv i, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 5-7. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most 11 most 13 most 14 most 15 most 16 oscillation stabilization time status f x = 2 mhz f x = 5 mhz f x = 10 mhz 1 0 0 0 0 2 11 /f x min. 1.02 ms min. 409.6 s min. 204.8 s min. 1 1 0 0 0 2 13 /f x min. 4.10 ms min. 1.64 ms min. 819.2 s min. 1 1 1 0 0 2 14 /f x min. 8.19 ms min. 3.27 ms min. 1.64 ms min. 1 1 1 1 0 2 15 /f x min. 16.38 ms min. 6.55 ms min. 3.27 ms min. 1 1 1 1 1 2 16 /f x min. 32.77 ms min. 13.11 ms min. 6.55 ms min. cautions 1. after the above time has elapsed, th e bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator user?s manual u18329ej4v0ud 158 (8) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elapsed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 5-8. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 2 mhz f x = 5 mhz f x = 10 mhz 0 0 1 2 11 /f x 1.02 ms 409.6 s 204.8 s 0 1 0 2 13 /f x 4.10 ms 1.64 ms 819.2 s 0 1 1 2 14 /f x 8.19 ms 3.27 ms 1.64 ms 1 0 0 2 15 /f x 16.38 ms 6.55 ms 3.27 ms 1 0 1 2 16 /f x 32.77 ms 13.11 ms 6.55 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 5 clock generator user?s manual u18329ej4v0ud 159 (9) internal high-speed oscillati on trimming register (hiotrm) this register corrects the accuracy of the internal high- speed oscillator. the accuracy can be corrected by self- measuring the frequency of the internal high-speed oscill ator, using a subsystem clock using a crystal resonator or using a timer with high-accuracy external clock input, such as a real-time counter. hiotrm can be set by an 8-bit memory manipulation instruction. reset signal generation sets hiotrm to 10h. caution if the temperature or v dd pin voltage is changed after accu racy correction, the frequency will fluctuate. also, if a value othe r than the initial value (10h) is set to the hiotrm register, the oscillation accuracy of the inte rnal high-speed oscillation clock may exceed the min. and max. values described in chapter 31 electr ical specifications (standard products) due to the subsequent fluctuat ion in the temperature or v dd voltage, or hiotrm register setting value. if the temperature or v dd voltage fluctuates, accuracy correction must be executed either before frequency accur acy will be required or regularly. chapter 5 clock generator user?s manual u18329ej4v0ud 160 figure 5-9. format of internal high-spee d oscillation trimming register (hiotrm) address: ff30h after reset: 10h r/w symbol 7 6 5 4 3 2 1 0 hiotrm 0 0 0 ttrm4 ttrm3 ttrm2 ttrm1 ttrm0 clock correction value (2.7 v v dd 5.5 v) ttrm4 ttrm3 ttrm2 ttrm1 ttrm0 min. typ. max. 0 0 0 0 0 ? 5.54% ? 4.88% ? 4.02% 0 0 0 0 1 ? 5.28% ? 4.62% ? 3.76% 0 0 0 1 0 ? 4.99% ? 4.33% ? 3.47% 0 0 0 1 1 ? 4.69% ? 4.03% ? 3.17% 0 0 1 0 0 ? 4.39% ? 3.73% ? 2.87% 0 0 1 0 1 ? 4.09% ? 3.43% ? 2.57% 0 0 1 1 0 ? 3.79% ? 3.13% ? 2.27% 0 0 1 1 1 ? 3.49% ? 2.83% ? 1.97% 0 1 0 0 0 ? 3.19% ? 2.53% ? 1.67% 0 1 0 0 1 ? 2.88% ? 2.22% ? 1.36% 0 1 0 1 0 ? 2.23% ? 1.91% ? 1.31% 0 1 0 1 1 ? 1.92% ? 1.60% ? 1.28% 0 1 1 0 0 ? 1.60% ? 1.28% ? 0.96% 0 1 1 0 1 ? 1.28% ? 0.96% ? 0.64% 0 1 1 1 0 ? 0.96% ? 0.64% ? 0.32% 0 1 1 1 1 ? 0.64% ? 0.32% 0% 1 0 0 0 0 0% (default) 1 0 0 0 1 0% +0.32% +0.64% 1 0 0 1 0 +0.33% +0.65% +0.97% 1 0 0 1 1 +0.66% +0.98% +1.30% 1 0 1 0 0 +0.99% +1.31% +1.63% 1 0 1 0 1 +1.32% +1.64% +1.96% 1 0 1 1 0 +1.38% +1.98% +2.30% 1 0 1 1 1 +1.46% +2.32% +2.98% 1 1 0 0 0 +1.80% +2.66% +3.32% 1 1 0 0 1 +2.14% +3.00% +3.66% 1 1 0 1 0 +2.48% +3.34% +4.00% 1 1 0 1 1 +2.83% +3.69% +4.35% 1 1 1 0 0 +3.18% +4.04% +4.70% 1 1 1 0 1 +3.53% +4.39% +5.05% 1 1 1 1 0 +3.88% +4.74% +5.40% 1 1 1 1 1 +4.24% +5.10% +5.76% caution the internal high-speed o scillation frequency will increase in speed if the hiotrm register value is incremented above a sp ecific value, and will decrease in speed if decremented below that specific value. a reversa l, such that the frequency decre ases in speed by incrementing the value, or increases in speed by decr ementing the value, will not occur. chapter 5 clock generator user?s manual u18329ej4v0ud 161 5.4 system clock oscillator 5.4.1 x1 oscillator the x1 oscillator oscillates with a cryst al resonator or ceramic resonator (2 to 10 mhz) connected to the x1 and x2 pins. an external clock can also be input. in this case, input the clock signal to the exclk pin. figure 5-10 shows an example of the exte rnal circuit of the x1 oscillator. figure 5-10. example of extern al circuit of x1 oscillator (a) crystal or ceramic osc illation (b) external clock v ss x1 x2 crystal resonator or ceramic resonator exclk external clock 5.4.2 xt1 oscillator the xt1 oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. figure 5-11 shows an example of the exte rnal circuit of the xt1 oscillator. figure 5-11. example of extern al circuit of xt1 oscillator (a) crystal oscillation xt2 v ss xt1 32.768 khz caution 1. when using the x1 oscillator and xt1 osc illator, wire as follows in the area enclosed by the broken lines in the figures 5-10 and 5-11 to avoid an adverse e ffect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal li nes. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the os cillator capacitor the same potential as v ss . do not ground the capacitor to a ground patter n through which a high current flows. ? do not fetch signals from the oscillator. note that the xt1 oscillator is designed as a low-amplitude circuit for reducing power consumption. chapter 5 clock generator user?s manual u18329ej4v0ud 162 figure 5-12 shows examples of incorrect resonator connection. figure 5-12. examples of incorr ect resonator connection (1/2) (a) too long wiring (b) crossed signal line x2 v ss x1 x1 v ss x2 port remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. chapter 5 clock generator user?s manual u18329ej4v0ud 163 figure 5-12. examples of incorr ect resonator connection (2/2) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss x1 x2 v ss x1 x2 ab c pmn v dd high current high current (e) signals are fetched v ss x1 x2 remark when using the subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. caution 2. when x2 and xt1 are wired in paralle l, the crosstalk noise of x2 may increase with xt1, resulting in malfunctioning. chapter 5 clock generator user?s manual u18329ej4v0ud 164 5.4.3 when subsystem clock is not used if it is not necessary to use the subsystem clock for low power consumption operat ions, or if not using the subsystem clock as an i/o port, set the xt1 and xt2 pins to input port mode (oscse ls = 0) and independently connect to v dd or v ss via a resistor. remark oscsels: bit 4 of clock operati on mode select register (oscctl) 5.4.4 internal hi gh-speed oscillator the internal high-speed oscillator is incorporated in the 78k0/lf3. oscillation can be controlled by the internal oscillation mode register (rcm). after a reset release, the internal high-speed oscilla tor automatically starts oscillation (8 mhz (typ.)). 5.4.5 internal low-speed oscillator the internal low-speed oscillator is incorporated in the 78k0/lf3. the internal low-speed oscillation clock is only used as the clock of the watchdog timer, 8-bit timer h1, and lcd controller/driver. the internal low-speed osci llation clock cannot be used as the cpu clock. ?can be stopped by software? or ?cannot be stopped? ca n be selected by the option byte. when ?can be stopped by software? is set, oscillation can be controlled by the internal oscillation mode register (rcm). after a reset release, the internal low-speed oscillator automatically starts oscillati on, and the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operation is enabled using the option byte. 5.4.6 prescaler the prescaler generates various clocks by dividing the main system clock when the ma in system clock is selected as the clock to be supplied to the cpu. chapter 5 clock generator user?s manual u18329ej4v0ud 165 5.5 clock generator operation the clock generator generates the following clocks and contro ls the operation modes of the cpu, such as standby mode (see figure 5-1 ). ? main system clock f xp ? high-speed system clock f xh x1 clock f x external main system clock f exclk ? internal high-speed oscillation clock f rh ? subsystem clock f sub ? xt1 clock f xt ? internal low-speed oscillation clock f rl ? cpu clock f cpu ? peripheral hardware clock f prs the cpu starts operation when the internal high-speed osc illator starts outputting after a reset release in the 78k0/lf3, thus enab ling the following. (1) enhancement of security function when the x1 clock is set as the cpu clock by the defaul t setting, the device cannot operate if the x1 clock is damaged or badly connected and therefore does not operate after reset is released. however, the start clock of the cpu is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release. consequently , the system can be safely shut down by performing a minimum operation, such as acknowledging a reset source by software or performing safety processing when there is a malfunction. (2) improvement of performance because the cpu can be started with out waiting for the x1 clock oscillation stabilization time, the total performance can be improved. when the power supply voltage is turned on, the cl ock generator operation is shown in figure 5-13. chapter 5 clock generator user?s manual u18329ej4v0ud 166 figure 5-13. clock generator operation wh en power supply voltage is turned on (when 1.59 v poc mode is set (option byte: pocmode = 0)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note 2 starting x1 oscillation is specified by software. starting xt1 oscillation is specified by software. reset processing (19 to 80 s) <3> waiting for voltage stabilization internal reset signal 0 v 1.59 v (typ.) 1.8 v 0.5 v/ms (min.) power supply voltage (v dd ) <1> <2> <4> <5> <5> <4> note 1 (1.93 to 5.39 ms) <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 1.59 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> when the power supply voltage rises with a slope of 0.5 v/ms (min.), the cp u starts operation on the internal high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the power supply and regulator have elapsed, and then reset processing is performed. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlli ng high-speed system clock and (3) in 5.6.3 example of controlling subsystem clock ). notes 1. the internal voltage stabilization time includes the osc illation accuracy stabilization time of the internal high-speed oscillation clock. 2. when releasing a reset (above figure) or releas ing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the osc illation stabilization time for the x1 clock using the oscillation stabilization time count er status register (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation st abilization time when releasing stop mode using the oscillation stabilization time select register (osts). cautions 1. if the voltage rises wit h a slope of less than 0.5 v/ms (min .) from power application until the voltage reaches 1.8 v, input a lo w level to the reset pin from power application until the voltage reaches 1.8 v, or set th e 2.7 v/1.59 v poc mode by us ing the option byte (pocmode = 1) (see figure 5-14). by doing so, th e cpu operates with the same timing as <2> and thereafter in figure 5-13 after re set release by the reset pin. 2. it is not necessary to wait for the oscillati on stabilization time when an external clock input from the exclk pin is used. chapter 5 clock generator user?s manual u18329ej4v0ud 167 remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed o scillation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 5.6.1 example of co ntrolling high-speed system clock , (3) in 5.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 5.6.3 example of controlling subsystem clock ). figure 5-14. clock generator operation wh en power supply voltage is turned on (when 2.7 v/1.59 v poc mode is set (option byte: pocmode = 1)) internal high-speed oscillation clock (f rh ) cpu clock high-speed system clock (f xh ) (when x1 oscillation selected) internal high-speed oscillation clock high-speed system clock switched by software subsystem clock (f sub ) (when xt1 oscillation selected) subsystem clock x1 clock oscillation stabilization time: 2 11 /f x to 2 16 /f x note starting x1 oscillation is specified by software. starting xt1 oscillation is specified by software. waiting for oscillation accuracy stabilization (86 to 361 s ) internal reset signal 0 v 2.7 v (typ.) power supply voltage (v dd ) <1> <3> <2> <4> <5> reset processing (11 to 47 s ) <4> <5> <1> when the power is turned on, an internal reset signal is generated by the power-on-clear (poc) circuit. <2> when the power supply voltage exceeds 2.7 v (typ.), the reset is released and the internal high-speed oscillator automatically starts oscillation. <3> after the reset is released and reset processing is performed, the cpu starts operation on the internal high- speed oscillation clock. <4> set the start of oscillation of the x1 or xt1 clock via software (see (1) in 5.6.1 example of controlling high- speed system clock and (1) in 5.6.3 example of cont rolling subsystem clock) . <5> when switching the cpu clock to the x1 or xt1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see (3) in 5.6.1 example of controlli ng high-speed system clock and (3) in 5.6.3 example of controlling subsystem clock ). note when releasing a reset (above figure) or releasing stop mode while the cpu is operating on the internal high-speed oscillation clock, confirm the oscillation stab ilization time for the x1 clock using the oscillation stabilization time counter status r egister (ostc). if the cpu operates on the high-speed system clock (x1 oscillation), set the oscillation stabilization time when releasing stop mode using the oscillation stabilization time select register (osts). cautions 1. a voltage oscillation stabilization time of 1.93 to 5.39 ms is require d after the supply voltage reaches 1.59 v (typ.). if the ti me the supply voltage rises from 1.59 v (typ.) to 2.7 v (typ.) is within 1.93 to 5.39 ms, a power supply stabiliz ation wait time of 0 to 5.39 ms occurs automatically before reset processing, an d the reset processing time becomes 19 to 80 s. 2. it is not necessary to wait for the oscillation stabilization ti me when an external clock input from the exclk pin is used. chapter 5 clock generator user?s manual u18329ej4v0ud 168 remark while the microcontroller is operating, a clock t hat is not used as the cpu clock can be stopped via software settings. the internal high-speed o scillation clock and high-speed system clock can be stopped by executing the stop instruction (see (4) in 5.6.1 example of co ntrolling high-speed system clock , (3) in 5.6.2 example of controlling inte rnal high-speed oscillation clock , and (4) in 5.6.3 example of controlling subsystem clock ). 5.6 controlling clock 5.6.1 example of control ling high-speed system clock the following two types of high-s peed system clocks are available. ? x1 clock: crystal/ceramic resonator is connected across the x1 and x2 pins. ? external main system clock: exter nal clock is input to the exclk pin. when the high-speed system clock is not used, the ocd0a/x1/p121 and ocd0b/x2/exclk/p122 pins can be used as i/o port pins. caution the ocd0a/x1/p121 and ocd0b/x2/exclk/p122 pi ns are in the i/o port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating x1 clock (2) when using external main system clock (3) when using high-speed system clock as cpu clock and peripheral hardware clock (4) when stopping high-speed system clock (1) example of setting procedure when oscillating the x1 clock <1> setting p121/x1 and p122/x2/exclk pins and selecti ng x1 clock or external clock (oscctl register) when exclk is cleared to 0 and oscsel is set to 1, the mode is switched from port mode to x1 oscillation mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 0 1 x1 oscillation mode crystal/ceramic resonator connection <2> controlling oscillation of x1 clock (moc register) if mstop is cleared to 0, the x1 oscillator starts oscillating. <3> waiting for the stabilization of the oscillation of x1 clock check the ostc register and wait for the necessary time. during the wait time, other software processing c an be executed with the internal high-speed oscillation clock. cautions 1. do not change the value of exclk and oscsel while the x1 clock is operating. 2. set the x1 clock after the supply voltage has reached the ope rable voltage of the clock to be used (see chapter 31 electrical specifications (standard products)). chapter 5 clock generator user?s manual u18329ej4v0ud 169 (2) example of setting procedure when using the external main system clock <1> setting p121/x1 and p122/x2/exclk pins and selecting operation mode (oscctl register) when exclk and oscsel are set to 1, the mode is switched from port mode to external clock input mode. exclk oscsel operation mode of high- speed system clock pin p121/x1 pin p122/x2/exclk pin 1 1 external clock input mode i/o port external clock input <2> controlling external main system clock input (moc register) when mstop is cleared to 0, the input of the external main system clock is enabled. cautions 1. do not change the value of exclk a nd oscsel while the external main system clock is operating. 2. set the external main system clock afte r the supply voltage h as reached the operable voltage of the clock to be used (see chapter 31 electrical specifications (standard products)). (3) example of setting procedure when using high-speed system clo ck as cpu clock and peripheral hardware clock <1> setting high-speed system clock oscillation note (see 5.6.1 (1) example of setting proce dure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when hi gh-speed system clock is already operating. <2> setting the high-speed system clock as the main system clock (mcm register) when xsel and mcm0 are set to 1, the high-speed syst em clock is supplied as the main system clock and peripheral hardware clock. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 1 1 high-speed system clock (f xh ) high-speed system clock (f xh ) caution if the high-speed system clock is selected as the main syst em clock, a clock other than the high-speed system clock cannot be set as the peripheral hardware clock. <3> setting the main system clock as the cpu clo ck and selecting the division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited chapter 5 clock generator user?s manual u18329ej4v0ud 170 (4) example of setting procedure when stopping the high-speed system clock the high-speed system clock can be st opped in the foll owing two ways. ? executing the stop instruction to set the stop mode ? setting mstop to 1 and stopping the x1 oscillation (dis abling clock input if the external clock is used) (a) to execute a stop instruction <1> setting to stop peripheral hardware stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 23 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and x1 oscillation is stopped (the input of the ex ternal clock is disabled). (b) to stop x1 oscillation (disabling exter nal clock input) by setting mstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operat ing on a clock other than the high-speed system clock. when cls = 0 and mcs = 1, the high-speed system cl ock is supplied to the cpu, so change the cpu clock to the subsystem clock or internal high-speed oscillation clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the high-speed system clock (moc register) when mstop is set to 1, x1 oscillation is stopp ed (the input of the external clock is disabled). caution be sure to confirm that mcs = 0 or cls = 1 when setting mstop to 1. in addition, stop peripheral hardware that is operating on the high-speed system clock. 5.6.2 example of controlling inte rnal high-speed oscillation clock the following describes examples of clock setting procedures for the following cases. (1) when restarting oscillation of the internal high-speed oscillation clock (2) when using internal high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock (3) when stopping the internal high-speed oscillation clock chapter 5 clock generator user?s manual u18329ej4v0ud 171 (1) example of setting procedure wh en restarting oscillation of the in ternal high-speed oscillation clock note 1 <1> setting restart of oscillation of the intern al high-speed oscillation clock (rcm register) when rstop is cleared to 0, the internal high-speed oscillation clock starts operating. <2> waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (rcm register) wait until rsts is set to 1 note 2 . notes 1. after a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the cpu clock. 2. this wait time is not necessary if high accura cy is not necessary for the cpu clock and peripheral hardware clock. (2) example of setting procedure when using intern al high-speed oscillation clock as cpu clock, and internal high-speed oscillation clock or high-speed system clo ck as peripheral hardware clock <1> ? restarting oscillation of the internal high-speed oscillation clock note (see 5.6.2 (1) example of setting procedure when restarting internal high-speed oscillation clock ). ? oscillating the high-speed system clock note (this setting is required when using the high-speed system clock as the peripheral hardware clock. see 5.6.1 (1) example of setting proced ure when oscillating the x1 clock and (2) example of setting procedure when using th e external main system clock. ) note the setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> selecting the clock s upplied as the main system clock and peri pheral hardware clock (mcm register) set the main system clock and peripheral hardware clock using xsel and mcm0. selection of main system clock and clock supplied to peripheral hardware xsel mcm0 main system clock (f xp ) peripheral hardware clock (f prs ) 0 0 0 1 internal high-speed oscillation clock (f rh ) 1 0 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) <3> selecting the cpu clock division ratio (pcc register) when css is cleared to 0, the main system clock is supplied to the cpu. to select the cpu clock division ratio, use pcc0, pcc1, and pcc2. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 f xp 0 0 1 f xp /2 (default) 0 1 0 f xp /2 2 0 1 1 f xp /2 3 1 0 0 f xp /2 4 0 other than above setting prohibited chapter 5 clock generator user?s manual u18329ej4v0ud 172 (3) example of setting procedure when stoppi ng the internal high-speed oscillation clock the internal high-speed oscillation clock can be stopped in the following two ways. ? executing the stop instruction to set the stop mode ? setting rstop to 1 and stopping the internal high-speed oscillation clock (a) to execute a stop instruction <1> setting of peripheral hardware stop peripheral hardware that c annot be used in the stop mode (f or peripheral hardware that cannot be used in stop mode, see chapter 23 standby function ). <2> setting the x1 clock oscillation st abilization time after standby release when the cpu is operating on the x1 clock, set t he value of the osts r egister before the stop instruction is executed. <3> executing the stop instruction when the stop instruction is ex ecuted, the system is placed in the stop mode and internal high- speed oscillation clock is stopped. (b) to stop internal high-speed o scillation clock by setting rstop to 1 <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operati ng on a clock other than the internal high-speed oscillation clock. when cls = 0 and mcs = 0, the internal high-speed oscillation clock is supplied to the cpu, so change the cpu clock to the high-spe ed system clock or subsystem clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the internal high-speed oscillation clock (rcm register) when rstop is set to 1, internal high-speed oscillation clock is stopped. caution be sure to confirm that mcs = 1 or cls = 1 when setting rstop to 1. in addition, stop peripheral hardware that is operating on the internal high-speed oscillation clock. 5.6.3 example of cont rolling subsystem clock the following two types of sub system clocks are available. ? xt1 clock: crystal/ceramic resonator is connected across the xt1 and xt2 pins. when the subsystem clock is not us ed, the xt1/p123 and xt2/p124 pins can be used as input port pins. caution the xt1/p123 and xt2/p124 pins are in the input port mode after a reset release. the following describes examples of setti ng procedures for the following cases. (1) when oscillating xt1 clock (2) when using subsystem clock as cpu clock (3) when stopping subsystem clock chapter 5 clock generator user?s manual u18329ej4v0ud 173 (1) example of setting procedur e when oscillating the xt1 clock <1> setting xt1 and xt2 pins and selectin g operation mode (pcc and oscctl registers) when oscsels is set as any of the following, the mo de is switched from port mode to xt1 oscillation mode. oscsels operation mode of subsystem clock pin p123/xt1 pin p124/xt2 pin 1 xt1 oscillation mode crystal/ceramic resonator connection <2> waiting for the stabilization of the subsystem clock oscillation wait for the oscillation stabilization time of the subsystem clock by software, using a timer function. caution do not change the value of oscsel s while the subsystem clock is operating. (2) example of setting procedure when us ing the subsystem cl ock as the cpu clock <1> setting subsystem clock oscillation note (see 5.6.3 (1) example of setting proce dure when oscillating the xt1 clock ) note the setting of <1> is not necessary when while the subsystem clock is operating. <2> switching the cpu clock (pcc register) when css is set to 1, the subsystem clock is supplied to the cpu. css pcc2 pcc1 pcc0 cpu clock (f cpu ) selection 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 f sub /2 1 other than above setting prohibited (3) example of setting procedure wh en stopping the subsystem clock <1> confirming the cpu clock st atus (pcc and mcm registers) confirm with cls and mcs that the cpu is operat ing on a clock other than the subsystem clock. when cls = 1, the subsystem clock is supplied to t he cpu, so change the cpu clock to the internal high-speed oscillation clock or high-speed system clock. cls mcs cpu clock status 0 0 internal high-speed oscillation clock 0 1 high-speed system clock 1 subsystem clock <2> stopping the subsystem clock (oscctl register) when oscsels is cleared to 0, xt1 oscillation is stopped. cautions 1. be sure to confirm that cls = 0 when clearing oscsel s to 0. in addition, stop the peripheral hardware if it is op erating on the subsystem clock. 2. the subsystem clock oscillation cannot be stopped using the stop instruction. chapter 5 clock generator user?s manual u18329ej4v0ud 174 5.6.4 example of controlling in ternal low-speed oscillation clock the internal low-speed oscillation clock cannot be used as the cpu clock. only the following peripheral hardware can operate with this clock. ? watchdog timer ? 8-bit timer h1 (if f rl , f rl /2 7 or f rl /2 9 is selected as the count clock) ? lcd controller/driver (if f rl /2 3 is selected as the lcd source clock) in addition, the following operation modes can be selected by the option byte. ? internal low-speed oscillator cannot be stopped ? internal low-speed oscillator can be stopped by software the internal low-speed oscillator autom atically starts oscillation after a reset release, and the watchdog timer is driven (240 khz (typ.)) if the watchdog timer operation has been enabled by the option byte. (1) example of setting procedure when stoppi ng the internal low-speed oscillation clock <1> setting lsrstop to 1 (rcm register) when lsrstop is set to 1, the internal low-speed oscillation clock is stopped. (2) example of setting procedure when restarting osc illation of the internal low-speed oscillation clock <1> clearing lsrstop to 0 (rcm register) when lsrstop is cleared to 0, the internal low-speed oscillation clock is restarted. caution if ?internal low-speed oscillator cannot be st opped? is selected by the option byte, oscillation of the internal low-speed oscillati on clock cannot be controlled. 5.6.5 clocks supplied to cp u and peripheral hardware the following table shows the relation among the clocks supplied to the cpu and peripheral hardware, and setting of registers. table 5-4. clocks supplied to cpu and peripheral hardware, and register setting supplied clock clock supplied to cpu clock su pplied to peripheral hardware xsel css mcm0 exclk internal high-speed oscillation clock 0 0 x1 clock 1 0 0 0 internal high-speed oscillation clock external main system clock 1 0 0 1 x1 clock 1 0 1 0 external main system clock 1 0 1 1 internal high-speed oscillation clock 0 1 1 1 0 0 x1 clock 1 1 1 0 1 1 0 1 subsystem clock external main system clock 1 1 1 1 remarks 1. xsel: bit 2 of the main clock mode register (mcm) 2. css: bit 4 of the processor clock control register (pcc) 3. mcm0: bit 0 of mcm 4. exclk: bit 7 of the clock operat ion mode select register (oscctl) 5. : don?t care chapter 5 clock generator user?s manual u18329ej4v0ud 175 5.6.6 cpu clock stat us transition diagram figure 5-15 shows the cpu clock status transition diagram of this product. figure 5-15. cpu clock stat us transition diagram (when 1.59 v poc mode is set (option byte: pocmode = 0)) power on reset release internal low-speed oscillation: woken up internal high-speed oscillation: woken up x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation input: stops (input port mode) internal low-speed oscillation: operating internal high-speed oscillation: operating x1 oscillation/exclk input: stops (i/o port mode) xt1 oscillation input: stops (input port mode) cpu: operating with internal high- speed oscillation internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: selectable by cpu xt1 oscillation input: selectable by cpu cpu: internal high- speed oscillation stop internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation input: operable cpu: internal high- speed oscillation halt internal low-speed oscillation: operable internal high-speed oscillation: operating x1 oscillation/exclk input: operable xt1 oscillation input: operable cpu: operating with x1 oscillation or exclk input cpu: x1 oscillation/exclk input stop cpu: x1 oscillation/exclk input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: operating xt1 oscillation input: selectable by cpu internal low-speed oscillation: operable internal high-speed oscillation: stops x1 oscillation/exclk input: stops xt1 oscillation: operable internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operating xt1 oscillation input: operable cpu: operating with xt1 oscillation input cpu: xt1 oscillation input halt internal low-speed oscillation: operable internal high-speed oscillation: selectable by cpu x1 oscillation/exclk input: selectable by cpu xt1 oscillation input: operating internal low-speed oscillation: operable internal high-speed oscillation: operable x1 oscillation/exclk input: operable xt1 oscillation input: operating (b) (a) (c) (d) (e) (f) (g) (h) (i) v dd 1.59 v (typ.) v dd 1.8 v (min.) v dd < 1.59 v (typ.) remark in the 2.7 v/1.59 v poc mode ( option byte: pocmode = 1), the cpu cl ock status changes to (a) in the above figure when the supply voltage exceeds 2.7 v (typ.), and to (b) after reset processing (11 to 47 s (typ.)). chapter 5 clock generator user?s manual u18329ej4v0ud 176 table 5-5 shows transition of the cpu clock and examples of setting the sfr registers. table 5-5. cpu clock transition a nd sfr register setting examples (1/4) (1) cpu operating with internal high-speed oscillation clock (b) a fter reset release (a) status transition sfr register setting (a) (b) sfr registers do not have to be se t (default status after reset release). (2) cpu operating with high-speed system clock (c) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition exclk oscsel mstop ostc register xsel mcm0 (a) (b) (c) (x1 clock) 0 1 0 must be checked 1 1 (a) (b) (c) (external main clock) 1 1 0 must not be checked 1 1 caution set the clock after the supply volt age has reached the operable voltag e of the clock to be set (see chapter 31 electrical specif ications (standard products)). (3) cpu operating with subsystem cl ock (d) after reset release (a) (the cpu operates with the internal high-speed oscill ation clock immediately after a reset release (b).) (setting sequence of sfr registers) setting flag of sfr register status transition oscsels waiting for oscillation stabilization css (a) (b) (d) 1 necessary 1 remarks 1. (a) to (i) in table 5-5 correspond to (a) to (i) in figure 5-15. 2. exclk, oscsel, oscsels: bits 7, 6, and 4 of the clock op eration mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) chapter 5 clock generator user?s manual u18329ej4v0ud 177 table 5-5. cpu clock transition a nd sfr register setting examples (2/4) (4) cpu clock changing from inte rnal high-speed oscillation clock (b) to high-speed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition exclk oscsel mstop ostc register xsel note mcm0 (b) (c) (x1 clock) 0 1 0 must be checked 1 1 (b) (c) (external main clock) 1 1 0 must not be checked 1 1 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock note the value of this flag can be changed only once after a re set release. this setting is not necessary if it has already been set. caution set the clock after the supply volt age has reached the operable voltag e of the clock to be set (see chapter 31 electrical specif ications (standard products)). (5) cpu clock changing from in ternal high-speed oscillation cl ock (b) to subsystem clock (d) (setting sequence of sfr registers) setting flag of sfr register status transition oscsels waiting for oscillation stabilization css (b) (d) 1 necessary 1 remarks 1. (a) to (i) in table 5-5 correspond to (a) to (i) in figure 5-15. 2. exclk, oscsel, oscsels: bits 7, 6, and 4 of the clock op eration mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) chapter 5 clock generator user?s manual u18329ej4v0ud 178 table 5-5. cpu clock transition a nd sfr register setting examples (3/4) (6) cpu clock changing from high- speed system clock (c) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 (c) (b) 0 confirm this flag is 1. 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock (7) cpu clock changing from high-speed system clock (c) to subsystem clock (d) (setting sequence of sfr registers) setting flag of sfr register status transition oscsels waiting for oscillation stabilization css (c) (d) 1 necessary 1 unnecessary if the cpu is operating with the subsystem clock (8) cpu clock changing from subsystem clock (d ) to internal high-speed oscillation clock (b) (setting sequence of sfr registers) setting flag of sfr register status transition rstop rsts mcm0 css (d) (b) 0 confirm this flag is 1. 0 0 unnecessary if the cpu is operating with the internal high-speed oscillation clock unnecessary if xsel is 0 remarks 1. (a) to (i) in table 5-5 correspond to (a) to (i) in figure 5-15. 2. mcm0: bit 0 of the main clock mode register (mcm) oscsels: bit 4 of the clock operat ion mode select register (oscctl) rsts, rstop: bits 7 and 0 of the internal oscillation mode register (rcm) css: bit 4 of the processor clock control register (pcc) chapter 5 clock generator user?s manual u18329ej4v0ud 179 table 5-5. cpu clock transition a nd sfr register setting examples (4/4) (9) cpu clock changing from subsystem clock (d) to high-sp eed system clock (c) (setting sequence of sfr registers) setting flag of sfr register status transition exclk oscsel mstop ostc register xsel note mcm0 css (d) (c) (x1 clock) 0 1 0 must be checked 1 1 0 (d) (c) (external main clock) 1 1 0 must not be checked 1 1 0 unnecessary if these registers are already set unnecessary if the cpu is operating with the high-speed system clock note the value of this flag can be changed only once after a re set release. this setting is not necessary if it has already been set. caution set the clock after the supply volt age has reached the operable voltag e of the clock to be set (see chapter 31 electrical specif ications (standard products)). (10) ? halt mode (e) set while cpu is operating wit h internal high-speed oscillation clock (b) ? halt mode (f) set while cpu is ope rating with high-speed system clock (c) ? halt mode (g) set while cpu is operating with subsystem clock (d) status transition setting (b) (e) (c) (f) (d) (g) executing halt instruction (11) ? stop mode (h) set while cp u is operating with internal hi gh-speed oscillation clock (b) ? stop mode (i) set while cpu is ope rating with high-speed system clock (c) (setting sequence) status transition setting (b) (h) (c) (i) stopping peripheral functions that cannot operate in stop mode executing stop instruction remarks 1. (a) to (i) in table 5-5 correspond to (a) to (i) in figure 5-15. 2. exclk, oscsel: bits 7 and 6 of the clock operation mode select register (oscctl) mstop: bit 7 of the main osc control register (moc) xsel, mcm0: bits 2 and 0 of the main clock mode register (mcm) css: bit 4 of the processor clock control register (pcc) chapter 5 clock generator user?s manual u18329ej4v0ud 180 5.6.7 condition before changing cpu clo ck and processing after changing cpu clock condition before changing the cpu clock and processing after changing the cpu clock are shown below. table 5-6. changing cpu clock cpu clock before change after change condition before change processing after change x1 clock stabilization of x1 oscillation ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time internal high- speed oscillation clock external main system clock enabling input of exter nal clock from exclk pin ? mstop = 0, oscsel = 1, exclk = 1 ? internal high-speed oscillator can be stopped (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock internal high- speed oscillation clock oscillation of internal high-speed oscillator ? rstop = 0 external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock operating current can be reduced by stopping internal high-speed oscillator (rstop = 1). x1 clock x1 oscillation can be stopped (mstop = 1). external main system clock xt1 clock stabilization of xt1 oscillation ? oscsels = 1 ? after elapse of oscillation stabilization time external main system clock input can be disabled (mstop = 1). internal high- speed oscillation clock oscillation of internal high-speed oscillator and selection of internal high-speed oscillation clock as main system clock ? rstop = 0, mcs = 0 x1 clock stabilization of x1 oscillation and selection of high-speed system cl ock as main system clock ? mstop = 0, oscsel = 1, exclk = 0 ? after elapse of oscillation stabilization time ? mcs = 1 xt1 clock external main system clock enabling input of exter nal clock from exclk pin and selection of high-speed system clock as main system clock ? mstop = 0, oscsel = 1, exclk = 1 ? mcs = 1 xt1 oscillation can be stopped (oscsels = 0). chapter 5 clock generator user?s manual u18329ej4v0ud 181 5.6.8 time required for switchover of cpu clock and main system clock by setting bits 0 to 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc), the cpu clock can be switched (between the main system clock and the s ubsystem clock) and the division ratio of the main system clock can be changed. the actual switchover operat ion is not performed immediately after rewr iting to pcc; operat ion continues on the pre-switchover clock for several clocks (see table 5-7 ). whether the cpu is oper ating on the main system clock or the sub system clock can be ascertained using bit 5 (cls) of the pcc register. table 5-7. time required for switchover of cpu clock and main system cl ock cycle division factor set value before switchover set value after switchover css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 16 clocks 16 clocks 16 clocks 16 clocks 2f xp /f sub clocks 0 0 1 8 clocks 8 clocks 8 clocks 8 clocks f xp /f sub clocks 0 1 0 4 clocks 4 clocks 4 clocks 4 clocks f xp /2f sub clocks 0 1 1 2 clocks 2 clocks 2 clocks 2 clocks f xp /4f sub clocks 0 1 0 0 1 clock 1 clock 1 clock 1 clock f xp /8f sub clocks 1 2 clocks 2 clocks 2 clo cks 2 clocks 2 clocks caution selection of the main system clock cycle division factor (pcc0 to pcc2) and switchover from the main system clock to the sub system clock (changing css from 0 to 1) should not be set simultaneously. simultaneous setting is possi ble, however, for selection of th e main system cl ock cycle division factor (pcc0 to pcc2) and switchover from th e subsystem clock to th e main system clock (changing css from 1 to 0). remarks 1. the number of clocks listed in table 5-7 is the number of cpu clocks before switchover. 2. when switching the cpu clock from the main system clock to the subsystem clock, calculate the number of clocks by rounding up to the next clo ck and discarding the decimal portion, as shown below. example when switching cpu clock from f xp /2 to f sub /2 (@ oscillation with f xp = 10 mhz, f sub = 32.768 khz) f xp /f sub = 10000/32.768 ? 305.1 306 clocks by setting bit 0 (mcm0) of the main clock mode register (mcm), the main system clo ck can be switch ed (between the internal high-speed oscillation clock and the high-speed system clock). the actual switchover oper ation is not performed immediately after re writing to mcm0; operation continues on the pre-switchover clock for several clocks (see table 5-8 ). whether the cpu is operating on the internal high-speed oscillation cloc k or the high-speed system clock can be ascertained using bit 1 (mcs) of mcm. chapter 5 clock generator user?s manual u18329ej4v0ud 182 table 5-8. maximum time required for main system clock switchover set value before switchover set value after switchover mcm0 mcm0 0 1 0 1 + 2f rh /f xh clock 1 1 + 2f xh /f rh clock caution when switching the intern al high-speed oscillation clock to the high-speed system clock, bit 2 (xsel) of mcm must be set to 1 in advance. the value of xsel can be changed only once after a reset release. remarks 1. the number of clocks listed in table 5-8 is t he number of main system clocks before switchover. 2. calculate the number of clocks in t able 5-8 by removing the decimal portion. example when switching the main system clock from the internal high-speed oscillation clock to the high-speed system clock (@ oscillation with f rh = 8 mhz, f xh = 10 mhz) 1 + 2f rh /f xh = 1 + 2 8/10 = 1 + 2 0.8 = 1 + 1.6 = 2.6 2 clocks 5.6.9 conditions before cl ock oscillation is stopped the following lists the register flag settings for stopping th e clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. table 5-9. conditions before the clo ck oscillation is stopped and flag settings clock conditions before clock oscillation is stopped (external clock input disabled) flag settings of sfr register internal high-speed oscillation clock mcs = 1 or cls = 1 (the cpu is operating on a clock ot her than the internal high-speed oscillation clock) rstop = 1 x1 clock external main system clock mcs = 0 or cls = 1 (the cpu is operating on a clock other than the high-speed system clock) mstop = 1 xt1 clock cls = 0 (the cpu is operating on a clock other than the subsystem clock) oscsels = 0 chapter 5 clock generator user?s manual u18329ej4v0ud 183 5.6.10 peripheral hardware and source clocks the following lists peripheral hardware and source clocks incorpor ated in the 78k0/lf3. table 5-10. peripheral ha rdware and source clocks source clock peripheral hardware peripheral hardware clock (f prs ) subsystem clock (f sub ) internal low-speed oscillation clock (f rl ) tm50 output tm52 output tmh1 output external clock from peripheral hardware pins 16-bit timer/ event counter 00 y y n n y n y (ti000 pin) note 50 y n n n n n y (ti50 pin) note 51 y n n n n y y (ti51 pin) note 8-bit timer/ event counter 52 y n n n n n y (ti52 pin) note h0 y n n y n n n h1 y n y n n n n 8-bit timer h2 y n n n n n n real-time counter y y n n n n n watchdog timer n n y n n n n buzzer output y n n n n n n clock output y y n n n n n successive approximation type a/d converter y n n n n n n ? type a/d converter y y n n n n n uart0 y n n y n n n uart6 y n n y n n n csi10 y n n n n n y (sck10 pin) note serial interface csia0 y n n n n n y (scka0 pin) note lcd controller/driver y y y n n n n manchester code generator y n n n n n n remote controller receiver y y n n n n n note when the cpu is operating on the s ubsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of thes e functions on the external clock input from peripheral hardware pins. remark y: can be selected, n: cannot be selected user?s manual u18329ej4v0ud 184 chapter 6 16-bit timer/event counter 00 6.1 functions of 16-bit timer/event counter 00 16-bit timer/event counter 00 has the following functions. (1) interval timer 16-bit timer/event counter 00 generates an inte rrupt request at the preset time interval. (2) square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. (3) external event counter 16-bit timer/event counter 00 c an measure the number of pulses of an externally input signal. (4) one-shot pulse output 16-bit timer event counter 00 can output a one-shot pulse whose output pulse width can be set freely. (5) ppg output 16-bit timer/event counter 00 can output a rectangular wa ve whose frequency and output pulse width can be set freely. (6) pulse width measurement 16-bit timer/event counter 00 can measure the pulse width of an externally input signal. (7) external 24-bit event counter 16-bit timer/event counter 00 can be op erated to function as an external 24- bit event counter, by connecting 16- bit timer 00 and 8-bit timer/event counter 52 in cascade, and using the external event counter function of 8-bit timer/event counter 52. when using it as an external 24-bit event counter, extern al event input gate enable can be controlled via 8-bit timer counter h2 output. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 185 6.2 configuration of 16-bit timer/event counter 00 16-bit timer/event counter 00 includes the following hardware. table 6-1. configuration of 16-bit timer/event counter 00 item configuration time/counter 16-bit timer counter 00 (tm00) register 16-bit timer capture/compare registers 000, 010 (cr000, cr010) timer input ti000, ti010 pins timer output to00 pin, output controller control registers 16-bit timer mode control register 00 (tmc00) capture/compare control register 00 (crc00) 16-bit timer output control register 00 (toc00) prescaler mode register 00 (prm00) input switch control register (isc) port mode register 3 (pm3) port register 3 (p3) remark when using 16-bit timer/event counter 00 as an external 24-bit event counter, 8-bit timer/event counter 52 (tm52) and 8-bit timer counter h2 (tmh2) are used. for details, see 6.4.9 external 24- bit event counter operation . figures 6-1 shows the block diagrams. figure 6-1. block diagram of 16-bit timer/event counter 00 internal bus capture/compare control register 00 (crc00) ti010/to00/p34/ti52/ rtc1hz/intp1 prescaler mode register 00 (prm00) 3 prm002 prm001 crc002 16-bit timer capture/compare register 010 (cr010) match match 16-bit timer counter 00 (tm00) clear noise elimi- nator crc002 crc001 crc000 inttm000 to00/ti010/p34/ti52/ rtc1hz/intp1 inttm010 16-bit timer output control register 00 (toc00) 16-bit timer mode control register 00 (tmc00) internal bus tmc003 tmc002 tmc001 ovf00 toc004 lvs00 lvr00 toc001 toe00 selector 16-bit timer capture/compare register 000 (cr000) selector selector selector noise elimi- nator noise elimi- nator output controller ospe00 ospt00 output latch (p34) pm34 to cr010 prm000 tm52 output ti000/p33/rtcdiv/ rtccl/buz/intp2 isc4 isc1 isc5 p113/rxd6 p15/rxd6 input switch control register (isc) selector selector f prs f prs /2 2 f prs /2 8 f prs f prs /2 4 f sub f prs /2 to00 output cautions 1. the valid edge of ti010 and timer output (to00) cannot be used fo r the p34 pin at the same time. select either of the functions. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 186 cautions 2. if clearing of bits 3 and 2 (tmc003 a nd tmc002) of 16-bit timer mode control register 00 (tmc00) to 00 and input of the capture trigger c onflict, then the capture d data is undefined. 3. to change the mode from the capture mode to the comparison mode, first clear the tmc003 and tmc002 bits to 00, and then change the setting. a value that has been once captured remains stored in cr000 unless the device is reset. if the mode has been changed to the comparis on mode, be sure to set a comparison value. (1) 16-bit timer counter 00 (tm00) tm00 is a 16-bit read-only regist er that counts count pulses. the counter is incremented in synchronization with the rising edge of the count clock. figure 6-2. format of 16-bit timer counter 00 (tm00) tm00 ff11h ff10h address: ff10h, ff11h after reset: 0000h r 1514131211109876543210 the count value of tm00 can be read by reading tm00 when the value of bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (tmc00) is other th an 00. the value of tm00 is 0000h if it is read when tmc003 and tmc002 = 00. the count value is reset to 0000h in the following cases. ? at reset signal generation ? if tmc003 and tmc002 are cleared to 00 ? if the valid edge of the ti000 pin is input in the mode in which the clear & start occurs when inputting the valid edge to the ti000 pin ? if tm00 and cr000 match in the mode in which the clear & start occurs when tm00 and cr000 match ? ospt00 is set to 1 in one-shot pulse output m ode or the valid edge is input to the ti000 pin caution even if tm00 is read, th e value is not captured by cr010. (2) 16-bit timer capture/compare regi ster 000 (cr000), 16-bit timer cap ture/compare register 010 (cr010) cr000 and cr010 are 16-bit registers that are used with a capture function or compar ison function selected by using crc00. change the value of cr000 while the timer is stopped (tmc003 and tmc002 = 00). the value of cr010 can be changed during operation if the val ue has been set in a specific way. for details, see 6.5.1 rewriting cr010 during tm00 operation . these registers can be read or written in 16-bit units. reset signal generation sets these registers to 0000h. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 187 figure 6-3. format of 16-bit timer ca pture/compare register 000 (cr000) cr000 ff13h ff12h address: ff12h, ff13h after reset: 0000h r/w 1514131211109876543210 (i) when cr000 is used as a compare register the value set in cr000 is constantly compared with the tm00 count value, and an interrupt request signal (inttm000) is generated if they match. t he value is held until cr000 is rewritten. caution cr000 does not perform the capture operati on when it is set in the comparison mode, even if a capture trigger is input to it. (ii) when cr000 is used as a capture register the count value of tm00 is captured to cr000 when a capture trigger is input. as the capture trigger, an edge of a phas e reverse to that of the ti000 pin or the valid edge of the ti010 pin can be selected by using crc00 or prm00. figure 6-4. format of 16-bit timer ca pture/compare register 010 (cr010) cr010 ff15h ff14h address: ff14h, ff15h after reset: 0000h r/w 1514131211109876543210 (i) when cr010 is used as a compare register the value set in cr010 is constantly compared with the tm00 count value, and an interrupt request signal (inttm010) is generated if they match. caution cr010 does not perform the capture operati on when it is set in the comparison mode, even if a capture trigger is input to it. (ii) when cr010 is used as a capture register the count value of tm00 is captured to cr010 when a capture trigger is input. it is possible to select the valid edge of the ti000 pin as the capture trigger. the ti000 pin valid edge is set by prm00. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 188 (iii) setting range when cr000 or cr 010 is used as a compare register when cr000 or cr010 is used as a compare register, set it as shown below. operation cr000 register setting range cr010 register setting range operation as interval timer operation as square-wave output operation as external event counter 0000h < n ffffh 0000h note m ffffh normally, this setting is not used. mask the match interrupt signal (inttm010). operation in the clear & start mode entered by ti000 pin valid edge input operation as free-running timer 0000h note n ffffh 0000h note m ffffh operation as ppg output m < n ffffh 0000h note m < n operation as one-shot pulse output 0000h note n ffffh (n m) 0000h note m ffffh (m n) note when 0000h is set, a match interrupt immediately after the timer operation does not occur and timer output is not changed, and the first match timing is as follows . a match interrupt occurs at the timing when the timer counter (tm00 register) is changed from 0000h to 0001h. ? when the timer counter is cleared due to overflow ? when the timer counter is cleared due to ti000 pin valid edge (when clear & start mode is entered by ti000 pin valid edge input) ? when the timer counter is cleared due to compare ma tch (when clear & start mode is entered by match between tm00 and cr000 (cr000 = other than 0000h, cr010 = 0000h)) operation enabled (other than 00) tm00 register timer counter clear interrupt signal is not generated interrupt signal is generated timer operation enable bit (tmc003, tmc002) interrupt request signal compare register set value (0000h) operation disabled (00) remarks 1. n: cr000 register set value, m: cr010 register set value 2. for details of tmc003 and tmc002, see 6.3 (1) 16-bit timer mode control register 00 (tmc00) . chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 189 table 6-2. capture operation of cr000 and cr010 external input signal capture operation ti000 pin input ti010 pin input set values of es001 and es000 position of edge to be captured set values of es101 and es100 position of edge to be captured 01: rising 01: rising 00: falling 00: falling crc001 = 1 ti000 pin input (reverse phase) 11: both edges (cannot be captured) crc001 bit = 0 ti010 pin input 11: both edges capture operation of cr000 interrupt signal inttm000 signal is not generated even if value is captured. interrupt signal inttm000 signal is generated each time value is captured. set values of es001 and es000 position of edge to be captured 01: rising 00: falling ti000 pin input note 11: both edges capture operation of cr010 interrupt signal inttm010 signal is generated each time value is captured. note the capture operation of cr010 is not affected by the setting of the crc001 bit. caution to capture the count value of the tm00 regi ster to the cr000 register by using the phase reverse to that input to the ti 000 pin, the interrupt request si gnal (inttm000) is not generated after the value has been captured. if the valid edge is de tected on the ti010 pin during this operation, the capture operation is not performed but the inttm 000 signal is generated as an external interrupt signal. to not use th e external interrupt, mask the inttm000 signal. remark crc001: see 6.3 (2) capture/compare control register 00 (crc00) . es101, es100, es001, es000: see 6.3 (4) prescaler mode register 00 (prm00) . chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 190 6.3 registers controlling 16- bit timer/event counter 00 registers used to control 16-bit time r/event counter 00 are shown below. ? 16-bit timer mode control register 00 (tmc00) ? capture/compare contro l register 00 (crc00) ? 16-bit timer output control register 00 (toc00) ? prescaler mode register 00 (prm00) ? input switch control register (isc) ? port mode register 3 (pm3) ? port register 3 (p3) (1) 16-bit timer mode control register 00 (tmc00) tmc00 is an 8-bit register that sets the 16-bit time r/event counter 00 operation mode, tm00 clear mode, and output timing, and detects an overflow. rewriting tmc00 is prohibited during operation (when tm c003 and tmc002 = other than 00). however, it can be changed when tmc003 and tmc002 are cleared to 00 (s topping operation) and when ovf00 is cleared to 0. tmc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets tmc00 to 00h. caution 16-bit timer/event counter 00 starts operati on at the moment tmc002 and tmc003 are set to values other than 00 (operation stop mode), respectively. set tmc002 and tmc003 to 00 to stop the operation. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 191 figure 6-5. format of 16-bit timer mode control register 00 (tmc00) address: ffbah after reset: 00h r/w symbol 7 6 5 4 3 2 1 <0> tmc00 0 0 0 0 tmc003 tmc002 tmc001 ovf00 tmc003 tmc002 operation enable of 16-bit timer/event counter 00 0 0 disables 16-bit timer/event counter 00 ope ration. stops supplyi ng operating clock. clears 16-bit timer counter 00 (tm00). 0 1 free-running timer mode 1 0 clear & start mode entered by ti000 pin valid edge input note 1 1 clear & start mode entered upon a match between tm00 and cr000 tmc001 condition to reverse timer output (to00) 0 ? match between tm00 and cr000 or match between tm00 and cr010 1 ? match between tm00 and cr000 or match between tm00 and cr010 ? trigger input of ti000 pin valid edge ovf00 tm00 overflow flag clear (0) clears ovf00 to 0 or tmc003 and tmc002 = 00 set (1) overflow occurs. ovf00 is set to 1 when the value of tm00 changes from ffffh to 0000h in all the operation modes (free-running timer mode, clear & start mode entered by ti000 pin valid edge input, and clear & start mode entered upon a match between tm00 and cr000). it can also be set to 1 by writing 1 to ovf00. note the ti000 pin valid edge is set by bits 5 and 4 ( es001, es000) of prescaler mode register 00 (prm00). chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 192 (2) capture/compare control register 00 (crc00) crc00 is the register that controls the operation of cr000 and cr010. changing the value of crc00 is prohibited during oper ation (when tmc003 and tmc002 = other than 00). crc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears crc00 to 00h. figure 6-6. format of capture/comp are control register 00 (crc00) address: ffbch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 crc00 0 0 0 0 0 crc002 crc001 crc000 crc002 cr010 operating mode selection 0 operates as compare register 1 operates as capture register crc001 cr000 capture trigger selection 0 captures on valid edge of ti010 pin 1 captures on valid edge of ti000 pin by reverse phase note the valid edge of the ti010 and ti000 pin is set by prm00. if es001 and es000 are set to 11 (both edges) when crc001 is 1, the valid edge of the ti000 pin cannot be detected. crc000 cr000 operating mode selection 0 operates as compare register 1 operates as capture register if tmc003 and tmc002 are set to 11 (clear & start mode entered upon a match between tm00 and cr000), be sure to set crc000 to 0. note when the valid edge is detected from the ti010 pin, the capture opera tion is not performed but the inttm000 signal is generated as an external interrupt signal. caution to ensure that the capture operation is perf ormed properly, the capture trigger requires a pulse two cycles longer than the count clock selected by prescaler mode register 00 (prm00). chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 193 figure 6-7. example of cr010 capture operat ion (when rising edge is specified) count clock tm00 ti000 rising edge detection cr010 inttm010 n ? 3n ? 2n ? 1 n n + 1 n valid edge (3) 16-bit timer output control register 00 (toc00) toc00 is an 8-bit register t hat controls to00 output. toc00 can be rewritten while only ospt00 is oper ating (when tmc003 and tmc002 = other than 00). rewriting the other bits is prohibited during operation. however, toc004 can be rewritten during timer operation as a means to rewrite cr010 (see 6.5.1 rewriting cr010 during tm00 operation ). toc00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears toc00 to 00h. caution be sure to set toc00 using the following procedure. <1> set toc004 and toc001 to 1. <2> set only toe00 to 1. <3> set either of lvs00 or lvr00 to 1. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 194 figure 6-8. format of 16-bit timer ou tput control register 00 (toc00) address: ffbdh after reset: 00h r/w symbol 7 <6> <5> 4 <3> <2> 1 <0> toc00 0 ospt00 ospe00 toc004 lvs00 lvr00 toc001 toe00 ospt00 one-shot pulse out put trigger via software 0 ? 1 one-shot pulse output the value of this bit is always ?0? when it is read. do not set this bit to 1 in a mode other than the one- shot pulse output mode. if it is set to 1, tm00 is cleared and started. ospe00 one-shot pulse output operation control 0 successive pulse output 1 one-shot pulse output one-shot pulse output operates correctly in the fr ee-running timer mode or clear & start mode entered by ti000 pin valid edge input. the one-shot pulse cannot be output in the clear & start mode entered upon a match between tm00 and cr000. toc004 to00 output control on match between cr010 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm010) is generated even when toc004 = 0. lvs00 lvr00 setting of to00 pin output status 0 0 no change 0 1 initial value of to00 output is low level (to00 output is cleared to 0). 1 0 initial value of to00 output is high level (to00 output is set to 1). 1 1 setting prohibited ? lvs00 and lvr00 can be used to set the initial value of the to00 output level. if the initial value does not have to be set, leave lvs00 and lvr00 as 00. ? be sure to set lvs00 and lvr00 when toe00 = 1. lvs00, lvr00, and toe00 being simultaneously set to 1 is prohibited. ? lvs00 and lvr00 are trigger bits. by setting these bits to 1, the initial value of the to00 output level can be set. even if these bits are cleared to 0, to00 output is not affected. ? the values of lvs00 and lvr00 are always 0 when they are read. ? for how to set lvs00 and lvr00, see 6.5.2 setting lvs00 and lvr00 . ? the actual to00/ti010/p34/ti52/rtc1hz/intp1 pin output is determined depending on pm34 and p34, besides to00 output. toc001 to00 output control on match between cr000 and tm00 0 disables inversion operation 1 enables inversion operation the interrupt signal (inttm000) is generated even when toc001 = 0. toe00 to00 output control 0 disables output (to00 output fixed to low level) 1 enables output chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 195 (4) prescaler mode register 00 (prm00) prm00 is the register that se ts the tm00 count clock and ti000 and ti010 pin input valid edges. rewriting prm00 is prohibited during operati on (when tmc003 and tmc002 = other than 00). prm00 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets prm00 to 00h. cautions 1. do not apply the following setting when setting the prm001 and prm000 bits to 11 (to specify the valid edge of th e ti000 pin as a count clock). ? clear & start mode entered by the ti000 pin valid edge ? setting the ti000 pin as a capture trigger 2. if the operation of the 16- bit timer/event counter 00 is enable d when the ti000 or ti010 pin is at high level and when the valid edge of the ti000 or ti010 pin is specified to be the rising edge or both edges, th e high level of the ti000 or ti010 pi n is detected as a rising edge. note this when the ti000 or ti010 pin is pulled up. however, the rising edge is not detected when the timer operation has been once stopped and then is enabled again. 3. the valid edge of ti010 and timer output (to 00) cannot be used for the p34 pin at the same time. select either of the functions. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 196 figure 6-9. format of prescaler mode register 00 (prm00) address: ffbbh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 prm00 es101 es100 es001 es000 0 prm002 prm001 prm000 es101 es100 ti010 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges es001 es000 ti000 pin valid edge selection 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both falling and rising edges count clock selection note 1 prm002 prm001 prm000 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz 0 0 0 f prs note 2 2 mhz 5 mhz 10 mhz 0 0 1 f prs /2 1 mhz 2.5 mhz 5 mhz 0 1 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 0 1 1 f prs /2 4 1.25 mhz 2.5 mhz 625 khz 1 0 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 1 0 1 f sub 32.768 khz 1 1 0 ti000 valid edge note 3 1 1 1 tm52 output notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of prm002 = prm001 = prm000 = 0 (count clock: f prs ) is prohibited. 3. the external clock from the ti000 pin requires a pulse longer than twice the cycle of the peripheral hardware clock (f prs ). caution do not select the valid edge of ti000 as the count clock during the pu lse width measurement. remarks 1. 8-bit timer/event counter 52 (tm52) output can be selected as the tm00 count clock by setting prm002, prm001, prm000 = 1, 1, 1. any frequen cy can be set as the 16-bit timer (tm00) count clock, depending on the tm52 count clock and compare register setting values. 2. f prs : peripheral hardware clock frequency f sub : subsystem clock frequency chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 197 (5) input switch control register (isc) the input source to ti000 becomes the input signal from the p33/ti000 pin, by setting isc1 to 0. isc can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets isc to 00h. figure 6-10. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 ics5 ics4 ics3 ics2 ics1 ics0 ics5 ics4 txd6, rxd6 input source selection 0 0 txd6:p112, rxd6: p113 0 1 txd6:p16, rxd6: p15 other than above setting prohibited isc3 rxd6/p113 input enabled/disabled 0 r x d6/p113 input disabled 1 r x d6/p113 input enabled isc2 ti52 input source control 0 no enable control of ti52 input (p34) 1 enable controlled of ti52 input (p34) note 1 isc1 ti000 input source selection 0 ti000 (p33) 1 rxd6 (p15 or p113 note 2 ) isc0 intp0 input source selection 0 intp0 (p120) 1 r x d6 (p15 or p113 note 2 ) notes 1. ti52 input is controlled by toh2 output signal. 2. this is selected by isc5 and isc4. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 198 (6) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p34/ti52/ti 010/to00/rtc1hz/intp1 pin for timer output , set pm34 and the output latches of p34 to 0. when using the p33/ti000/rtcdiv/rt ccl/buz/intp2 and p34/ti52/ti010/to 00/rtc1hz/intp1 pins for timer input, set pm33 and pm34 to 1. at this time, the output latches of p33 and p34 may be 0 or 1. pm3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm3 to ffh. figure 6-11. format of port mode register 3 (pm3) 7 1 6 1 5 1 4 pm34 3 pm33 2 pm32 1 pm31 0 pm30 symbol pm3 address: ff23h after reset: ffh r/w pm3n 0 1 p3n pin i/o mode selection (n = 0 to 4) output mode (output buffer on) input mode (output buffer off) chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 199 6.4 operation of 16-bit timer/event counter 00 6.4.1 interval timer operation if bits 3 and 2 (tmc003 and tmc002) of the 16-bit timer mode co ntrol register (tmc00) are set to 11 (clear & start mode entered upon a match between tm00 and cr000), the count operation is started in synchronization with the count clock. when the value of tm00 later matches the value of cr000, tm00 is cleared to 0000h and a match interrupt signal (inttm000) is generated. this inttm000 signal ena bles tm00 to operate as an interval timer. remarks 1. for the setting of i/o pins, see 6.3 (6) port mode register 3 (pm3) . 2. for how to enable the inttm000 interrupt, see chapter 21 interrupt functions . figure 6-12. block diagram of interval timer operation 16-bit counter (tm00) cr000 register operable bits tmc003, tmc002 count clock clear match signal inttm000 signal figure 6-13. basic timing exampl e of interval timer operation tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) compare match interrupt (inttm000) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 200 figure 6-14. example of register se ttings for interval timer operation (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register (c) 16-bit timer output control register 00 (toc00) 00000 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 000 (d) prescaler mode register 00 (prm00) 00000 3 prm002 prm001 prm000 es101 es100 es001 es000 selects count clock 0/1 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) if m is set to cr000, the interval time is as follows. ? interval time = (m + 1) count clock cycle setting cr000 to 0000h is prohibited. (g) 16-bit capture/compare register 010 (cr010) usually, cr010 is not used for the interval timer func tion. however, a compare match interrupt (inttm010) is generated when the set value of cr010 matches the value of tm00. therefore, mask the interrupt request by using the interrupt mask flag (tmmk010). chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 201 figure 6-15. example of software pr ocessing for interval timer function tm00 register 0000h operable bits (tmc003, tmc002) cr000 register inttm000 signal n 11 00 n n n <1> <2> tmc003, tmc002 bits = 11 tmc003, tmc002 bits = 00 register initial setting prm00 register, crc00 register, cr000 register, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. start stop <1> count operation start flow <2> count operation stop flow chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 202 6.4.2 square wave output operation when 16-bit timer/event counter 00 operates as an interval timer (see 6.4.1 ), a square wave can be output from the to00 pin by setting the 16-bit timer output control register 00 (toc00) to 03h. when tmc003 and tmc002 are set to 11 (count clear & start mode entered upon a match between tm00 and cr000), the counting operation is started in synchronizat ion with the count clock. when the value of tm00 later matches the value of cr000, tm00 is cleared to 0000h, an interrupt signal (inttm000) is generated, and to00 output is inverted. this to00 output that is inverted at fixed intervals enables to00 to output a square wave. remarks 1. for the setting of i/o pins, see 6.3 (6) port mode register 3 (pm3) . 2. for how to enable the inttm000 signal interrupt, see chapter 21 interrupt functions . figure 6-16. block diagram of square wave output operation 16-bit counter (tm00) cr000 register operable bits tmc003, tmc002 count clock clear match signal inttm000 signal output controller to00 pin to00 output figure 6-17. basic timing example of square wave output operation tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) to00 output compare match interrupt (inttm000) n 11 00 n n n n interval (n + 1) interval (n + 1) interval (n + 1) interval (n + 1) chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 203 figure 6-18. example of register setti ngs for square wave output operation (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0 0 0 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output. inverts to00 output on match between tm00 and cr000. 0/1 1 1 specifies initial value of to00 output f/f (d) prescaler mode register 00 (prm00) 00000 3 prm002 prm001 prm000 es101 es100 es001 es000 selects count clock 0/1 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) if m is set to cr000, the interval time is as follows. ? square wave frequency = 1 / [2 (m + 1) count clock cycle] setting cr000 to 0000h is prohibited. (g) 16-bit capture/compare register 010 (cr010) usually, cr010 is not used for the square wave outpu t function. however, a compare match interrupt (inttm010) is generated when the set valu e of cr010 matches the value of tm00. therefore, mask the interrupt request by using the interrupt mask flag (tmmk010). chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 204 figure 6-19. example of software proce ssing for square wave output function tm00 register 0000h operable bits (tmc003, tmc002) cr000 register to00 output inttm000 signal to00 output control bit (toc001, toe00) tmc003, tmc002 bits = 11 tmc003, tmc002 bits = 00 register initial setting prm00 register, crc00 register, toc00 register note , cr000 register, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. start stop <1> count operation start flow <2> count operation stop flow n 11 00 n n n <1> <2> 00 note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 205 6.4.3 external event counter operation when bits 1 and 0 (prm001 and prm000) of the prescaler m ode register 00 (prm00) are set to 11 (for counting up with the valid edge of the ti000 pin) and bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (tmc00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between tm00 and cr000 (inttm000) is generated. to input the external event, the ti000 pin is used. th erefore, the timer/event co unter cannot be used as an external event counter in the clear & start mode enter ed by the ti000 pin valid edge input (when tmc003 and tmc002 = 10). the inttm000 signal is generated with the following timing. ? timing of generation of inttm000 signal (second time or later) = number of times of detection of valid edge of external event (set value of cr000 + 1) however, the first match interrupt immediately after the timer/event counter has start ed operating is generated with the following timing. ? timing of generation of inttm000 signal (first time only) = number of times of detection of valid edge of external event input (set value of cr000 + 2) to detect the valid edge, the signal input to t he ti000 pin is sampled during the clock cycle of f prs . the valid edge is not detected until it is detected two times in a row. t herefore, a noise with a short pul se width can be eliminated. remarks 1. for the setting of i/o pins, see 6.3 (6) port mode register 3 (pm3) . 2. for how to enable the inttm000 signal interrupt, see chapter 21 interrupt functions . figure 6-20. block diagram of ex ternal event counter operation 16-bit counter (tm00) cr000 register operable bits tmc003, tmc002 clear match signal inttm000 signal f prs edge detection ti000 pin output controller to00 pin to00 output chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 206 figure 6-21. example of register settings in external event counter mode (1/2) (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0 0 0/1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 0/1 0/1 0/1 0: disables to00 output 1: enables to00 output 00: does not invert to00 output on match between tm00 and cr000/cr010. 01: inverts to00 output on match between tm00 and cr000. 10: inverts to00 output on match between tm00 and cr010. 11: inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output f/f (d) prescaler mode register 00 (prm00) 0 0 0/1 0/1 0 3 prm002 prm001 prm000 es101 es100 es001 es000 selects count clock (specifies valid edge of ti000). 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 110 chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 207 figure 6-21. example of register settings in external event counter mode (2/2) (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) if m is set to cr000, the interrupt signal (inttm000) is generated when the num ber of external events reaches (m + 1). setting cr000 to 0000h is prohibited. (g) 16-bit capture/compare register 010 (cr010) usually, cr010 is not used in the external event counter mode. however, a compare match interrupt (inttm010) is generated when the set valu e of cr010 matches the value of tm00. therefore, mask the interrupt request by using the interrupt mask flag (tmmk010). chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 208 figure 6-22. example of software proce ssing in external event counter mode tm00 register 0000h operable bits (tmc003, tmc002) 11 00 n n n tmc003, tmc002 bits = 11 tmc003, tmc002 bits = 00 register initial setting prm00 register, crc00 register, toc00 register note , cr000 register, port setting start stop <1> <2> compare match interrupt (inttm000) compare register (cr000) to00 output control bits (toc004, toc001, toe00) to00 output n 00 initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 11. starts count operation the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. <1> count operation start flow <2> count operation stop flow note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 209 6.4.4 operation in clear & start mode entered by ti000 pin valid edge input when bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (tmc00) are set to 10 (clear & start mode entered by the ti000 pin va lid edge input) and the count clock (set by prm00) is supplied to the timer/event counter, tm00 starts counti ng up. when the valid edge of the ti 000 pin is detected during the counting operation, tm00 is cleared to 0000h a nd starts counting up again. if the valid edge of the ti000 pin is not detected, tm00 overflows and continues counting. the valid edge of the ti000 pin is a c ause to clear tm00. starting the counter is not controlled immediately after the start of the operation. cr000 and cr010 are used as compare registers and capture registers. (a) when cr000 and cr010 are used as compare registers signals inttm000 and inttm010 are generated when the va lue of tm00 matches the value of cr000 and cr010. (b) when cr000 and cr010 are used as capture registers the count value of tm00 is captur ed to cr000 and the inttm000 signal is generated when the valid edge is input to the ti010 pin (or when the phase reverse to that of the valid edge is input to the ti000 pin). when the valid edge is input to t he ti000 pin, the count value of tm00 is captured to cr010 and the inttm010 signal is generated. as soon as the count value has been captured, t he counter is cleared to 0000h. caution do not set the count clo ck as the valid edge of the ti000 pin (prm002, prm001, and prm000 = 110). when prm002, prm001, and prm000 = 110, tm00 is cleared. remarks 1. for the setting of the i/o pins, see 6.3 (6) port mode register 3 (pm3) . 2. for how to enable the inttm000 signal interrupt, see chapter 21 interrupt functions . (1) operation in clear & start mode en tered by ti000 pin valid edge input (cr000: compare register , cr010: compare register) figure 6-23. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: compare register, cr010: compare register) timer counter (tm00) clear output controller edge detection compare register (cr010) match signal to00 pin match signal interrupt signal (inttm000) interrupt signal (inttm010) ti000 pin compare register (cr000) operable bits tmc003, tmc002 count clock to00 output chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 210 figure 6-24. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: compare register, cr010: compare register) (a) toc00 = 13h, prm00 = 10h, crc00, = 00h, tmc00 = 08h tm00 register 0000h operable bits (tmc003, tmc002) count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to0 0 output m 10 m nn nn mmm 00 n (b) toc00 = 13h, prm00 = 10h, crc00, = 00h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output m 10 m nn nn mmm 00 n (a) and (b) differ as follows depending on the setting of bit 1 (tmc001) of the 16-bit timer mode control register 01 (tmc00). (a) the to00 output level is inverted wh en tm00 matches a compare register. (b) the to00 output level is inverted when tm00 matches a compare register or when the valid edge of the ti000 pin is detected. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 211 (2) operation in clear & start mode en tered by ti000 pin valid edge input (cr000: compare register , cr010: capture register) figure 6-25. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: compare register, cr010: capture register) timer counter (tm00) clear output controller edge detector capture register (cr010) capture signal to00 pin match signal interrupt signal (inttm000) interrupt signal (inttm010) ti000 pin compare register (cr000) operable bits tmc003, tmc002 count clock to00 output figure 6-26. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: compare register, cr010: capture register) (1/2) (a) toc00 = 13h, prm00 = 10h, crc00, = 04h, tmc00 = 08h, cr000 = 0001h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output 0001h 10 q p n m s 00 0000h m n s p q this is an application example where the to00 output level is inverted w hen the count value has been captured & cleared. the count value is captured to cr010 and tm00 is cleared (to 0000h) when the valid edge of the ti000 pin is detected. when the count value of tm00 is 0001h, a compare match interr upt signal (inttm000) is generated, and the to00 output level is inverted. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 212 figure 6-26. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: compare register, cr010: capture register) (2/2) (b) toc00 = 13h, prm00 = 10h, crc00, = 04h, tmc00 = 0ah, cr000 = 0003h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output 0003h 0003h 10 q p n m s 00 0000h m 4444 ns pq this is an application exampl e where the width set to cr0 00 (4 clocks in this example) is to be output from the to00 pin when the count value has been captured & cleared. the count value is captured to cr010, a capture interr upt signal (inttm010) is gener ated, tm00 is cleared (to 0000h), and the to00 output is invert ed when the valid edge of the ti000 pin is detected. when the count value of tm00 is 0003h (four clocks have been counted), a compare match inte rrupt signal (inttm000) is generated and the to00 output level is inverted. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 213 (3) operation in clear & start mode by entered ti000 pin valid edge input (cr000: capture register , cr010: compare register) figure 6-27. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: compare register) timer counter (tm00) clear output controller edge detection capture register (cr000) capture signal to00 pin match signal interrupt signal (inttm010) interrupt signal (inttm000) ti000 pin compare register (cr010) operable bits tmc003, tmc002 count clock to00 output chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 214 figure 6-28. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: compare register) (1/2) (a) toc00 = 13h, prm00 = 10h, crc00, = 03h, tmc00 = 08h, cr010 = 0001h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output 10 p n m s 00 l 0001h 0000h mns p this is an application example where the to00 output le vel is to be inverted when the count value has been captured & cleared. tm00 is cleared at the rising edge det ection of the ti000 pin and it is captured to cr000 at the falling edge detection of the ti000 pin. when bit 1 (crc001) of capture/compare control register 00 (crc00) is set to 1, the count value of tm00 is captured to cr000 in the phase reverse to that of the signa l input to the ti000 pin, but the capture interrupt signal (inttm000) is not generated. however, the inttm000 sig nal is generated when the valid edge of the ti010 pin is detected. mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 215 figure 6-28. timing example of clear & star t mode entered by ti000 pin valid edge input (cr000: capture register, cr010: compare register) (2/2) (b) toc00 = 13h, prm00 = 10h, crc00, = 03h, tmc00 = 0ah, cr010 = 0003h tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output 0003h 0003h 10 p n m s 00 4444 l 0000h m n s p this is an application exampl e where the width set to cr0 10 (4 clocks in this example) is to be output from the to00 pin when the count value has been captured & cleared. tm00 is cleared (to 0000h) at the rising edge detection of the ti000 pin and captur ed to cr000 at the falling edge detection of the ti000 pin. the to00 output is inverted when tm00 is cleared (to 0000h) because the rising edge of the ti000 pin has been detected or when t he value of tm00 matches that of a compare register (cr010). when bit 1 (crc001) of capture/compare control register 00 (crc00) is 1, the count value of tm00 is captured to cr000 in the phase reverse to that of the input si gnal of the ti000 pin, but th e capture interrupt signal (inttm000) is not generated. however, the inttm000 inte rrupt is generated when t he valid edge of the ti010 pin is detected. mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 216 (4) operation in clear & start mode en tered by ti000 pin valid edge input (cr000: capture register , cr010: capture register) figure 6-29. block diagram of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) timer counter (tm00) clear output controller capture register (cr000) capture signal capture signal to00 pin note interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin note selector to00 output note the timer output (to00) cannot be used when det ecting the valid edge of the ti010 pin is used. figure 6-30. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) (1/3) (a) toc00 = 13h, prm00 = 30h, crc00 = 05h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output 10 r s t o l m n p q 00 l 0000h 0000h lm nopqrst this is an application example where the count value is captured to cr010, tm00 is cleared, and the to00 output is inverted when the rising or fal ling edge of the ti000 pin is detected. when the edge of the ti010 pin is det ected, an interrupt signal (inttm000) is generated. mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 217 figure 6-30. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) (2/3) (b) toc00 = 13h, prm00 = c0h, crc00 = 05h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti010 pin input) capture register (cr000) capture interrupt (inttm000) capture & count clear input (ti000) capture register (cr010) capture interrupt (inttm010) 10 r s t o l m n p q 00 ffffh l l 0000h 0000h lmn o pq r s t this is a timing example where an edge is not input to the ti000 pin, in an applicatio n where the count value is captured to cr000 when the rising or fa lling edge of the ti010 pin is detected. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 218 figure 6-30. timing example of clear & start mode entered by ti000 pin valid edge input (cr000: capture register, cr010: capture register) (3/3) (c) toc00 = 13h, prm00 = 00h, crc00 = 07h, tmc00 = 0ah tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000 pin input) capture register (cr000) capture register (cr010) capture interrupt (inttm010) capture input (ti010) capture interrupt (inttm000) 0000h 10 p o m q r t s w n l 00 l l ln r pt 0000h moq sw this is an application example where the pulse width of the signal input to the ti000 pin is measured. by setting crc00, the count value can be captured to cr000 in the phase reverse to the falling edge of the ti000 pin (i.e., rising edge) and to cr010 at the falling edge of the ti000 pin. the high- and low-level widths of the input pulse can be calculated by the following expressions. ? high-level width = [cr010 value] ? [cr000 value] [count clock cycle] ? low-level width = [cr000 value] [count clock cycle] if the reverse phase of the ti000 pin is selected as a tri gger to capture the count value to cr000, the inttm000 signal is not generated. read the values of cr000 an d cr010 to measure the pulse width immediately after the inttm010 signal is generated. however, if the valid edge specified by bits 6 and 5 (e s101 and es100) of prescaler mode register 00 (prm00) is input to the ti010 pin, the count value is not captured but the inttm00 0 signal is generated. to measure the pulse width of the ti000 pin, mask the inttm000 signal when it is not used. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 219 figure 6-31. example of register settings in clear & st art mode entered by ti000 pin valid edge input (1/2) (a) 16-bit timer mode control register 00 (tmc00) 0000100/10 tmc003 tmc002 tmc001 ovf00 clears and starts at valid edge input of ti000 pin. 0: inverts to00 output on match between cr000 and cr010. 1: inverts to00 output on match between cr000 and cr010 and valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 000000/10/10/1 crc002 crc001 crc000 0: cr000 used as compare register 1: cr000 used as capture register 0: cr010 used as compare register 1: cr010 used as capture register 0: ti010 pin is used as capture trigger of cr000. 1: reverse phase of ti000 pin is used as capture trigger of cr000. (c) 16-bit timer output control register 00 (toc00) 0 0 0 0/1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 0: disables to00 output note 1: enables to00 output 00: does not invert to00 output on match between tm00 and cr000/cr010. 01: inverts to00 output on match between tm00 and cr000. 10: inverts to00 output on match between tm00 and cr010. 11: inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output f/f 0/1 0/1 0/1 note the timer output (to00) cannot be used when det ecting the valid edge of the ti010 pin is used. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 220 figure 6-31. example of register settings in clear & st art mode entered by ti000 pin valid edge input (2/2) (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 3 prm002 prm001 prm000 es101 es100 es001 es000 count clock selection (setting ti000 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc001 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0/1 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm000) is generated. the count value of tm00 is not cleared. to use this register as a capture regist er, select either the ti000 or ti010 pin note input as a capture trigger. when the valid edge of the capture tr igger is detected, the count va lue of tm00 is stored in cr000. note the timer output (to00) cannot be used when detection of the vali d edge of the ti010 pin is used. (g) 16-bit capture/compare register 010 (cr010) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm010) is generated. the count value of tm00 is not cleared. when this register is used as a capt ure register, the ti000 pi n input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm00 is stored in cr010. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 221 figure 6-32. example of software processing in clear & start mode entered by ti000 pin valid edge input tm00 register 0000h operable bits (tmc003, tmc002) count clear input (ti000 pin input) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output m 10 m n n n n mmm 00 <1> <2> <2> <2> <3> <2> 00 n tmc003, tmc002 bits = 10 edge input to ti000 pin register initial setting prm00 register, crc00 register, toc0 0 register note , cr000, cr010 registers, tmc00.tmc001 bit, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 10. starts count operation when the valid edge is input to the ti000 pin, the value of the tm00 register is cleared. start <1> count operation start flow <2> tm00 register clear & start flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <3> count operation stop flow note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 222 6.4.5 free-running timer operation when bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (t mc00) are set to 01 (free- running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. when it has counted up to ffffh, the over flow flag (ovf00) is set to 1 at t he next clock, and tm00 is cleared (to 0000h) and continues counting. clear ovf00 to 0 by executing the clr instruction via software. the following three types of free-runn ing timer operations are available. ? both cr000 and cr010 are used as compare registers. ? one of cr000 or cr010 is used as a compare regi ster and the other is us ed as a capture register. ? both cr000 and cr010 are used as capture registers. remarks 1. for the setting of the i/o pins, see 6.3 (6) port mode register 3 (pm3) . 2. for how to enable the inttm000 signal interrupt, see chapter 21 interrupt functions . (1) free-running timer mode operation (cr000: compare register , cr010: compare register) figure 6-33. block diagram of free-running timer mode (cr000: compare register, cr010: compare register) timer counter (tm00) output controller compare register (cr010) match signal to00 pin match signal interrupt signal (inttm000) interrupt signal (inttm010) compare register (cr000) operable bits tmc003, tmc002 count clock to00 output chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 223 figure 6-34. timing example of free-running timer mode (cr000: compare register, cr010: compare register) ? toc00 = 13h, prm00 = 00h, crc00 = 00h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output ovf00 bit 01 m n m n m n m n 00 00 n 0 write clear 0 write clear 0 write clear 0 write clear m this is an application example where two compare registers are used in the free-running timer mode. the to00 output level is reversed each time the count value of tm00 matches the set value of cr000 or cr010. when the count value matches the register val ue, the inttm000 or inttm010 signal is generated. (2) free-running timer mode operation (cr000: compare register , cr010: capture register) figure 6-35. block diagram of free-running timer mode (cr000: compare register, cr010: capture register) timer counter (tm00) output controller edge detection capture register (cr010) capture signal to00 pin match signal interrupt signal (inttm000) interrupt signal (inttm010) ti000 pin compare register (cr000) operable bits tmc003, tmc002 count clock to00 output chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 224 figure 6-36. timing example of free-running timer mode (cr000: compare register, cr010: capture register) ? toc00 = 13h, prm00 = 10h, crc00 = 04h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) compare register (cr000) compare match interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) to00 output overflow flag (ovf00) 0 write clear 0 write clear 0 write clear 0 write clear 01 m n s p q 00 0000h 0000h mn s p q this is an application example where a compare register an d a capture register are used at the same time in the free-running timer mode. in this example, the inttm000 signal is generated and t he to00 output is reversed each time the count value of tm00 matches the set value of cr000 (compare register). in addition, the inttm010 signal is generated and the count value of tm00 is captured to cr010 each ti me the valid edge of t he ti000 pin is detected. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 225 (3) free-running timer mode operation (cr000: capture register , cr010: capture register) figure 6-37. block diagram of free-running timer mode (cr000: capture register, cr010: capture register) timer counter (tm00) capture register (cr000) capture signal capture signal interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin selector remark if both cr000 and cr010 are used as capture regist ers in the free-running timer mode, the to00 output level is not inverted. however, it can be inverted each time the valid e dge of the ti000 pin is detec ted if bit 1 (tmc001) of 16-bit timer mode control register 00 (tmc00) is set to 1. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 226 figure 6-38. timing example of free-running timer mode (cr000: capture register, cr010: capture register) (1/2) (a) toc00 = 13h, prm00 = 50h, crc00 = 05h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) overflow flag (ovf00) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q this is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stor ed in separate capture registers in the free-running timer mode. the count value is captured to cr010 when the valid edge of the ti000 pi n input is detected and to cr000 when the valid edge of the ti010 pin input is detected. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 227 figure 6-38. timing example of free-running timer mode (cr000: capture register, cr010: capture register) (2/2) (b) toc00 = 13h, prm00 = c0h, crc00 = 05h, tmc00 = 04h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) 01 l m p s n o r q t 00 0000h 0000h lmn o pq r s t l l this is an application example wh ere both the edges of the ti010 pin ar e detected and the count value is captured to cr000 in the free-running timer mode. when both cr000 and cr010 are used as capture register s and when the valid edge of only the ti010 pin is to be detected, the count value cannot be captured to cr010. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 228 figure 6-39. example of register setti ngs in free-running timer mode (1/2) (a) 16-bit timer mode control register 00 (tmc00) 0000010/10 tmc003 tmc002 tmc001 ovf00 free-running timer mode 0: inverts to00 output on match between tm00 and cr000/cr010. 1: inverts to00 output on match between tm00 and cr000/cr010 and valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 000000/10/10/1 crc002 crc001 crc000 0: cr000 used as compare register 1: cr000 used as capture register 0: cr010 used as compare register 1: cr010 used as capture register 0: ti010 pin is used as capture trigger of cr000. 1: reverse phase of ti000 pin is used as capture trigger of cr000. (c) 16-bit timer output control register 00 (toc00) 0 0 0 0/1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 0: disables to00 output 1: enables to00 output 00: does not invert to00 output on match between tm00 and cr000/cr010. 01: inverts to00 output on match between tm00 and cr000. 10: inverts to00 output on match between tm00 and cr010. 11: inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output f/f 0/1 0/1 0/1 chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 229 figure 6-39. example of register setti ngs in free-running timer mode (2/2) (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 3 prm002 prm001 prm000 es101 es100 es001 es000 count clock selection (setting ti000 valid edge is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting prohibited when crc001 = 1) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0/1 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm000) is generated. the count value of tm00 is not cleared. to use this register as a capture register, select ei ther the ti000 or ti010 pin in put as a capture trigger. when the valid edge of the capture tr igger is detected, the count va lue of tm00 is stored in cr000. (g) 16-bit capture/compare register 010 (cr010) when this register is used as a compare register an d when its value matches the count value of tm00, an interrupt signal (inttm010) is generated. the count value of tm00 is not cleared. when this register is used as a capt ure register, the ti000 pi n input is used as a capture trigger. when the valid edge of the capture trigger is detected, the count value of tm00 is stored in cr010. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 230 figure 6-40. example of software pr ocessing in free-running timer mode ffffh tm0n register 0000h operable bits (tmc003, tmc002) compare register (cr003) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) timer output control bits (toe0, toc004, toc001) to00 output m 01 n n n n m m m 00 <1> <2> 00 n tmc003, tmc002 bits = 0, 1 register initial setting prm00 register, crc00 register, toc00 register note , cr000/cr010 register, tmc00.tmc001 bit, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits to 01. starts count operation start <1> count operation start flow tmc003, tmc002 bits = 0, 0 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <2> count operation stop flow note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 231 6.4.6 ppg output operation a square wave having a pulse width set in advance by cr010 is output from the to00 pin as a ppg (programmable pulse generator) signal during a cycle set by cr000 when bits 3 and 2 (tmc003 and tmc002) of 16- bit timer mode control register 00 (tmc00) are set to 11 (clear & start upon a match between tm00 and cr000). the pulse cycle and duty factor of the pulse generated as the ppg output are as follows. ? pulse cycle = (set value of cr000 + 1) count clock cycle ? duty = (set value of cr010 + 1) / (set value of cr000 + 1) caution to change the duty factor (value of cr010) during operation, see 6.5. 1 rewriting cr010 during tm00 operation. remarks 1. for the setting of i/o pins, see 6.3 (6) port mode register 0 (pm0) . 2. for how to enable the inttm000 signal interrupt, see chapter 21 interrupt functions . figure 6-41. block diagram of ppg output operation timer counter (tm00) clear output controller compare register (cr010) match signal to00 pin match signal interrupt signal (inttm000) interrupt signal (inttm010) compare register (cr000) operable bits tmc003, tmc002 count clock chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 232 figure 6-42. example of register settings for ppg output operation (a) 16-bit timer mode control register 00 (tmc00) 00001100 tmc003 tmc002 tmc001 ovf00 clears and starts on match between tm00 and cr000. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register cr010 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0 0 1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output 11: inverts to00 output on match between tm00 and cr000/cr010. 00: disables one-shot pulse output specifies initial value of to00 output f/f 0/1 1 1 (d) prescaler mode register 00 (prm00) 00000 3 prm002 prm001 prm000 es101 es100 es001 es000 selects count clock 0/1 0/1 0/1 (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) an interrupt signal (inttm000) is generated when the value of this register matches the count value of tm00. the count value of tm00 is cleared. (g) 16-bit capture/compare register 010 (cr010) an interrupt signal (inttm010) is generated when the value of this register matches the count value of tm00. the count value of tm00 is not cleared. caution set values to cr000 and cr010 such that the condition 0000h cr010 < cr000 ffffh is satisfied. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 233 figure 6-43. example of software pr ocessing for ppg output operation tm00 register 0000h operable bits (tmc003, tmc002) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) timer output control bits (toe00, toc004, toc001) to00 output m 11 m m m n n n 00 <1> n + 1 <2> 00 n tmc003, tmc002 bits = 11 register initial setting prm00 register, crc00 register, toc00 register note , cr000, cr010 registers, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits. starts count operation start <1> count operation start flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <2> count operation stop flow n + 1 n + 1 m + 1 m + 1 m + 1 note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . remark ppg pulse cycle = (m + 1) count clock cycle ppg duty = (n + 1)/(m + 1) chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 234 6.4.7 one-shot pulse output operation a one-shot pulse can be output by setting bits 3 and 2 (tmc003 and tmc002) of the 16-bit timer mode control register 00 (tmc00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the ti000 pin valid edge) and setting bit 5 (ospe00) of 16-bit timer ou tput control register 00 (toc00) to 1. when bit 6 (ospt00) of toc00 is set to 1 or when the valid edge is input to the ti000 pin during timer operation, clearing & starting of tm00 is triggered, and a pulse of the difference between the values of cr000 and cr010 is output only once from the to00 pin. cautions 1. do not input the trigger again (setting ospt00 to 1 or detecting the valid edge of the ti000 pin) while the one-shot pulse is output. to out put the one-shot pulse again, generate the trigger after the current one-s hot pulse output has completed. 2. to use only the setting of ospt00 to 1 as the trigger of one-shot pulse output, do not change the level of the ti000 pin or it s alternate function port pin. otherwise, the pulse will be unexpectedly output. remarks 1. for the setting of the i/o pins, see 6.3 (6) port mode register 3 (pm3) . 2. for how to enable the inttm000 signal interrupt, see chapter 21 interrupt functions . figure 6-44. block diagram of on e-shot pulse output operation timer counter (tm00) output controller compare register (cr010) match signal to00 pin match signal interrupt signal (inttm000) interrupt signal (inttm010) compare register (cr000) operable bits tmc003, tmc002 count clock ti000 edge detection ospt00 bit ospe00 bit clear to00 output chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 235 figure 6-45. example of register settings for one-shot pulse output operation (1/2) (a) 16-bit timer mode control register 00 (tmc00) 00000/10/100 tmc003 tmc002 tmc001 ovf00 01: free running timer mode 10: clear and start mode by valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 00000000 crc002 crc001 crc000 cr000 used as compare register cr010 used as compare register (c) 16-bit timer output control register 00 (toc00) 0 0/1 1 1 0/1 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 enables to00 output inverts to00 output on match between tm00 and cr000/cr010. specifies initial value of to00 output enables one-shot pulse output software trigger is generated by writing 1 to this bit (operation is not affected even if 0 is written to it). 0/1 1 1 (d) prescaler mode register 00 (prm00) 00000 3 prm002 prm001 prm000 es101 es100 es001 es000 selects count clock 0/1 0/1 0/1 chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 236 figure 6-45. example of register settings for one-shot pulse output operation (2/2) (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) this register is used as a compar e register when a one-shot pulse is output. when the value of tm00 matches that of cr000, an interrupt signal (inttm000) is generated and the to00 output level is inverted. (g) 16-bit capture/compare register 010 (cr010) this register is used as a compar e register when a one-shot pulse is output. when the value of tm00 matches that of cr010, an interrupt signal (inttm010) is generated and the to00 output level is inverted. caution do not set the same value to cr000 and cr010. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 237 figure 6-46. example of software processing for one-shot pulse output operation (1/2) ffffh tm00 register 0000h operable bits (tmc003, tmc002) one-shot pulse enable bit (ospe0) one-shot pulse trigger bit (ospt0) one-shot pulse trigger input (ti000 pin) overflow plug (ovf00) compare register (cr000) compare match interrupt (inttm000) compare register (cr010) compare match interrupt (inttm010) to00 output to00 output control bits (toe00, toc004, toc001) n m n ? m n ? m 01 or 10 00 00 n n n m m m m + 1 m + 1 <1> <2> <2> <3> to00 output level is not inverted because no one- shot trigger is input. ? time from when the one-shot pulse trigger is input until the one-shot pulse is output = (m + 1) count clock cycle ? one-shot pulse output active level width = (n ? m) count clock cycle chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 238 figure 6-46. example of software processing for one-shot pulse output operation (2/2) tmc003, tmc002 bits = 01 or 10 register initial setting prm00 register, crc00 register, toc00 register note , cr000, cr010 registers, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits. starts count operation start <1> count operation start flow <2> one-shot trigger input flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <3> count operation stop flow toc00.ospt00 bit = 1 or edge input to ti000 pin write the same value to the bits other than the ostp00 bit. note care must be exercised when setting toc00. for details, see 6.3 (3) 16-bit timer output control register 00 (toc00) . chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 239 6.4.8 pulse width measurement operation tm00 can be used to measure the pulse width of the signal input to the ti000 and ti010 pins. measurement can be accomplished by operating the 16-bit ti mer/event counter 00 in the free-running timer mode or by restarting the timer in synchronizati on with the signal input to the ti000 pin. when an interrupt is generated, read the value of the valid capture register and measure the pulse width. check bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc 00). if it is set (to 1), clear it to 0 by software. figure 6-47. block di agram of pulse width measureme nt (free-running timer mode) timer counter (tm00) capture register (cr000) capture signal capture signal interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin selector figure 6-48. block diagram of pulse width measurement (clear & start mode entered by ti000 pin valid edge input) timer counter (tm00) capture register (cr000) capture signal capture signal interrupt signal (inttm010) interrupt signal (inttm000) capture register (cr010) operable bits tmc003, tmc002 count clock edge detection ti000 pin edge detection ti010 pin clear selector chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 240 a pulse width can be measured in the following three ways. ? measuring the pulse width by using two input signals of the ti000 and ti010 pins (free-running timer mode) ? measuring the pulse width by using one input signal of the ti000 pin (free-running timer mode) ? measuring the pulse width by using one input signal of the ti000 pin (clear & start mode entered by the ti000 pin valid edge input) caution do not select the ti000 valid edge as the co unt clock when measuring the pulse width. remarks 1. for the setting of the i/o pins, see 6.3 (6) port mode register 3 (pm3) . 2. for how to enable the inttm000 signal interrupt, see chapter 21 interrupt functions . (1) measuring the pulse width by using two input si gnals of the ti000 and ti010 pins (free-running timer mode) set the free-running timer mode (tmc003 and tmc002 = 01). when the valid edge of t he ti000 pin is detected, the count value of tm00 is captured to cr010. when the valid edge of the ti 010 pin is detected, the count value of tm00 is captured to cr000. specify detecti on of both the edges of the ti000 and ti010 pins. by this measurement method, the prev ious count value is subt racted from the count valu e captured by the edge of each input signal. therefore, sa ve the previously captured value to a separate register in advance. if an overflow occurs, the value becomes negative if the pr eviously captured value is si mply subtracted from the current captured value and, t herefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addition, clear bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc00) to 0. figure 6-49. timing example of pulse width measurement (1) ? tmc00 = 04h, prm00 = f0h, crc00 = 05h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) overflow flag (ovf00) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h abc d e 0000h mn s p q chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 241 (2) measuring the pulse width by using one input signal of the ti000 pin (free-running mode) set the free-running timer mode (tmc003 and tmc002 = 01). the count value of tm00 is captured to cr000 in the phase reverse to the valid edge detec ted on the ti000 pin. when the valid edge of the ti000 pin is detected, the count value of tm00 is captured to cr010. by this measurement method, values are stored in se parate capture registers when a width from one edge to another is measured. theref ore, the capture values do not have to be saved. by subtracting the value of one capture register from that of a nother, a high-level width, low-level width, and cycle are calculated. if an overflow occurs, the value becomes negative if one c aptured value is simply subtracted from another and, therefore, a borrow occurs (bit 0 (cy) of the program status word (psw) is set to 1). if this happens, ignore cy and take the calculated value as the pulse width. in addi tion, clear bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc00) to 0. figure 6-50. timing example of pulse width measurement (2) ? tmc00 = 04h, prm00 = 10h, crc00 = 07h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr000) capture register (cr010) capture interrupt (inttm010) overflow flag (ovf00) capture trigger input (ti010) compare match interrupt (inttm000) 01 m a b c de n s p q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000h l l abc d e 0000h mn s p q chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 242 (3) measuring the pulse width by using one input signal of the ti000 pin (clear & start mode entered by the ti000 pin valid edge input) set the clear & start mode entered by the ti000 pin valid edge (tmc003 and tmc002 = 10). the count value of tm00 is captured to cr000 in the phase reverse to the valid edge of the ti000 pin, and the count value of tm00 is captured to cr010 and tm00 is cleared (0000h) when t he valid edge of the ti000 pin is detected. therefore, a cycle is stored in cr010 if tm00 does not overflow. if an overflow occurs, take the value that results from adding 10000h to the value stored in cr010 as a cycle. clear bit 0 (ovf00) of 16-bit timer mode control register 00 (tmc00) to 0. figure 6-51. timing example of pulse width measurement (3) ? tmc00 = 08h, prm00 = 10h, crc00 = 07h ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000) capture register (cr000) capture register (cr010) capture interrupt (inttm010) overflow flag (ovf00) capture trigger input (ti010) capture interrupt (inttm000) 10 <1> <2> <3> <3> <3> <3> <2> <2> <2> <1> <1> <1> m a b cd n s p q 00 00 0 write clear 0000h l l abc d 0000h mn s p q <1> pulse cycle = (10000h number of times ovf00 bit is set to 1 + captured value of cr010) count clock cycle <2> high-level pulse width = (10000h number of times ovf00 bit is set to 1 + captured value of cr000) count clock cycle <3> low-level pulse width = (pulse cycle ? high-level pulse width) chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 243 figure 6-52. example of register setti ngs for pulse width measurement (1/2) (a) 16-bit timer mode control register 00 (tmc00) 00000/10/100 tmc003 tmc002 tmc001 ovf00 01: free running timer mode 10: clear and start mode entered by valid edge of ti000 pin. (b) capture/compare cont rol register 00 (crc00) 0000010/11 crc002 crc001 crc000 1: cr000 used as capture register 1: cr010 used as capture register 0: ti010 pin is used as capture trigger of cr000. 1: reverse phase of ti000 pin is used as capture trigger of cr000. (c) 16-bit timer output control register 00 (toc00) 00000 lvr00 lvs00 toc004 ospe00 ospt00 toc001 toe00 000 (d) prescaler mode register 00 (prm00) 0/1 0/1 0/1 0/1 0 3 prm002 prm001 prm000 es101 es100 es001 es000 selects count clock (setting valid edge of ti000 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection (setting when crc001 = 1 is prohibited) 00: falling edge detection 01: rising edge detection 10: setting prohibited 11: both edges detection 0/1 0/1 0/1 chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 244 figure 6-52. example of register setti ngs for pulse width measurement (2/2) (e) 16-bit timer counter 00 (tm00) by reading tm00, the count value can be read. (f) 16-bit capture/compare register 000 (cr000) this register is used as a capture register. either th e ti000 or ti010 pin is selected as a capture trigger. when a specified edge of t he capture trigger is detec ted, the count value of tm00 is stored in cr000. (g) 16-bit capture/compare register 010 (cr010) this register is used as a capture register. the signal input to the ti 000 pin is used as a capture trigger. when the capture trigger is detected, the count value of tm00 is stored in cr010. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 245 figure 6-53. example of software proce ssing for pulse width measurement (1/2) (a) example of free-running timer mode ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture trigger input (ti000) capture register (cr010) capture interrupt (inttm010) capture trigger input (ti010) capture register (cr000) capture interrupt (inttm000) 01 d 00 d 00 d 01 d 01 d 02 d 02 d 03 d 03 d 04 d 04 d 10 d 10 d 11 d 11 d 12 d 12 d 13 d 13 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <2> <3> (b) example of clear & start mode entered by ti000 pin valid edge ffffh tm00 register 0000h operable bits (tmc003, tmc002) capture & count clear input (ti000) capture register (cr000) capture interrupt (inttm000) capture register (cr010) capture interrupt (inttm010) 10 d 0 l d 0 d 1 d 1 d 2 d 2 d 3 d 3 d 4 d 4 d 5 d 5 d 6 d 6 d 7 d 7 d 8 d 8 00 00 0000h 0000h <1> <2> <2> <2> <2> <2> <2> <2> <2> <3> <2> chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 246 figure 6-53. example of software proce ssing for pulse width measurement (2/2) <2> capture trigger input flow edge detection of ti000, ti010 pins calculated pulse width from capture value stores count value to cr000, cr010 registers generates capture interrupt note tmc003, tmc002 bits = 01 or 10 register initial setting prm00 register, crc00 register, port setting initial setting of these registers is performed before setting the tmc003 and tmc002 bits. starts count operation start <1> count operation start flow tmc003, tmc002 bits = 00 the counter is initialized and counting is stopped by clearing the tmc003 and tmc002 bits to 00. stop <3> count operation stop flow note the capture interrupt signal (in ttm000) is not generated when the reve rse-phase edge of the ti000 pin input is selected to the valid edge of cr000. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 247 6.4.9 external 24-bit event counter operation 16-bit timer/event counter 00 can be operat ed to function as an external 24-bit event counter, by connecting 16-bit timer/event counter 00 and 8-bit timer/ev ent counter 52 in cascade, and using the external event counter function of 8- bit timer/event counter 52. it operates as an external 24-bit event counter, by countin g the number of external cl ock pulses input to the ti52 pin via 8-bit timer counter 52 (tm52), and counting the si gnal which has been output upon a match between the tm52 count value and 8-bit timer compare register 52 (cr52 = ffh note ) via 16-bit timer counter 00 (tm00). when using 16-bit timer/event counter 00 as an external 24 -bit event counter, external event input enable can be controlled via 8-bit timer counter h2 output. the valid edge of the input to the ti 52 pin can be specified by timer clock se lection register 52 (tcl52) of 8-bit timer counter 52 (tm52). also, input enable for tm52 exter nal event input can be controlled via 8-bit timer counter h2 output, by setting bit 2 (isc2) of the input switch control register (isc) to ?1?. count operation using 8-bit timer 52 out put as the count clock is started, by setting bi ts 2, 1, and 0 (prm002, prm001, and prm000) of prescaler mode register 00 (prm00) of 16-bit timer/event counter 00 to ?1?, ?1?, and ?1? (tm52 output is selected as a count clock), and bits 3 and 2 (tmc003 and tmc002) of 16-bit timer mode control register 00 (tmc00) to ?1? and ?1? (count clear & st art mode entered upon a match between tm00 and cr000). tm00 is cleared to ?0? and an interrupt request signal (inttm000) is generated upon a match between the tm00 count value and 16-bit timer compare register 000 (cr000) value. subsequently, inttm000 is generated upon every match between the tm00 and cr000 values. note when operating 16-bit timer/event counter 00 as an ex ternal 24-bit event counter, the 8-bit timer compare register 52 (cr52) value must be set to ffh. also , the tm52 interrupt request signal (inttm52) must be masked (tmmk52 = 1). chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 248 figure 6-54. configuration diagram of external 24-bit event counter prm002 prm001 prm000 16-bit timer/event counter 00 count clock count clock 3 ti000 valid edge tm52 output inttm000 cr000 register chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 249 setting <1> each mode of tm00 and tm52 is set. (a) set tm00 as an interval timer. se lect tm52 output as the count clock. - tmc00: set to operation prohibited. (tmc00 = 00000000b) - crc00: set to operation as a compare register. (crc00 = 000000x0b, x = don?t care) - toc00: setting to00 pin output is proh ibited upon a match between cr000 and tm00 (toc00 = 00000000b) - prm00: tm52 output selected as a count clock. (prm00 = 00000111b) - cr000: set the compare value to ffffh. if the compare value is set to m, tm00 will only count up to m. - cr010: normally, cr010 is not used, however, a co mpare match interrupt (inttm010) is generated upon a match between the cr010 setting val ue and tm00 value. therefore, mask the interrupt request by using the interrupt mask flag (tmmk010). (b) set tm52 as an external event counter. - tcl52: edge selection of ti52 pin input falling edge of ti52 pin tcl52 = 00h rising edge of ti52 pin tcl52 = 01h - cr52: set the compare register value to ffh. - tmc52: count operation is stopped. (tmc52 = 00000000b) - tmif52: clear this register. caution when operating 16-bit timer/event counter 00 as an external 24-bi t event counter, inttm52 must be masked (tmmk52 = 1). also, the compare register 52 (c r52) value must be set to ffh. (c) set tmh2 to the input enable width adjust mode (pwm mode) for the ti52 pin. note - tmhmd2: count operation is stopped, the count clock is selected, the mode is set to input enable width adjust mode (pwm mode), the timer output level default value is set to high level, and timer output is set to enable (tmhmd2 = 0xxx1011b, x = set based on usage conditions). - cmp02: compare value (n) frequency setting - cmp12: compare value (m) duty setting remark 00h cmp12 (m) < cmp02 (n) ffh - isc2: set to isc2 = 1 (ti52 pin input enable controlled) note this setting is not required if input en able for the ti52 pin is not controlled. <2> tm00, tm52, and tmh2 count operatio n is started. timer operation must be started in accordance with the following procedure. (a) start tm00 counter operation by setti ng the tmc003 and tmc002 bits to 1 and 1. (b) start tm52 counter operation by setting tce52 to 1. (c) start tmh2 counter operation by setting tmhe2 to 1. note note this setting is not required if input en able for the ti52 pin is not controlled. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 250 <3> when the tm52 and cr52 (= ffh) values match, tm52 is cleared to 00, and the match signal causes tm000 to start counting up. then, when the tm000 and cr000 values match, tm00 is cleared to 0000h, and a match interrupt signal (inttm000) is generated. if input enable for the ti52 pin is controlled, external ev ent count values within the input enable periods for the ti52 pin can be measured, by reading tm52, the tm00 count value, and tmif52 via interrupt servicing by the tmh2 interrupt request signal (inttmh2). figure 6-55. operation timing of external 24-bit event counter tmh2 output signal clear tm52/tm00 counter read tm52/tm00 count value ti52 tm52 tm00 inttm52 inttmh2 ti52 & toh2 41h 1234h 0000h 0001h 0000h 0001h 0002h fffeh ffffh 42h 43h ffh 00h 01h ffh 00h 01h ffh 00h 01h ffh 00h 01h ffh 00h 01h 00h 01h 02h 03h 04h 00h 01h clear tm52/tm00 counter read tm52/tm00 count value chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 251 figure 6-56. operation flowchart of external 24-bit event counter set tmh2 to pwm mode set in this order perform these steps during low level output of toh2 these operations must be restarted since the counter is cleared when timer operation is stopped. note note set tm52 to external event counter set tm00 to interval timer starts tm00 count operation read tm00 counter value read tm52 counter value clear tm00 counter value clear tm52 counter value starts tm00 count operation starts tm52 count operation starts tm52 count operation starts tmh2 count operation generates inttmh2? tmc003 = 0, tmc002 = 0 tce52 = 0 note this setting is not required if input en able for the ti52 pin is not controlled. 6.4.10 cautions for external 24-bit event counter (1) 8-bit timer counter h2 output signal the output level control (default value) of 8-bit timer h2 which is used to control input enable for the ti52 pin, must be set to high level (tolev2 = 1). consequently, an interrupt request signal (inttmh2) is generated while the input enable signal to the ti52 pi n is disabled (tmh2 output: low level), and the tm52 and tm00 count values (= external event count value in input enable period) can be read via servicing of this interrupt. note with caution that the input enable signal to the ti52 pin is at high level (enable status) until the tmh2 and cmp02 register values match, after 8-bit timer h2 oper ation has been enabled (tmhe2 = 1) via this setting (tolev2 = 1). chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 252 (2) cautions for input enable control for ti52 pin the input enable control signal (tmh2 output signal) for th e ti52 pin is synchronized by the ti52 pin input clock, as described in figure 6-54 configuration diagram of external 24-bit event counter and figure 6-55 operation timing of extern al 24-bit event counter . thus, when the counter is operated as an external event counter, an error up to one count may be caused. (3) cautions for 16-bit timer/event counter 00 c ount up during external 24-b it event counter operation 16-bit timer/event counter 00 has an internal synchronizati on circuit to eliminate noise when starting operation, and the first clock immediately afte r operation start is not counted. when using the counter as a 24-bit counter, by setting 16- bit timer/event counter 00 an d 8-bit timer/event counter 52 as the higher and lower timer and connecting them in ca scade, the interrupt request flag of 8-bit timer/event counter 52 which is the lower timer must be checked as de scribed below, in order to accurately read the 24-bit count values. - if tmif52 = 1 when tm52 and tm00 are read: the actual tm00 count value is ?read value of tm00 + 1?. - if tmif52 = 0 when tm52 and tm00 are read: the read value is the correct value. this phenomenon of 16-bit timer/event counter 00 occurs onl y when operation is started. a count delay will not occur when 16-bit timer/event counter 00 overflows and t he count is restarted from 0000h, since synchronization has already been implemented. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 253 6.5 special use of tm00 6.5.1 rewriting cr010 during tm00 operation in principle, rewriting cr000 and cr01 0 of the 78k0/lf3 when th ey are used as compare registers is prohibited while tm00 is operating (tmc003 and tmc002 = other than 00). however, the value of cr010 can be changed, even while tm00 is operating, using the following procedure if cr010 is used for ppg output and the duty factor is changed (when setting cr010 to a smaller or larger value than the current value, rewrite the cr010 value immediately after a match between cr010 and tm00 or between cr000 and tm00. when cr010 is rewritten immediately before a match between cr010 and tm00 or between cr000 and tm00, an unexpected operation may be performed). procedure for changing value of cr010 <1> disable interrupt inttm010 (tmmk010 = 1). <2> disable reversal of the timer output when th e value of tm00 matches that of cr010 (toc004 = 0). <3> change the value of cr010. <4> wait for one cycle of the count clock of tm00. <5> enable reversal of the timer output when the value of tm00 matches that of cr010 (toc004 = 1). <6> clear the interrupt flag of inttm010 (tmif010 = 0) to 0. <7> enable interrupt inttm010 (tmmk010 = 0). remark for tmif010 and tmmk010, see chapter 21 interrupt functions . 6.5.2 setting lvs00 and lvr00 (1) usage of lvs00 and lvr00 lvs00 and lvr00 are used to set the default value of the to00 output and to inve rt the timer output without enabling the timer operation (tmc003 and tmc002 = 00). clear lvs00 and lvr00 to 00 (default value: low- level output) when software control is unnecessary. lvs00 lvr00 timer output status 0 0 not changed (low-level output) 0 1 cleared (low-level output) 1 0 set (high-level output) 1 1 setting prohibited chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 254 (2) setting lvs00 and lvr00 set lvs00 and lvr00 using the following procedure. figure 6-57. example of flow for setting lvs00 and lvr00 bits setting toc00.ospe00, toc004, toc001 bits setting toc00.toe00 bit setting toc00.lvs00, lvr00 bits setting tmc00.tmc003, tmc002 bits <3> enabling timer operation <2> setting of timer output f/f <1> setting of timer output operation caution be sure to set lvs00 and lvr00 follo wing steps <1>, <2>, and <3> above. step <2> can be performed after <1> and before <3>. figure 6-58. timing example of lvr00 and lvs00 toc00.lvs00 bit toc00.lvr00 bit operable bits (tmc003, tmc002) to00 output inttm000 signal <1> 00 <2> <1> <3> <4> <4> <4> 01, 10, or 11 <1> the to00 output goes high when lvs00 and lvr00 = 10. <2> the to00 output goes low when lvs00 and lvr00 = 01 (the pin output remains unchanged from the high level even if lvs00 and lvr00 are cleared to 00). <3> the timer starts operating when tmc003 and tmc002 are set to 01, 10, or 11. because lvs00 and lvr00 were set to 10 before the operat ion was started, the to 00 output starts from the high level. after the timer starts operating, setting lvs00 and lvr 00 is prohibited until tmc003 and tmc002 = 00 (disabling the timer operation). <4> the to00 output level is inverted each time an interrupt signal (inttm000) is generated. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 255 6.6 cautions for 16-bit timer/event counter 00 (1) restrictions for each channel of 16-bit timer/event counter 00 table 6-3 shows the restrictions for each channel. table 6-3. restrictions for each ch annel of 16-bit timer/event counter 00 operation restriction as interval timer as square wave output as external event counter ? as clear & start mode entered by ti000 pin valid edge input using timer output (to00) is prohibited when det ection of the valid edge of the ti010 pin is used. (toc00 = 00h) as free-running timer ? as ppg output 0000h cr010 < cr000 ffffh as one-shot pulse output setting the same value to cr000 and cr010 is prohibited. as pulse width measurement using timer output (to00) is prohibited (toc00 = 00h) (2) timer start errors an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because counting tm00 is start ed asynchronously to the count pulse. figure 6-59. start timing of tm00 count 0000h timer start 0001h 0002h 0003h 0004h count pulse tm00 count value (3) setting of cr000 and cr010 (clear & start m ode entered upon a match between tm00 and cr000) set a value other than 0000h to cr000 and cr010 (tm00 c annot count one pulse when it is used as an external event counter). chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 256 (4) timing of holding data by capture register (a) when the valid edge is input to t he ti000/ti010 pin and the reverse phase of the ti000 pin is detected while cr000/cr010 is read, cr010 performs a capture operation but the read value of cr000/cr010 is not guaranteed. at this time, an interrupt signal (inttm 000/inttm010) is generated wh en the valid edge of the ti000/ti010 pin is detected (t he interrupt signal is not generated when the reverse-phase edge of the ti000 pin is detected). when the count value is captured because the valid edge of the ti000/ti010 pi n was detected, read the value of cr000/cr010 after inttm000/inttm010 is generated. figure 6-60. timing of holding data by capture register n n + 1 n + 2 x n + 1 m m + 1 m + 2 count pulse tm00 count value edge input inttm010 value captured to cr010 capture read signal capture operation is performed but read value is not guaranteed. capture operation (b) the values of cr000 and cr010 are not guarant eed after 16-bit timer/event counter 00 stops. (5) setting valid edge set the valid edge of the ti000 pin while the timer operation is stopped (tmc003 and tmc002 = 00). set the valid edge by using es000 and es001. (6) re-triggering one-shot pulse make sure that the trigger is not generated while an active level is being output in t he one-shot pulse output mode. be sure to input the next trigger afte r the current active level is output. chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 257 (7) operation of ovf00 flag (a) setting ovf00 flag (1) the ovf00 flag is set to 1 in the following case, as well as when tm00 overflows. select the clear & start mode entered upon a match between tm00 and cr000. set cr000 to ffffh. when tm00 matches cr000 and tm00 is cleared from ffffh to 0000h figure 6-61. operation timing of ovf00 flag fffeh ffffh ffffh 0000h 0001h count pulse tm00 inttm000 ovf00 cr000 (b) clearing ovf00 flag even if the ovf00 flag is cleared to 0 after tm00 overflows and before the next count clock is counted (before the value of tm00 becomes 0001h), it is set to 1 again and clearing is invalid. (8) one-shot pulse output one-shot pulse output operates correct ly in the free-running timer mode or the clear & start mode entered by the ti000 pin valid edge. the one-shot pulse cannot be output in the clea r & start mode entered upon a match between tm00 and cr000. chapter 6 16-bit timer/event counter 00 user?s manual u18329ej4v0ud 258 (9) capture operation (a) when valid edge of ti 000 is specified as count clock when the valid edge of ti000 is specified as the count cl ock, the capture register for which ti000 is specified as a trigger does not operate correctly. (b) pulse width to accurately capture value by signals input to ti010 and ti000 pins to accurately capture the count value, the pulse input to the ti000 and ti010 pins as a capture trigger must be wider than two count clocks selected by prm00 (see figure 6-7 ). (c) generation of interrupt signal the capture operation is per formed at the falling edge of the count clock but the in terrupt signals (inttm000 and inttm010) are generated at the risi ng edge of the next count clock (see figure 6-7 ). (d) note when crc001 (bit 1 of capture/compa re control register 00 (crc00)) is set to 1 when the count value of the tm00 regist er is captured to the cr000 regi ster in the phase reverse to the signal input to the ti000 pin, the interrupt signal (i nttm000) is not generated after the count value is captured. if the valid edge is det ected on the ti010 pin during this oper ation, the captur e operation is not performed but the inttm000 signal is generated as an ex ternal interrupt signal. mask the inttm000 signal when the external interrupt is not used. (10) edge detection (a) specifying valid edge after reset if the operation of the 16-bit timer/ev ent counter 00 is enabled after reset and while the ti000 or ti010 pin is at high level and when the rising edge or both the edges are specified as the valid edge of the ti000 or ti010 pin, then the high level of the ti000 or ti010 pin is detected as the rising edge. note this when the ti000 or ti010 pin is pulled up. however, t he rising edge is not detected when the operation is once stopped and then enabled again. (b) sampling clock for eliminating noise the sampling clock for eliminating noise differs depend ing on whether the valid edge of ti000 is used as the count clock or capture trigger. in the fo rmer case, the sampling clock is fixed to f prs . in the latter, the count clock selected by prm00 is used for sampling. when the signal input to the ti000 pin is sampled and the valid level is detected two times in a row, the valid edge is detected. therefore, noise having a short pulse width can be eliminated (see figure 6-7 ). (11) timer operation the signal input to the ti000/ti010 pin is not acknow ledged while the timer is stopped, regardless of the operation mode of the cpu. remark f prs : peripheral hardware clock frequency chapter 6 16-bit timer/event counters 00 user?s manual u18329ej4v0ud 259 (12) reading of 16-bit timer counter 00 (tm00) tm00 can be read without stopping the actual counter, bec ause the count values captured to the buffer are fixed when it is read. the buffer, however , may not be updated when it is read i mmediately before the counter counts up, because the buffer is updated at the timing the counter counts up. figure 6-62. 16-bit timer count er 00 (tm00) read timing count clock tm00 count value 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 0034h 0035h 0037h 0038h 003bh read buffer read signal user?s manual u18329ej4v0ud 260 chapter 7 8-bit timer/event counters 50, 51, and 52 7.1 functions of 8-bit timer/ event counters 50, 51, and 52 8-bit timer/event counters 50 and 51 have the following functions. ? interval timer ? external event counter note 1 ? square-wave output note 2 ? pwm output note 2 notes 1. tm52 and tm00 can be connected in cascade to be used as an external 24-bit event counter. also, the external event input of tm52 can be input enable-controlled via tmh2. for details, see chapter 6 16-bit timer/event counter 00 . 2. tm50 and tm51 only. 7.2 configuration of 8-bit ti mer/event counters 50, 51, and 52 8-bit timer/event counters 50, 51, and 52 include the following hardware. table 7-1. configuration of 8-bit timer/event counters 50, 51, and 52 item configuration timer register 8-bit timer counter 5n (tm5n) register 8-bit timer compare register 5n (cr5n) timer input ti5n timer output to50, to51 control registers timer clock selection register 5n (tcl5n) 8-bit timer mode control register 5n (tmc5n) input switch control register (isc) port mode register 3 (pm3) or port mode register 4 (pm4) port register 3 (p3) or port register 4 (p4) remark n = 0 to 2 figures 7-1 to 7-3 show the block diagrams of 8-bit timer/event counters 50, 51, and 52. chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 261 figure 7-1. block diagram of 8-bit timer/event counter 50 internal bus 8-bit timer compare register 50 (cr50) ti50/to50/p44/kr4 f prs /2 13 f prs f prs /2 match mask circuit ovf 3 clear tcl502 tcl501 tcl500 timer clock selection register 50 (tcl50) internal bus tce50 tmc506 lvs50 lvr50 tmc501 toe50 invert level 8-bit timer mode control register 50 (tmc50) s r s q r inv selector to tmh0 to uart0 to uart6 inttm50 to50/ti50/ p44/kr4 note 1 note 2 selector 8-bit timer counter 50 (tm50) selector output latch (p44) pm44 f prs /2 2 f prs /2 8 f prs /2 6 to50 output figure 7-2. block diagram of 8-bit timer/event counter 51 internal bus 8-bit timer compare register 51 (cr51) ti51/to51/ p43/kr3 match mask circuit ovf 3 clear tcl512 tcl511 tcl510 timer clock selection register 51 (tcl51) internal bus tce51 tmc516 lvs51 lvr51 tmc511 toe51 invert level 8-bit timer mode control register 51 (tmc51) s r s q r inv selector inttm51 to51/ti51/ p43/kr3 note 1 note 2 selector 8-bit timer counter 51 (tm51) selector output latch (p43) pm43 8-bit timer h1 output f prs f prs /2 4 f prs /2 8 f prs /2 f prs /2 6 to51 output notes 1. timer output f/f 2. pwm output f/f chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 262 figure 7-3. block diagram of 8-bit timer/event counter 52 3 inttm52 ti52/ti010/to00/ rtc1hz/intp1/p34 to tm00 tmh2 output tce52 tcl522 tcl521 tcl520 clear 8-bit timer compare register 52 (cr52) timer clock selection register 52 (tcl52) 8-bit timer counter 52 (tm52) selector selector internal bus internal bus 8-bit timer mode control register 52 (tmc52) match input switch control register (isc) isc2 f prs f prs /2 4 f prs /2 6 f prs /2 12 f prs /2 f prs /2 8 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 263 (1) 8-bit timer counter 5n (tm5n) tm5n is an 8-bit register that count s the count pulses and is read-only. the counter is incremented in synchronization with the rising edge of the count clock. figure 7-4. format of 8-bit timer counter 5n (tm5n) symbol tm5n (n = 0-2) address: ff16h (tm50), ff6fh (tm51), ff51h (tm52) after reset: 00h r in the following situations, the count value is cleared to 00h. <1> reset signal generation <2> when tce5n is cleared <3> when tm5n and cr5n match in the mode in which clear & start occurs upon a match of the tm5n and cr5n. (2) 8-bit timer compare register 5n (cr5n) cr5n can be read and written by an 8-bi t memory manipulation instruction. except in pwm mode, the value set in cr5n is constantly compared with the 8-bit timer counter 5n (tm5n) count value, and an interrupt request (in ttm5n) is generated if they match. in the pwm mode, the to5n output becomes inactive when the values of tm5n and cr5n match, but no interrupt is generated. the value of cr5n can be set within 00h to ffh. reset signal generation sets cr5n to 00h. figure 7-5. format of 8-bit time r compare register 5n (cr5n) symbol cr5n (n = 0-2) address: ff17h (cr50), ff41h (cr51), ff59h (cr52) after reset: 00h r/w cautions 1. in the mode in which clear & start oc curs on a match of tm5n and cr5n (tmc5n6 = 0), do not write other values to cr5n during operation. 2. in pwm mode, make the cr5n rewrite peri od 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0 to 2 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 264 7.3 registers controlling 8-bit ti mer/event counters 50, 51, and 52 the following five registers are used to contro l 8-bit timer/event counters 50, 51, and 52. ? timer clock selection register 5n (tcl5n) ? 8-bit timer mode control register 5n (tmc5n) ? input switch control register (isc) ? port mode register 3 (pm3) or port mode register 4 (pm4) ? port register 3 (p3) or port register 4 (p4) (1) timer clock selecti on register 5n (tcl5n) this register sets the count clock of 8-bit timer/ev ent counter 5n and the valid edge of the ti5n pin input. tcl5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets tcl5n to 00h. remark n = 0 to 2 figure 7-6. format of timer clo ck selection register 50 (tcl50) address: ff6ah after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl50 0 0 0 0 0 tcl502 tcl501 tcl500 count clock selection note 1 tcl502 tcl501 tcl500 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz 0 0 0 ti50 pin falling edge 0 0 1 ti50 pin rising edge 0 1 0 f prs note 2 2 mhz 5 mhz 10 mhz 0 1 1 f prs /2 1 mhz 2.5 mhz 5 mhz 1 0 0 f prs /2 2 500 khz 1.25 mhz 2.5 mhz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 1 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 1 1 1 f prs /2 13 0.24 khz 0.61 khz 1.22 khz notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tcl502, tcl501, tcl500 = 0, 1, 0 (count clock: f prs ) is prohibited. cautions 1. when rewriting tcl50 to othe r data, stop the timer operation beforehand. 2. be sure to clea r bits 3 to 7 to 0. remark f prs : peripheral hardware clock frequency chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 265 figure 7-7. format of timer clo ck selection register 51 (tcl51) address: ff8ch after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl51 0 0 0 0 0 tcl512 tcl511 tcl510 count clock selection note 1 tcl512 tcl511 tcl510 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz 0 0 0 ti51 pin falling edge 0 0 1 ti51 pin rising edge 0 1 0 f prs note 2 2 mhz 5 mhz 10 mhz 0 1 1 f prs /2 1 mhz 2.5 mhz 5 mhz 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 1 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 1 1 1 timer h1 output signal notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tcl512, tcl511, tcl510 = 0, 1, 0 (count clock: f prs ) is prohibited. cautions 1. when rewriting tcl51 to othe r data, stop the timer operation beforehand. 2. be sure to clea r bits 3 to 7 to 0. chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 266 figure 7-8. format of timer clo ck selection register 52 (tcl52) address: ff5bh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 tcl52 0 0 0 0 0 tcl522 tcl521 tcl520 count clock selection note 1 tcl522 tcl521 tcl520 f prs = 2 mhz f prs = 5 mhz f prs = 10 mhz 0 0 0 falling edge of clock selected by isc2 0 0 1 rising edge of clock selected by isc2 0 1 0 f prs note 2 2 mhz 5 mhz 10 mhz 0 1 1 f prs /2 1 mhz 2.5 mhz 5 mhz 1 0 0 f prs /2 4 125 khz 312.5 khz 625 khz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 156.25 khz 1 1 0 f prs /2 8 7.81 khz 19.53 khz 39.06 khz 1 1 1 f prs /2 12 0.49 khz 1.22 khz 2.44 khz notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tcl522, tcl521, tcl520 = 0, 1, 0 (count clock: f prs ) is prohibited. cautions 1. when rewriting tcl52 to othe r data, stop the timer operation beforehand. 2. be sure to clea r bits 3 to 7 to 0. remark f prs : peripheral hardware clock frequency chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 267 (2) 8-bit timer mode control register 5n (tmc5n) tmc5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (tm5n) count operation control <2> 8-bit timer counter 5n (tm5n) operating mode selection note <3> timer output f/f (flip flop) status setting note <4> active level selection in timer f/f control or pwm (free-running) mode note <5> timer output control note tmc5n can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. note tm50 and tm51 only. remark n = 0 to 2 figure 7-9. format of 8-bit timer mode control register 50 (tmc50) address: ff6bh after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc50 tce50 tmc506 0 0 lvs50 lvr50 tmc501 toe50 tce50 tm50 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc506 tm50 operating mode selection 0 mode in which clear & start occurs on a match between tm50 and cr50 1 pwm (free-running) mode lvs50 lvr50 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default value of to50 output: low level) 1 0 timer output f/f set (1) (defaul t value of to50 output: high level) 1 1 setting prohibited in other modes (tmc506 = 0) in pwm mode (tmc506 = 1) tmc501 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe50 timer output control 0 output disabled (to50 output is low level) 1 output enabled note bits 2 and 3 are write-only. ( cautions and remarks are listed on the next page.) chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 268 figure 7-10. format of 8-bit timer mode control register 51 (tmc51) address: ff43h after reset: 00h r/w note symbol <7> 6 5 4 <3> <2> 1 <0> tmc51 tce51 tmc516 0 0 lvs51 lvr51 tmc511 toe51 tce51 tm51 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start tmc516 tm51 operating mode selection 0 mode in which clear & start occurs on a match between tm51 and cr51 1 pwm (free-running) mode lvs51 lvr51 timer output f/f status setting 0 0 no change 0 1 timer output f/f clear (0) (default value of to51 output: low) 1 0 timer output f/f set (1) (default value of to51 output: high) 1 1 setting prohibited in other modes (tmc516 = 0) in pwm mode (tmc516 = 1) tmc511 timer f/f control active level selection 0 inversion operation disabled active-high 1 inversion operation enabled active-low toe51 timer output control 0 output disabled (to51 output is low level) 1 output enabled note bits 2 and 3 are write-only. cautions 1. the settings of lvs5n and lv r5n are valid in other than pwm mode. 2. perform <1> to <4> below in the following order, not at the same time. <1> set tmc5n1, tmc5n6 : operation mode setting <2> set toe5n to enable output: timer output enable <3> set lvs5n, lvr5n (see caution 1): timer f/f setting <4> set tce5n 3. when tce5n = 1, setting the ot her bits of tmc5n is prohibited. 4. the actual to50/ti50/p44/kr4 and to51/ti51/ p43/kr3 pin outputs ar e determined depending on pm44 and p44, and pm43 and p43, besides to5n output. remarks 1. in pwm mode, pwm output is made inactive by clearing tce5n to 0. 2. if lvs5n and lvr5n are read, the value is 0. 3. the values of the tmc5n6, lvs5n, lvr5n, tmc 5n1, and toe5n bits are re flected at the to5n pin regardless of the value of tce5n. 4. n = 0, 1 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 269 figure 7-11. format of 8-bit timer mode control register 52 (tmc52) address: ff5ch after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 tmc52 tce52 0 0 0 0 0 0 0 tce52 tm52 count operation control 0 after clearing to 0, count operation disabled (counter stopped) 1 count operation start caution be sure to clea r bits 0 to 6 to 0. chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 270 (3) input switch control register (isc) by setting isc2 to 1, the ti52 input signal can be controlled via the toh2 output signal. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 7-12. format of input s witch control register (isc) address: ff4fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 isc 0 0 isc5 isc4 isc3 isc2 isc1 isc0 isc5 isc4 txd6, rxd6 input source selection 0 0 txd6:p112, rxd6: p113 0 1 txd6:p16, rxd6: p15 other than above setting prohibited isc3 rxd6/p113 input enabled/disabled 0 r x d6/p113 input disabled 1 r x d6/p113 input enabled isc2 ti52 input source control 0 no enable control of ti52 input (p34) 1 enable controlled of ti52 input (p34) note 1 isc1 ti000 input source selection 0 ti000 (p33) 1 rxd6 (p15 or p113 note 2 ) isc0 intp0 input source selection 0 intp0 (p120) 1 r x d6 (p15 or p113 note 2 ) notes 1. ti52 input is controlled by toh2 output signal. 2. this is selected by isc5 and isc4. chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 271 (4) port mode registers 3 and 4 (pm3, pm4) these registers set port 3 and 4 input/output in 1-bit units. when using the p44/to50/ti 50/kr4 and p43/to51/ti51/ kr3 pins for timer output, clear pm44 and pm43 and the output latches of p44 and p43 to 0. when using the p44/to50/ti50/kr4, p43/to51/ti51/kr3, and p34/ti52/t i010/to00/rtc1hz/intp1 pins for timer input, set pm44, pm43, and pm34 to 1. the output latches of p44, pm43, and pm 34 at this time may be 0 or 1. pm3 and pm4 can be set by a 1-bit or 8- bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 7-13. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 pm3n p1n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) figure 7-14. format of port mode register 4 (pm4) address: ff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pm4n p4n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 272 7.4 operations of 8-bit time r/event counters 50, 51, and 52 7.4.1 operation as interval timer 8-bit timer/event counter 5n operates as an interval time r that generates interrupt req uests repeatedly at intervals of the count value preset to 8-bi t timer compare register 5n (cr5n). when the count value of 8-bit timer counter 5n (tm5n) ma tches the value set to cr5n, counting continues with the tm5n value cleared to 0 and an interrupt request signal (inttm5n) is generated. the count clock of tm5n can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). setting <1> set the registers. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, se lect the mode in which clear & start occurs on a match of tm5n and cr5n. (tmc5n = 0000 0b = don?t care) <2> after tce5n = 1 is set, the count operation starts. <3> if the values of tm5n and cr5n match, intt m5n is generated (tm5n is cleared to 00h). <4> inttm5n is generated repeatedly at the same interval. set tce5n to 0 to stop the count operation. caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 21 interrupt functions . 2. n = 0 to 2 figure 7-15. interval ti mer operation timing (1/2) (a) basic operation t count clock tm5n count value cr5n tce5n inttm5n count start clear clear 00h 01h n 00h 01h n 00h 01h n n n n n interrupt acknowledged interrupt acknowledged interval time interval time remark interval time = (n + 1) t n = 01h to ffh n = 0 to 2 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 273 figure 7-15. interval ti mer operation timing (2/2) (b) when cr5n = 00h t interval time count clock tm5n cr5n tce5n inttm5n 00h 00h 00h 00h 00h (c) when cr5n = ffh t count clock tm5n cr5n tce5n inttm5n 01h feh ffh 00h feh ffh 00h ffh ffh ffh interval time interrupt acknowledged interrupt acknowledged remark n = 0 to 2 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 274 7.4.2 operation as external event counter the external event counter c ounts the number of external clock pulses to be input to the ti5n pin by 8-bit timer counter 5n (tm5n). tm5n is incremented each time the valid edge specified by timer clock selection regist er 5n (tcl5n) is input. either the rising or falling edge can be selected. when the tm5n count value matches the value of 8-bit ti mer compare register 5n (cr5n), tm5n is cleared to 0 and an interrupt request signal (inttm5n) is generated. whenever the tm5n value matches the va lue of cr5n, inttm5n is generated. setting <1> set each register. ? set the port mode register (pm44, pm43, or pm34) note to 1. ? tcl5n: select ti5n pin input edge. ti5n pin falling edge tcl5n = 00h ti5n pin rising edge tcl5n = 01h ? cr5n: compare value ? tmc5n: stop the count operation, select the mode in which clear & start occurs on match of tm5n and cr5n, disable the timer f/f inversion operation, disable timer output. (tmc5n = 0000 00b = don?t care) <2> when tce5n = 1 is set, the number of pu lses input from the ti5n pin is counted. <3> when the values of tm5n and cr5n match, inttm5n is generated (tm5n is cleared to 00h). <4> after these settings, inttm5n is generated each time the values of tm5n and cr5n match. note 8-bit timer/event counter 50: pm44 8-bit timer/event counter 51: pm43 8-bit timer/event counter 52: pm34 remark for how to enable the inttm5n signal interrupt, see chapter 21 interrupt functions . figure 7-16. external event counter oper ation timing (with rising edge specified) ti5n tm5n count value cr5n inttm5n 00h 01h 02h 03h 04h 05h n ? 1 n 00h 01h 02h 03h n count start remark 1. 8-bit timer/event counter 52 (tm52) can be us ed as an external 24-bit event counter, by connecting it with 16-bit timer/ event counter (tm00) in cascade. also, input enable of tm52 can be controlled via tmh2. for details, see 6.4.9 external 24-bit event counter operation . 2. n = 00h to ffh, n = 0 to 2 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 275 7.4.3 square-wave output operation a square wave with any selected frequency is output at in tervals determined by the value preset to 8-bit timer compare register 5n (cr5n). the to5n pin output status is inverted at intervals determined by the count value preset to cr5n by setting bit 0 (toe5n) of 8-bit timer mode control r egister 5n (tmc5n) to 1. this enables a square wave with any selected frequency to be output (duty = 50%). setting <1> set each register. ? clear the port output latch (p44 or p43) note and port mode register (pm44 or pm43) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operat ion, select the mode in which clear & start occurs on a match of tm5n and cr5n. lvs5n lvr5n timer output f/f status setting 1 0 timer output f/f clear (0) (default value of to5n output: low level) 0 1 timer output f/f set (1) (defaul t value of to5n output: high level) timer output enabled (tmc5n = 00001011b or 00000111b) <2> after tce5n = 1 is set, the count operation starts. <3> the timer output f/f is inverted by a match of tm5n and cr5n. after inttm5n is generated, tm5n is cleared to 00h. <4> after these settings, the timer output f/f is inverted at the same interval and a square wave is output from to5n. the frequency is as follows. ? frequency = 1/2t (n + 1) (n: 00h to ffh) note 8-bit timer/event counter 50: p44, pm44 8-bit timer/event counter 51: p43, pm43 caution do not write other values to cr5n during operation. remarks 1. for how to enable the inttm5n signal interrupt, see chapter 21 interrupt functions . 2. n = 0, 1 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 276 figure 7-17. square-wave output operation timing count clock tm5n count value 00h 01h 02h n ? 1n n 00h n ? 1 n 00h 01h 02h cr5n to5n note t count start note the initial value of to5n output c an be set by bits 2 and 3 (lvr5n, lvs5n) of 8-bit timer mode control register 5n (tmc5n). 7.4.4 pwm output operation 8-bit timer/event counter 5n operates as a pwm output when bit 6 (tmc5n6) of 8-bit timer mode control register 5n (tmc5n) is set to 1. the duty pulse determined by the value set to 8-bit time r compare register 5n (cr5n) is output from to5n. set the active level width of the pwm pulse to cr5n; the active level can be selected with bit 1 (tmc5n1) of tmc5n. the count clock can be selected with bits 0 to 2 (tcl5n0 to tcl5n2) of timer clock selection register 5n (tcl5n). pwm output can be enabled/disabled with bit 0 (toe5n) of tmc5n. caution in pwm mode, make the cr5n rewrite period 3 count clocks of the count clock (clock selected by tcl5n) or more. remark n = 0, 1 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 277 (1) pwm output basic operation setting <1> set each register. ? clear the port output latch (p44 or p43) note and port mode register (pm44 or pm43) note to 0. ? tcl5n: select the count clock. ? cr5n: compare value ? tmc5n: stop the count operation, select pwm mode. the timer output f/f is not changed. tmc5n1 active level selection 0 active-high 1 active-low timer output enabled (tmc5n = 01000001b or 01000011b) <2> the count operation starts when tce5n = 1. clear tce5n to 0 to stop the count operation. note 8-bit timer/event counter 50: p44, pm43 8-bit timer/event counter 51: p43, pm43 pwm output operation <1> pwm output (output from to5n) outputs an inactive level until an overflow occurs. <2> when an overflow occurs, the active level is output. the active level is output until cr5n matches the count value of 8-bit timer counter 5n (tm5n). <3> after the cr5n matches the count value, the inacti ve level is output until an overflow occurs again. <4> operations <2> and <3> are repe ated until the count operation stops. <5> when the count operation is stopped with tce5n = 0, pwm output becomes inactive. for details of timing, see figures 7-18 and 7-19 . the cycle, active-level width, and duty are as follows. ? cycle = 2 8 t ? active-level width = nt ? duty = n/2 8 (n = 00h to ffh) remark n = 0, 1 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 278 figure 7-18. pwm output operation timing (a) basic operation (active level = h) count clock tm5n cr5n tce5n inttm5n to5n 00h 01h ffh 00h 01h 02h n n + 1 ffh 00h 01h 02h m 00h n <2> active level <1> inactive level <3> inactive level <5> inactive level t <2> active level (b) cr5n = 00h count clock tm5n cr5n tce5n inttm5n 01h 00h ffh 00h 01h 02h 00h ffh 00h 01h 02h m 00h to5n l (inactive level) t (c) cr5n = ffh tm5n cr5n tce5n inttm5n to5n 01h 00h ffh 00h 01h 02h ffh <1> inactive level <2> active level ffh 00h 01h 02h m 00h <3> inactive level <2> active level <5> inactive level t remarks 1. <1> to <3> and <5> in figure 7-18 (a) correspond to <1> to <3> and <5> in pwm output operation in 7.4.4 (1) pwm output basic operation . 2. n = 0, 1 chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 279 (2) operation with cr5n changed figure 7-19. timing of operation with cr5n changed (a) cr5n value is changed from n to m before clock rising edge of ffh value is transferred to cr5n at overflow immediately after change. count clock tm5n cr5n tce5n inttm5n to5n <1> cr5n change (n m) n n + 1 n + 2 ffh 00h 01h m m + 1 m + 2 ffh 00h 01h 02h m m + 1 m + 2 n 02h m h <2> t (b) cr5n value is changed from n to m after clock rising edge of ffh value is transferred to cr5n at second overflow. count clock tm5n cr5n tce5n inttm5n to5n n n + 1 n + 2 ffh 00h 01h n n + 1 n + 2 ffh 00h 01h 02h n 02h n h m m m + 1 m + 2 <1> cr5n change (n m) <2> t caution when reading from cr5n betw een <1> and <2> in figure 7-19, the value read differs from the actual value (read value: m, actual value of cr5n: n). 7.5 cautions for 8-bit time r/event counters 50, 51, and 52 (1) timer start error an error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start. this is because 8-bit timer counters 50, 51, and 52 (tm 50, tm51, and tm52) are started asynchronously to the count clock. chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 280 figure 7-20. 8-bit timer counter 5n start timing count clock tm5n count value 00h 01h 02h 03h 04h timer start remark n = 0 to 2 (2) cautions for 16-bit timer/event counter 00 count up during external 24-bit event counter operation 16-bit timer/event counter 00 has an internal synchronizati on circuit to eliminate noise when starting operation, and the first clock immediately afte r operation start is not counted. when using the counter as a 24-bit counter, by setting 16- bit timer/event counter 00 an d 8-bit timer/event counter 52 as the higher and lower timer and connecting them in ca scade, the interrupt request flag of 8-bit timer/event counter 52 which is the lower timer must be checked as de scribed below, in order to accurately read the 24-bit count values. - if tmif52 = 1 when tm52 and tm00 are read: the actual tm00 count value is ?read value of tm00 + 1?. - if tmif52 = 0 when tm52 and tm00 are read: the read value is the correct value. this phenomenon of 16-bit timer/event counter 00 occurs onl y when operation is started. a count delay will not occur when 16-bit timer/event counter 00 overflows and t he count is restarted from 0000h, since synchronization has already been implemented. chapter 7 8-bit timer/event counters 50, 51, and 52 user?s manual u18329ej4v0ud 281 (3) reading of 8-bit timer counter 5n (tm5n) tm5n can be read without stopping the actual counter, bec ause the count values captured to the buffer are fixed when it is read. the buffer, however , may not be updated when it is read i mmediately before the counter counts up, because the buffer is updated at the timing the counter counts up. figure 7-21. 8-bit timer counter 5n (tm5n) read timing 34h 35h 36h 37h 38h 39h 3ah 3bh 34h 35h 37h 38h 3bh count clock tm5n count value read buffer read signal remark n = 0 to 2 user?s manual u18329ej4v0ud 282 chapter 8 8-bit timers h0, h1, and h2 8.1 functions of 8-bit timers h0, h1, and h2 8-bit timers h0, h1, and h2 have the following functions. ? interval timer ? square-wave output note 1 ? pwm output note 2 ? carrier generator (8-bit timer h1 only) note 3 notes 1. tmh0 and tmh1 only. 2. however, toh0 and toh1 only for tohn 3. tmh1 only. tm51 and tmh1 can be used in combination as a carrier generator mode. 8.2 configuration of 8-bi t timers h0, h1, and h2 8-bit timers h0, h1, and h2 include the following hardware. table 8-1. configuration of 8-bit timers h0, h1, and h2 item configuration timer register 8-bit timer counter hn registers 8-bit timer h compare register 0n (cmp0n) 8-bit timer h compare register 1n (cmp1n) timer output tohn note 1 , output controller control registers 8-bit timer h mode register n (tmhmdn) 8-bit timer h carrier control register 1 (tmcyc1) note 2 port mode register 3 (pm3) port register 3 (p3) notes 1. tmh2 does not have an output pin (toh2). it can only be used as an internal interrupt (inttmh2) or an external event input enable signal for the ti52 pin. 2. 8-bit timer h1 only remark n = 0-2, however, toh0 and toh1 only for tohn figures 8-1 and 8-3 show the block diagrams. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 283 figure 8-1. block diag ram of 8-bit timer h0 tmhe0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 toh0/p32/mcgo inttmh0 f prs f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 1 0 f/f r 3 2 pm32 match internal bus 8-bit timer h mode register 0 (tmhmd0) 8-bit timer h compare register 10 (cmp10) decoder selector interrupt generator output controller level inversion pwm mode signal timer h enable signal clear 8-bit timer h compare register 00 (cmp00) output latch (p32) 8-bit timer/ event counter 50 output selector 8-bit timer counter h0 toh0 output chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 284 figure 8-2. block diag ram of 8-bit timer h1 match internal bus tmhe1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 8-bit timer h compare register 1 1 (cmp11) decoder toh1/intp3/p31 8-bit timer h carrier control register 1 (tmcyc1) inttmh1 inttm51 selector interrupt generator output controller level inversion pm31 output latch (p31) 1 0 f/f r pwm mode signal carrier generator mode signal timer h enable signal 3 2 8-bit timer h compare register 0 1 (cmp01) 8-bit timer counter h1 clear rmc1 nrzb1 nrz1 reload/ interrupt control 8-bit timer h mode register 1 (tmhmd1) selector to 8-bit timer 51 f prs f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl f rl /2 7 f rl /2 9 toh1 output chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 285 figure 8-3. block diag ram of 8-bit timer h2 match internal bus tmhe2 cks22 cks21 cks20 tmmd21 tmmd20 tolev2 toen2 8-bit timer h compare register 1 2 (cmp12) decoder ti52 pin input enable signal (toh2 output) inttmh2 selector f prs f prs /2 f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 10 f prs /2 12 interrupt generator output controller level inversion 1 0 f/f r pwm mode signal timer h enable signal 3 2 8-bit timer h compare register 0 2 (cmp02) 8-bit timer counter h2 clear 8-bit timer h mode register 2 (tmhmd2) selector chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 286 (1) 8-bit timer h compar e register 0n (cmp0n) this register can be read or written by an 8-bit memory mani pulation instruction. this r egister is used in all of the timer operation modes. this register constantly compares t he value set to cmp0n with the count val ue of the 8-bit timer counter hn and, when the two values match, generates an interrupt request signal (inttm hn) and inverts the output level of tohn. rewrite the value of cmp0n while the timer is stopped (tmhen = 0). a reset signal generation sets this register to 00h. figure 8-4. format of 8-bit time r h compare register 0n (cmp0n) symbol cmp0n (n = 0 to 2) address: ff18h (cmp00), ff1ah (cmp01), ff44h (cmp02) after reset: 00h r/w 7 6 5 4 32 1 0 caution cmp0n cannot be rewritten during timer count operation. cmp0n can be refreshed (the same value is written) during timer count operation. (2) 8-bit timer h compar e register 1n (cmp1n) this register can be read or written by an 8-bit memory manipulation instruction. this register is used in the pwm output mode and carrier generator mode. in the pwm output mode, this register constantly compares the value set to cmp1n with the count value of the 8- bit timer counter hn and, when the two values match, in verts the output level of tohn. no interrupt request signal is generated. in the carrier generator mode, the cm p1n register always compares the val ue set to cmp1n with the count value of the 8-bit timer counter hn and, wh en the two values match, generates an in terrupt request signal (inttmhn). at the same time, the count value is cleared. cmp1n can be rewritten during timer count operation. if the value of cmp1n is rewritten while the timer is oper ating, the new value is la tched and transferred to cmp1n when the count value of the timer matches the old val ue of cmp1n, and then the valu e of cmp1n is changed to the new value. if matching of the count value and the cmp1n value and wr iting a value to cmp1n conflict, the value of cmp1n is not changed. a reset signal generation sets this register to 00h. figure 8-5. format of 8-bit time r h compare register 1n (cmp1n) symbol cmp1n (n = 0 to 2) address: ff19h (cmp10), ff1bh (cmp11), ff45h (cmp12) after reset: 00h r/w 7 6 5 4 32 1 0 caution in the pwm output mode and carrier genera tor mode, be sure to set cmp1n when starting the timer count operation (tmhen = 1) after the ti mer count operation was stopped (tmhen = 0) (be sure to set again even if se tting the same value to cmp1n). remark n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 287 8.3 registers controlling 8-bit timers h0, h1, and h2 the following four registers are used to control 8-bit timers h0, h1, and h2. ? 8-bit timer h mode register n (tmhmdn) ? 8-bit timer h carrier control register 1 (tmcyc1) note ? port mode register 3 (pm3) ? port register 3 (p3) note 8-bit timer h1 only (1) 8-bit timer h mode register n (tmhmdn) this register controls the mode of timer h. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark n = 0 to 2 chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 288 figure 8-6. format of 8-bit time r h mode register 0 (tmhmd0) tmhe0 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe0 0 1 timer operation enable tmhmd0 cks02 cks01 cks00 tmmd01 tmmd00 tolev0 toen0 address: ff69h after reset: 00h r/w cks02 0 0 0 0 1 1 cks01 0 0 1 1 0 0 cks00 0 1 0 1 0 1 count clock selection note 1 other than above interval timer mode pwm mode setting prohibited tmmd01 0 1 tmmd00 0 0 timer operation mode low level high level tolev0 0 1 timer output level control (in default mode) disables output enables output toen0 0 1 timer output control other than above <7> 6 5 4 3 2 <1> <0> f prs note 2 f prs /2 f prs /2 2 f prs /2 6 f prs /2 10 tm50 output note 3 setting prohibited f prs = 2 mhz 2 mhz 1 mhz 500 khz 31.25 khz 1.95 khz f prs = 5 mhz 5 mhz 2.5 mhz 1.25 mhz 78.13 khz 4.88 khz f prs = 10 mhz 10 mhz 5 mhz 2.5 mhz 156.25 khz 9.77 khz notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of cks02 = cks01 = cks00 = 0 (count clock: f prs ) is prohibited. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 289 notes 3. note the following points when select ing the tm50 output as the count clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of the 8-bit ti mer/event counter 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of the 8-bit ti mer/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. cautions 1. when tmhe0 = 1, setting the other bits of tmhmd0 is prohibited. however, tmhmd0 can be refreshed (the same va lue is written). 2. in the pwm output mode, be sure to set the 8-bit timer h compare register 10 (cmp10) when starting the timer count operation (tmhe0 = 1) after the timer count operation was stopped (tmhe0 = 0) (be sure to set again even if setting the same value to cmp10). 3. the actual toh0/p32/mcgo pin output is determined depending on pm 32 and p32, besides toh0 output. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 290 figure 8-7. format of 8-bit time r h mode register 1 (tmhmd1) tmhe1 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe1 0 1 timer operation enable tmhmd1 cks12 cks11 cks10 tmmd11 tmmd10 tolev1 toen1 address: ff6ch after reset: 00h r/w interval timer mode carrier generator mode pwm output mode setting prohibited tmmd11 0 0 1 1 tmmd10 0 1 0 1 timer operation mode low level high level tolev1 0 1 timer output level control (in default mode) disables output enables output toen1 0 1 timer output control <7> 6 5 4 3 2 <1> <0> f prs note 2 f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 12 f rl /2 7 f rl /2 9 f rl cks12 0 0 0 0 1 1 1 1 cks11 0 0 1 1 0 0 1 1 cks10 0 1 0 1 0 1 0 1 f prs = 2 mhz 2 mhz 500 khz 125 khz 31.25 khz 0.49 khz 1.88 khz (typ.) 0.47 khz (typ.) 240 khz (typ.) count clock selection note 1 f prs = 5 mhz 5 mhz 1.25 mhz 312.5 khz 78.13 khz 1.22 khz f prs = 10 mhz 10 mhz 2.5 mhz 625 khz 156.25 khz 2.44 khz notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of cks12 = cks11 = cks10 = 0 (count clock: f prs ) is prohibited. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 291 cautions 1. when tmhe1 = 1, setting the other bits of tmhmd1 is prohibited. however, tmhmd1 can be refreshed (the same va lue is written). 2. in the pwm output mode and carrier generato r mode, be sure to set the 8-bit timer h compare register 11 (cmp11) when star ting the timer count operation (tmh e1 = 1) after the timer count operation was stopped (tmhe1 = 0) (be sure to set again even if setting the same value to cmp11). 3. when the carrier generator mode is used, set so that the count clock frequency of tmh1 becomes more than 6 times the count clock frequency of tm51. 4. the actual toh1/p31/intp3 pin output is determined depending on pm31 and p31, besides toh1 output. remarks 1. f prs : peripheral hardware clock frequency 2. f rl : internal low-speed oscillation clock frequency chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 292 figure 8-8. format of 8-bit time r h mode register 2 (tmhmd2) tmhe2 stops timer count operation (counter is cleared to 0) enables timer count operation (count operation started by inputting clock) tmhe2 0 1 timer operation enable tmhmd2 cks22 cks21 cks20 tmmd21 tmmd20 tolev2 toen2 address: ff42h after reset: 00h r/w interval timer mode input enable width adjust mode for pins (pwm mode) tmmd21 0 1 tmmd20 0 0 timer operation mode low level high level tolev2 0 1 timer output level control (in default mode) disables output enables output note 3 toen2 0 1 timer output control <7> 6 5 4 3 2 <1> <0> cks22 0 0 0 0 1 1 1 cks21 0 0 1 1 0 0 1 cks20 0 1 0 1 0 1 0 count clock selection note 1 setting prohibited other than above setting prohibited other than above f prs note 2 f prs /2 f prs /2 2 f prs /2 4 f prs /2 6 f prs /2 10 f prs /2 12 f prs = 2 mhz 2 mhz 1 mhz 500 khz 125 khz 31.25 khz 1.95 khz 0.49 khz f prs = 5 mhz 5 mhz 2.5 mhz 1.25 mhz 312.5 khz 78.13 khz 4.88 khz 1.22 khz f prs = 10 mhz 10 mhz 5 mhz 2.5 mhz 625 khz 156.25 khz 9.77 khz 2.44 khz notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of cks22 = cks21 = cks20 = 0 (count clock: f prs ) is prohibited. 3. the timer output of tmh2 can only be used as an external event input enabl e signal of tm52. no pins for external output are available. caution when tmhe2 = 1, setting the ot her bits of tmhmd2 is prohibited. remark f prs : peripheral hardware clock frequency chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 293 (2) 8-bit timer h carrier control register 1 (tmcyc1) this register controls the remote control output and carrier pulse output status of 8-bit timer h1. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 8-9. format of 8-bit timer h carrier control register 1 (tmcyc1) 0 tmcyc1 0 0 0 0 rmc1 nrzb1 nrz1 address: ff6dh after reset: 00h r/w note symbol low-level output high-level output at rising edge of inttm51 signal input low-level output carrier pulse output at rising edge of inttm51 signal input rmc1 0 0 1 1 nrzb1 0 1 0 1 remote control output carrier output disabled status (low-level status) carrier output enabled status (rmc1 = 1: carrier pulse output, rmc1 = 0: high-level status) nrz1 0 1 carrier pulse output status flag <0> note bit 0 is read-only. caution do not rewrite rmc1 when tmhe1 = 1. ho wever, tmcyc1 can be refreshed (the same value is written). (3) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p32/toh0/mcgo and p31/toh1/intp3 pi ns for timer output, clear pm32 and pm31 and the output latches of p32 and p31 to 0. pm3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 8-10. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 294 8.4 operation of 8-bit timers h0, h1 and h2 8.4.1 operation as inter val timer/square-wave output when the 8-bit timer counter hn and compare register 0n (cmp0n) match, an interrupt request signal (inttmhn) is generated and the 8-bit timer counter hn is cleared to 00h. compare register 1n (cmp1n) is not used in interval timer mode. since a match of the 8-bit timer counter hn and the cmp1n register is not detect ed even if the cmp1n register is set, timer output is not affected. by setting bit 0 (toenn) of timer h mode register n (tmh mdn) to 1, a square wave of any frequency (duty = 50%) is output from tohn. the timer output of tmh2 can only be used as an extern al event input enable signal of tm52. note, no pins for external output are available. setting <1> set each register. figure 8-11. register setting during inte rval timer/square-wave output operation (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 0 0 0/1 0/1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output setting default setting of timer output level interval timer mode setting count clock (f cnt ) selection count operation stopped (ii) cmp0n register setting the interval time is as follows if n is set as a comparison value. ? interval time = (n +1)/f cnt <2> count operation starts when tmhen = 1. <3> when the values of the 8-bit timer counter hn and the cmp0n register match, the inttmhn signal is generated and the 8-bit timer counter hn is cleared to 00h. <4> subsequently, the inttmhn signal is generated at t he same interval. to stop the count operation, clear tmhen to 0. remarks 1. for the setting of the output pin, see 8.3 (3) port mode register 3 (pm3) . 2. for how to enable the inttmhn signal interrupt, see chapter 21 interrupt functions . 3. n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 295 figure 8-12. timing of interval time r/square-wave output operation (1/2) (a) basic operation (operation when 01h cmp0n feh) 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h n clear interval time clear n 00h 01h n 00h 01h 00h <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <2> level inversion, match interrupt occurrence, 8-bit timer counter hn clear <3> <1> <1> the count operation is enabled by setting the tmhen bi t to 1. the count clock starts counting no more than 1 clock after the operation is enabled. <2> when the value of the 8-bit timer counter hn matches the value of the cmp0n regist er, the value of the timer counter is cleared, and the level of th e tohn output is inverted. in addition, the inttmhn signal is output at the rising edge of the count clock. <3> if the tmhen bit is cleared to 0 while timer h is oper ating, the inttmhn signal and tohn output are set to the default level. if they are already at the default level before the tmhen bit is cleared to 0, then that level is maintained. remarks 1. n = 0 to 2, however, toh0 and toh1 only for tohn 2. 01h n feh chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 296 figure 8-12. timing of interval time r/square-wave output operation (2/2) (b) operation when cmp0n = ffh 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 01h feh clear clear ffh 00h feh ffh 00h ffh interval time (c) operation when cmp0n = 00h count clock count start 8-bit timer counter hn cmp0n tmhen inttmhn tohn 00h 00h interval time remark n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 297 8.4.2 operation as pwm output in pwm output mode, a pulse with an arbi trary duty and arbitrary cycle can be output. the 8-bit timer compare register 0n (cmp0n) controls the cycle of timer output (tohn). rewriting the cmp0n register during timer operation is prohibited. the 8-bit timer compare register 1n (cmp1n) controls the duty of timer output (toh n). rewriting the cmp1n register during timer operation is possible. the operation in pwm output mode is as follows. pwm output (tohn output) output s an active level and 8-bit timer counter hn is cleared to 0 when 8-bit timer counter hn and the cmp0n register match after the timer count is started. pwm out put (tohn output) outputs an inactive level when 8-bit timer counter hn and the cmp1n register match. the timer output of tmh2 (pwm output) can only be used as an external event input enable signal of tm52. note, no pins for external output are available. setting <1> set each register. figure 8-13. register setting in pwm output mode (i) setting timer h mode register n (tmhmdn) 0 0/1 0/1 0/1 1 0 0/1 1 tmmdn0 tolevn toenn cksn1 cksn2 tmhen tmhmdn cksn0 tmmdn1 timer output enabled default setting of timer output level pwm output mode selection count clock (f cnt ) selection count operation stopped (ii) setting cmp0n register ? compare value (n): cycle setting (iii) setting cmp1n register ? compare value (m): duty setting remarks 1. n = 0 to 2, however, toh0 and toh1 only for tohn 2. 00h cmp1n (m) < cmp0n (n) ffh <2> the count operation starts when tmhen = 1. <3> the cmp0n register is the compare re gister that is to be compared first after counter operation is enabled. when the values of the 8-bit timer c ounter hn and the cmp0n register matc h, the 8-bit timer counter hn is cleared, an interrupt request signal (inttmhn) is generated, an active level is output. at the same time, the compare register to be compared with the 8-bit timer c ounter hn is changed from the cmp0n register to the cmp1n register. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 298 <4> when the 8-bit timer counter hn and the cmp1n regist er match, an inactive level is output and the compare register to be compared with 8-bit timer counter hn is changed from the cmp1n register to the cmp0n register. at this time, 8-bit timer counter hn is not cleared and the inttmhn signal is not generated. <5> by performing procedures <3> and <4> repeatedl y, a pulse with an arbitrary duty can be obtained. <6> to stop the count operation, set tmhen = 0. if the setting value of the cmp0n regist er is n, the setting value of the cmp1n register is m, and the count clock frequency is f cnt , the pwm pulse output cycle and duty are as follows. ? pwm pulse output cycle = (n + 1)/f cnt ? duty = (m + 1)/(n + 1) cautions 1. the set value of the cmp1n register ca n be changed while the time r counter is operating. however, this takes a duration of three operati ng clocks (signal selected by the cksn2 to cksn0 bits of the tmhmdn register) from when the value of the cmp1n register is changed until the value is transferred to the register. 2. be sure to set the cmp1n register when st arting the timer count opera tion (tmhen = 1) after the timer count operation was stopped (tmhen = 0) (be sure to set again even if setting the same value to the cmp1n register). 3. make sure that the cmp1n re gister setting value (m) and cmp0 n register setting value (n) are within the following range. 00h cmp1n (m) < cmp0n (n) ffh remarks 1. for the setting of the output pin, see 8.3 (3) port mode register 3 (pm3) . 2. for details on how to enable the inttmhn signal interrupt, see chapter 21 interrupt functions . 3. n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 299 figure 8-14. operation timing in pwm output mode (1/4) (a) basic operation count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) tohn (tolevn = 1) 00h 01h a5h 00h 01h 02h a5h 00h a5h 00h 01h 02h cmp1n a5h 01h <1> <2> <3> <4> <1> the count operation is enabled by setting the tmhen bit to 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, pwm output outputs an inactive level. <2> when the values of 8-bit timer count er hn and the cmp0n register match, an active level is output. at this time, the value of 8-bit timer counter hn is cleared, and the inttmhn signal is output. <3> when the values of 8-bit timer count er hn and the cmp1n register match, an inactive level is output. at this time, the 8-bit counter value is not cleared and the inttmhn signal is not output. <4> clearing the tmhen bit to 0 during timer hn operat ion sets the inttmhn signal to the default and pwm output to an inactive level. remark n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 300 figure 8-14. operation timing in pwm output mode (2/4) (b) operation when cmp0n = ffh, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h ffh 00h 01h 02h ffh 00h ffh 00h 01h 02h cmp1n ffh 00h (c) operation when cmp0n = ffh, cmp1n = feh count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h feh ffh 00h 01h feh ffh 00h 01h feh ffh 00h cmp1n ffh feh remark n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 301 figure 8-14. operation timing in pwm output mode (3/4) (d) operation when cmp0n = 01h, cmp1n = 00h count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 01h 00h 01h 00h 01h 00h 00h 01h 00h 01h cmp1n 00h remark n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 302 figure 8-14. operation timing in pwm output mode (4/4) (e) operation by changi ng cmp1n (cmp1n = 02h 03h, cmp0n = a5h) count clock 8-bit timer counter hn cmp0n tmhen inttmhn tohn (tolevn = 0) 00h 01h 02h a5h 00h 01h 02h 03h a5h 00h 01h 02h 03h a5h 00h <1> <4> <3> <2> cmp1n <6> <5> 02h a5h 03h 02h (03h) <2>? 80h <1> the count operation is enabled by setting tmhen = 1. start 8-bit timer counter hn by masking one count clock to count up. at this time, pwm output outputs an inactive level. <2> the cmp1n register value can be changed during timer counter operation. this operation is asynchronous to the count clock. <3> when the values of 8-bit timer count er hn and the cmp0n register match, the value of 8-bit timer counter hn is cleared, an active level is output, and the inttmhn signal is output. <4> if the cmp1n register value is changed, the value is latched and not transferred to the register. when the values of the 8-bit timer counter hn and the cmp1 n register before the cha nge match, the value is transferred to the cmp1n register and the cm p1n register value is changed (<2>?). however, three count clocks or more are required fr om when the cmp1n register value is changed to when the value is transferred to the register. if a match signal is generated within thr ee count clocks, the changed value cannot be transferred to the register. <5> when the values of 8-bit timer counter hn and the cm p1n register after the change match, an inactive level is output. 8-bit timer counter hn is not cl eared and the inttmhn signal is not generated. <6> clearing the tmhen bit to 0 during timer hn operat ion sets the inttmhn signal to the default and pwm output to an inactive level. remark n = 0 to 2, however, toh0 and toh1 only for tohn chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 303 8.4.3 carrier generator opera tion (8-bit timer h1 only) in the carrier generator mode, the 8-bit timer h1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). the carrier clock generated by the 8-bit timer h1 is output in the cycle set by the 8-bit timer/event counter 51. in carrier generator mode, the output of the 8-bit timer h1 carrier pulse is controlled by the 8-bit timer/event counter 51, and the carrier pulse is output from the toh1 output. (1) carrier generation in carrier generator mode, the 8-bit timer h compare r egister 01 (cmp01) generates a low-level width carrier pulse waveform and the 8-bit timer h compare register 11 (cmp11) generates a high-level width carrier pulse waveform. rewriting the cmp11 register during t he 8-bit timer h1 operation is possible but rewriting the cm p01 register is prohibited. (2) carrier output control carrier output is controlled by the in terrupt request signal (inttm51) of t he 8-bit timer/event counter 51 and the nrzb1 and rmc1 bits of the 8-bit timer h carrier co ntrol register (tmcyc1). the relationship between the outputs is shown below. rmc1 bit nrzb1 bit output 0 0 low-level output 0 1 high-level output at rising edge of inttm51 signal input 1 0 low-level output 1 1 carrier pulse output at rising edge of inttm51 signal input chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 304 to control the carrier pulse output during a count operation, the nrz1 and nrzb1 bits of the tmcyc1 register have a master and slave bit configuratio n. the nrz1 bit is read-only but t he nrzb1 bit can be read and written. the inttm51 signal is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. the inttm5h1 signal becomes the data transfer signal of the nrz1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the timing for transfer from the nrz b1 bit to the nrz1 bit is as shown below. figure 8-15. transfer timing 8-bit timer h1 count clock tmhe1 inttm51 inttm5h1 nrz1 nrzb1 rmc1 1 1 1 0 00 <1> <2> <3> <1> the inttm51 signal is synchronized with the count clock of the 8-bit timer h1 and is output as the inttm5h1 signal. <2> the value of the nrzb1 bit is tr ansferred to the nrz1 bit at the second clock from the rising edge of the inttm5h1 signal. <3> write the next value to the nrzb1 bit in the inte rrupt servicing program t hat has been started by the inttm5h1 interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr51 register. cautions 1. do not rewrite the nrzb1 bit again until at least the second clock afte r it has been rewritten, or else the transfer from the nrzb1 bi t to the nrz1 bit is not guaranteed. 2. when the 8-bit timer/event c ounter 51 is used in the carrier generator mode, an interrupt is generated at the timing of <1>. when the 8-bit time r/event counter 51 is used in a mode other than the carrier generator mode, the timi ng of the interrupt generation differs. remark inttm5h1 is an internal signal and not an interrupt source. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 305 setting <1> set each register. figure 8-16. register setting in carrier generator mode (i) setting 8-bit timer h m ode register 1 (tmhmd1) 0 0/1 0/1 0/1 0 timer output enabled default setting of timer output level carrier generator mode selection count clock (f cnt ) selection count operation stopped 1 0/1 1 tmmd10 tolev1 toen1 cks11 cks12 tmhe1 tmhmd1 cks10 tmmd11 (ii) cmp01 register setting ? compare value (iii) cmp11 register setting ? compare value (iv) tmcyc1 register setting ? rmc1 = 1 ... remote control output enable bit ? nrzb1 = 0/1 ... carrier output enable bit (v) tcl51 and tmc51 register setting ? see 7.3 registers controlling 8-bit ti mer/event counters 50, 51, and 52 . <2> when tmhe1 = 1, the 8-bit timer h1 starts counting. <3> when tce51 of the 8-bit timer mode control register 51 (tmc51) is set to 1, the 8-bit timer/event counter 51 starts counting. <4> after the count operation is enabled, the first compar e register to be compared is the cmp01 register. when the count value of the 8-bit timer counter h1 and the cmp01 register value match, the inttmh1 signal is generated, the 8-bit timer c ounter h1 is cleared. at the same time, the compare register to be compared with the 8-bit timer counter h1 is switc hed from the cmp01 register to the cmp11 register. <5> when the count value of the 8-bit timer counter h1 and the cmp11 register value match, the inttmh1 signal is generated, the 8-bit timer c ounter h1 is cleared. at the same time, the compare register to be compared with the 8-bit timer counter h1 is switc hed from the cmp11 register to the cmp01 register. <6> by performing procedures <4> and <5> r epeatedly, a carrier clock is generated. <7> the inttm51 signal is synchronized with count clock of the 8-bit timer h1 and output as the inttm5h1 signal. the inttm5h1 signal becomes the data trans fer signal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <8> write the next value to the nrzb1 bit in the inte rrupt servicing program that has been started by the inttm5h1 interrupt or after timing has been checked by polling the interrupt request flag. write data to count the next time to the cr51 register. <9> when the nrz1 bit is high level, a carrier clock is output by toh1 output. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 306 <10> by performing the procedures above, an arbitrary carrier clock is obtained. to stop the count operation, clear tmhe1 to 0. if the setting value of the cmp01 regist er is n, the setting value of the cmp11 register is m, and the count clock frequency is f cnt , the carrier clock output cycle and duty are as follows. ? carrier clock output cycle = (n + m + 2)/f cnt ? duty = high-level width/carrier cl ock output width = (m + 1)/(n + m + 2) cautions 1. be sure to set the cmp11 register when starting the timer count operation (tmhe1 = 1) after the timer count operation was stopped (tmh e1 = 0) (be sure to set again even if setting the same value to the cmp11 register). 2. set so that the count clock frequency of tmh1 becomes more th an 6 times the count clock frequency of tm51. 3. set the values of the cmp01 and cmp 11 registers in a range of 01h to ffh. 4. the set value of the cmp11 register can be changed while the timer counter is operating. however, it takes the duration of three operating clocks (signal selected by the cks12 to cks10 bits of the tmhmd1 re gister) since the val ue of the cmp11 register has been changed until the val ue is transferred to the register. 5. be sure to set the rmc1 bit be fore the count operation is started. remarks 1. for the setting of the output pin, see 8.3 (3) port mode register 3 (pm3) . 2. for how to enable the inttmh1 signal interrupt, see chapter 21 interrupt functions . chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 307 figure 8-17. carrier generator mode operation timing (1/3) (a) operation when cmp01 = n, cmp11 = n cmp01 cmp11 tmhe1 inttmh1 carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 51 count clock tm51 count value cr5 1 tce5 1 toh 1 0 0 1 1 0 0 1 1 0 0 inttm5 1 nrzb 1 nrz 1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h 1 <1><2> <3> <4> <5> <6> <7> 8-bit timer h1 count clock 8-bit timer counter h1 count value k l m n <1> when tmhe1 = 0 and tce51 = 0, the 8-bi t timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, the 8-bit timer counter h1 starts a count operation. at that time, the carrier clock remains default. <3> when the count value of the 8-bit timer counter h1 matches the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8- bit timer counter h1 is switched from the cmp01 register to the cmp11 r egister. the 8-bit timer counter h1 is cleared to 00h. <4> when the count value of the 8-bit timer counter h1 matches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. the 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> the inttm5h1 signal becomes the data transfer si gnal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. <7> when nrz1 = 0 is set, the toh1 output becomes low level. remark inttm5h1 is an internal signal and not an interrupt source. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 308 figure 8-17. carrier generator mode operation timing (2/3) (b) operation when cmp01 = n, cmp11 = m n cmp01 cmp11 tmhe1 inttmh1 carrier clock tm51 count value 00h n 00h 01h m 00h n 00h 01h m 00h 00h n m tce51 toh1 0 0 1 1 0 0 1 1 0 0 inttm51 nrzb1 nrz1 carrier clock 00h 01h k 00h 01h l 00h 01h m 00h 01h 00h 01h n inttm5h1 <1><2> <3> <4> <5> <6> <7> 8-bit timer 51 count clock 8-bit timer h1 count clock 8-bit timer counter h1 count value k cr51 l m n <1> when tmhe1 = 0 and tce51 = 0, the 8-bi t timer counter h1 operation is stopped. <2> when tmhe1 = 1 is set, the 8-bit timer counter h1 starts a count operation. at that time, the carrier clock remains default. <3> when the count value of the 8-bit timer counter h1 matches the cmp01 register value, the first inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8- bit timer counter h1 is switched from the cmp01 register to the cmp11 r egister. the 8-bit timer counter h1 is cleared to 00h. <4> when the count value of the 8-bit timer counter h1 matches the cmp11 register value, the inttmh1 signal is generated, the carrier clock signal is inverted, and the compare register to be compared with the 8-bit timer counter h1 is switched from the cmp11 register to the cmp01 register. the 8-bit timer counter h1 is cleared to 00h. by performing procedures <3> and <4> repeatedly , a carrier clock with duty fixed to other than 50% is generated. <5> when the inttm51 signal is generated, it is synchronized with the 8-bit timer h1 count clock and is output as the inttm5h1 signal. <6> a carrier signal is output at the first rising edge of the carrier clock if nrz1 is set to 1. <7> when nrz1 = 0, the toh1 output is held at the high level and is not changed to low level while the carrier clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed). remark inttm5h1 is an internal signal and not an interrupt source. chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 309 figure 8-17. carrier generator mode operation timing (3/3) (c) operation when cmp11 is changed 8-bit timer h1 count clock cmp01 tmhe1 inttmh1 carrier clock 00h 01h n 00h 01h 01h m 00h n 00h l 00h <1> <3>? <4> <3> <2> cmp11 <5> m n l m (l) 8-bit timer counter h1 count value <1> when tmhe1 = 1 is set, the 8-bit timer h1 starts a c ount operation. at that time, the carrier clock remains default. <2> when the count value of the 8-bit timer counter h1 matches the value of the cmp01 register, the inttmh1 signal is output, the carrier signal is inverted, and the ti mer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with t hat of the 8-bit timer count er h1 is changed from the cmp01 register to the cmp11 register. <3> the cmp11 register is asynchronous to the count cl ock, and its value can be changed while the 8-bit timer h1 is operating. the new value (l) to which the value of the register is to be changed is latched. when the count value of the 8-bit timer counter h1 matches the value (m) of the cmp11 regist er before the change, the cmp11 register is changed (<3>?). however, it takes three count clo cks or more since the value of the cmp11 register ha s been changed until the value is transferred to the regist er. even if a match signal is generat ed before the duration of three count clocks elapses, the new value is not transferred to the register. <4> when the count value of 8-bit timer counter h1 ma tches the value (m) of the cmp1 register before the change, the inttmh1 signal is output, the carrier signal is inverted, and the timer counter is cleared to 00h. at the same time, the compare register whose value is to be compared with that of the 8-bit timer counter h1 is changed from the cmp11 regi ster to the cmp01 register. <5> the timing at which the count value of the 8-bit ti mer counter h1 and the cmp11 register value match again is indicated by the value after the change (l). chapter 8 8-bit timers h0, h1, and h2 user?s manual u18329ej4v0ud 310 8.4.4 control of number of carri er clocks by timer 51 counter the number of carrier clocks to be output from the toh1 pin can be controll ed by selecting the timer h1 output signal for the 8-bit timer 51 count clock. figure 8-18 shows an example of cont rol when three carrier clocks are to be output from the toh1 pin figure 8-18. example of controlling number of carrier clocks by timer 51 counter (setting timer h1 output signal for timer 51 count clock (tcl51 = 07h)) cmp01 cmp11 tmhe1 inttmh1 carrier clock 00h n 00h n 00h n 00h n 00h n 00h n n n 8-bit timer 51 count clock tm5 1 count value cr5 1 tce5 1 toh 1 0 1 inttm5 1 nrzb 1 nrz 1 carrier clock inttm5h 1 8-bit timer h1 count clock 8-bit timer counter h1 count value 00h 01h 02h 02h 00h 10 01h 00h n 00h n 00h n <1> <3> <4> <2> <1> set the cr51 register to 02h when three carr ier clocks are to be output from the toh1 pin. <2> the inttm51 signal is generated when the tm51 c ount value and the cr51 register value (02h) have matched. the signal is synchroniz ed with the 8-bit timer h1 count cl ock and is output as the inttm5h1 signal. <3> the inttm5h1 signal becomes the data transfer sig nal for the nrzb1 bit, and the nrzb1 bit value is transferred to the nrz1 bit. the transfer timing at this time is one timer h1 count clock after a rise of the inttm5h1 signal. <4> by setting nrz1 to 0, the toh1 output becomes low level after having output the third carrier clock. remark inttm5h1 is an internal signal and not an interrupt source. user?s manual u18329ej4v0ud 311 chapter 9 real-time counter 9.1 functions of real-time counter the real-time counter ha s the following features. ? having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. ? constant-period interrupt function (period: 1 month to 0.5 seconds) ? alarm interrupt function (alarm: week, hour, minute) ? interval interrupt function ? pin output function of 1 hz ? pin output function of 512 hz or 16.384 khz or 32.768 khz 9.2 configuration of real-time counter the real-time counter includes the following hardware. table 9-1. configuration of real-time counter item configuration control registers real-time counter clock selection register (rtccl) real-time counter control register 0 (rtcc0) real-time counter control register 1 (rtcc1) real-time counter control register 2 (rtcc2) sub-count register (rsubc) second count register (sec) minute count register (min) hour count register (hour) day count register (day) week count register (week) month count register (month) year count register (year) watch error correction register (subcud) alarm minute register (alarmwm) alarm hour register (alarmwh) alarm week register (alarmww) chapter 9 real-time counter user?s manual u18329ej4v0ud 312 figure 9-1. block diagra m of real-time counter intrtc f sub rtce rcloe1 rcloe0 ampm ct2 ct1 ct0 rinte rcloe2 ict2 ict1 ict0 rtce ampm ct0 to ct2 rckdiv f sub rtc1hz rtccl1 rtccl0 rckdiv rinte rtcdiv/rtccl intrtci rcloe2 f rtc rwait wale walie wafg rwait rwst rifg rwst rifg 12-bit counter real-time counter control register 1 (rtcc1) real-time counter control register 0 (rtcc0) alarm week register (alarmww) (7-bit) alarm hour register (alarmwh) (6-bit) alarm minute register (alarmwm) (7-bit) year count register (year) (8-bit) month count register (month) (5-bit) week count register (week) (3-bit) day count register (day) (6-bit) hour count register (hour) (6-bit) minute count register (min) (7-bit) second count register (sec) (7-bit) wait control 0.5 seconds sub-count register (rsubc) (16-bit) count clock = 32.768 khz selector buffer buffer buffer buffer buffer buffer buffer count enable/ disable circuit watch error correction register (subcud) (8-bit) selector selector internal bus real-time counter control register 2 (rtcc2) real-time counter clock selection register (rtccl) 1 month 1 day 1 hour 1 minute f prs /2 7 f prs /2 8 selector f rtc chapter 9 real-time counter user?s manual u18329ej4v0ud 313 9.3 registers controlling real-time counter timer real-time counter is controlle d by the following 16 registers. (1) real-time counter clock selection register (rtccl) this register controls t he mode of real-time counter. rtccl can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-2. format of real-time count er clock selection register (rtccl) address: ff54h after reset: 00h r/w symbol 7 6 5 4 3 2 <1> <0> rtccl 0 0 0 0 0 0 rtccl1 rtccl0 rtccl1 rtccl0 control of real-time counter (rtc) input clock (f rtc ) 0 0 f sub 0 1 f prs /2 7 1 0 f prs /2 8 1 1 setting prohibited remark ? when f prs = 4.19 mhz, f rtc = f prs /2 7 = 32.768 khz ? when f prs = 8.38 mhz, f rtc = f prs /2 8 = 32.768 khz (2) real-time counter cont rol register 0 (rtcc0) the rtcc0 register is an 8-bit register that is used to start or stop the real-time co unter operation, control the rtccl and rtc1hz pins, and set a 12- or 24-hour system and the constant-per iod interrupt function. rtcc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. chapter 9 real-time counter user?s manual u18329ej4v0ud 314 figure 9-3. format of real-time c ounter control register 0 (rtcc0) address: ff89h after reset: 00h r/w symbol <7> 6 <5> <4> 3 2 1 0 rtcc0 rtce 0 rcloe1 rcloe0 ampm ct2 ct1 ct0 rtce real-time counter operation control 0 stops counter operation. 1 starts counter operation. rcloe1 rtc1hz pin output control 0 disables output of rtc1hz pin (1 hz). 1 enables output of rtc1hz pin (1 hz). rcloe0 note rtccl pin output control 0 disables output of rtccl pin (32.768 khz). 1 enables output of rtccl pin (32.768 khz). ampm selection of 12-/24-hour system 0 12-hour system (a.m. and p.m. are displayed.) 1 24-hour system ? to change the value of ampm, set rwait (bit 0 of rtcc 1) to 1, and re-set the hour count register (hour). ? table 9-2 shows the displayed time digits. ct2 ct1 ct0 constant-period interrupt (intrtc) selection 0 0 0 does not use constant-period interrupt function. 0 0 1 once per 0.5 s (synchronized with second count up) 0 1 0 once per 1 s (same time as second count up) 0 1 1 once per 1 m (second 00 of every minute) 1 0 0 once per 1 hour (minute 00 and second 00 of every hour) 1 0 1 once per 1 day (hour 00, minute 00, and second 00 of every day) 1 1 once per 1 month (day 1, hour 00 a.m., minute 00, and second 00 of every month) after changing the values of ct2 to ct0, clear the interrupt request flag. note rcloe0 and rcloe2 must not be enabled at the same time. caution if rcloe0 and rcloe1 are changed when rtce = 1, a pulse with a narrow width may be generated on the 32.768 khz and 1 hz output signals. remark : don?t care chapter 9 real-time counter user?s manual u18329ej4v0ud 315 (3) real-time counter cont rol register 1 (rtcc1) the rtcc1 register is an 8-bit regist er that is used to control the alarm interrupt function and the wait time of the counter. rtcc1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-4. format of real-time count er control register 1 (rtcc1) (1/2) address: ff8ah after reset: 00h r/w symbol <7> <6> 5 <4> <3> 2 <1> <0> rtcc1 wale walie 0 wafg rifg 0 rwst rwait wale alarm operation control 0 match operation is invalid. 1 match operation is valid. to set the registers of alarm (walie flag of rt cc1, alarmwm register, alarmwh register, and alarmww register), disable wale (clear it to ?0?). walie control of alarm interrupt (intrtc) function operation 0 does not generate interrupt on matching of alarm. 1 generates interrupt on matching of alarm. wafg alarm detection status flag 0 alarm mismatch 1 detection of matching of alarm this is a status flag that indicates detection of matching wi th the alarm. it is valid only when wale = 1 and is set to ?1? one clock (32.768 khz) after matching of the alarm is detec ted. this flag is cleared w hen ?0? is written to it. writing ?1? to it is invalid. rifg constant-period interrupt status flag 0 constant-period interrupt is not generated. 1 constant-period interrupt is generated. this flag indicates the status of generation of the const ant-period interrupt. when the constant-period interrupt is generated, it is set to ?1?. this flag is cleared when ?0? is written to it. writing ?1? to it is invalid. rwst wait status flag of real-time counter 0 counter is operating. 1 mode to read or write counter value this status flag indicates whether the setting of rwait is valid. before reading or writing the counter value, confirm that the value of this flag is 1. chapter 9 real-time counter user?s manual u18329ej4v0ud 316 figure 9-4. format of real-time count er control register 1 (rtcc1) (2/2) rwait wait control of real-time counter 0 sets counter operation. 1 stops sec to year counters. mode to read or write counter value this bit controls the operation of the counter. be sure to write ?1? to it to read or write the counter value. because rsubc continues operation, complete reading or writ ing of it in 1 second, and clear this bit back to 0. when rwait = 1, it takes up to 1 clock (32.768 khz) until the counter value can be read or written. if rsubc overflows when rwait = 1, it counts up after rwai t = 0. if the second count register is written, however, it does not count up because rsubc is cleared. caution the rifg and wafg flags may be cleared when the rtcc1 regi ster is written by using a 1-bit manipulation instruction. use, th erefore, an 8-bit manipulation in struction in order to write to the rtcc1 register. to prevent the rifg and wa fg flags from being cl eared during writing, disable writing by setting ?1? to the correspondi ng bit. when the value may be rewritten because the rifg and wafg flags are not being used, the rtcc1 register may be written by using a 1-bit manipulation instruction. remark fixed-cycle interrupts and alarm match interrupts use the same interrupt source (intrtc). when using these two types of interrupt s at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (r ifg) and the alarm detecti on status flag (wafg) upon intrtc occurrence. chapter 9 real-time counter user?s manual u18329ej4v0ud 317 (4) real-time counter cont rol register 2 (rtcc2) the rtcc2 register is an 8-bit register that is used to control the interval interrupt function and the rtcdiv pin. rtcc2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-5. format of real-time c ounter control register 2 (rtcc2) address: ff8bh after reset: 00h r/w symbol <7> <6> <5> 4 3 2 1 0 rtcc2 rinte rcloe2 rckdiv 0 0 ict2 ict1 ict0 rinte ict2 ict1 ict0 interval interrupt (intrtci) selection 0 interval interrupt is not generated. 1 0 0 0 2 6 /f rtc (1.953125 ms) 1 0 0 1 2 7 /f rtc (3.90625 ms) 1 0 1 0 2 8 /f rtc (7.8125 ms) 1 0 1 1 2 9 /f rtc (15.625 ms) 1 1 0 0 2 10 /f rtc (31.25 ms) 1 1 0 1 2 11 /f rtc (62.5 ms) 1 1 1 2 12 /f rtc (125 ms) rcloe2 note rtcdiv pin output control 0 output of rtcdiv pin is disabled. 1 output of rtcdiv pin is enabled. rckdiv selection of rtcdiv pin output frequency 0 rtcdiv pin outputs 512 hz (1.95 ms). 1 rtcdiv pin outputs 16.384 khz (0.061 ms). note rcloe0 and rcloe2 must not be enabled at the same time. cautions 1. change ict2, ict1, and ict0 when rinte = 0. 2. when the output from rtcdiv pin is stoppe d, the output continu es after a maximum of two clocks of f rtc and enters the low level. while 512 hz is output, and when the output is stopped immediately after entering the high leve l, a pulse of at least one clock width of f xt may be generated. chapter 9 real-time counter user?s manual u18329ej4v0ud 318 (5) sub-count re gister (rsubc) the rsubc register is a 16-bit register that counts the reference time of 1 second of the real-time counter. it takes a value of 0000h to 7fffh and counts 1 second with a clock of 32.768 khz. rsubc can be set by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. cautions 1. when a correction is made by using the subcud regi ster, the value may become 8000h or more. 2. this register is also cl eared by reset effected by wr iting the second count register. 3. the value read from this register is not guar anteed if it is read du ring operation, because a value that is changing is read. figure 9-6. format of sub-count register (rsubc) address: ff60h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc7 subc6 subc5 subc4 subc3 subc2 subc1 subc0 address: ff61h after reset: 0000h r symbol 7 6 5 4 3 2 1 0 rsubc subc15 subc14 subc13 subc12 subc11 subc10 subc9 subc8 (6) second count register (sec) the sec register is an 8-bit register that takes a value of 0 to 59 (dec imal) and indicates the count value of seconds. it counts up when the sub-counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. sec can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-7. format of second count register (sec) address: ff62h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 sec 0 sec40 sec20 sec10 sec8 sec4 sec2 sec1 chapter 9 real-time counter user?s manual u18329ej4v0ud 319 (7) minute count register (min) the min register is an 8-bit register that takes a valu e of 0 to 59 (decimal) and indicates the count value of minutes. it counts up when the second counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 59 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. min can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-8. format of minute count register (min) address: ff63h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 min 0 min40 min20 min10 min8 min4 min2 min1 (8) hour count register (hour) the hour register is an 8-bit register that takes a va lue of 00 to 23 or 01 to 12, 21 to 32 (decimal) and indicates the count value of hours. it counts up when the minute counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 23 or 01 to 12, 21 to 32 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. hour can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit is set to 1 after reset. figure 9-9. format of hour count register (hour) address: ff64h after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 hour 0 0 hour20 hour10 ho ur8 hour4 hour2 hour1 caution bit 5 (hour20) of ho ur indicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected). chapter 9 real-time counter user?s manual u18329ej4v0ud 320 table 9-2 shows the relationship between the setting valu e of the ampm bit, the hour register value, and time. table 9-2. displayed time digits 24-hour display (ampm bit = 1) 12-hour display (ampm bit = 0) time hour register time hour register 0 00h 0 a.m. 12h 1 01h 1 a.m. 01h 2 02h 2 a.m. 02h 3 03h 3 a.m. 03h 4 04h 4 a.m. 04h 5 05h 5 a.m. 05h 6 06h 6 a.m. 06h 7 07h 7 a.m. 07h 8 08h 8 a.m. 08h 9 09h 9 a.m. 09h 10 10h 10 a.m. 10h 11 11h 11 a.m. 11h 12 12h 0 p.m. 32h 13 13h 1 p.m. 21h 14 14h 2 p.m. 22h 15 15h 3 p.m. 23h 16 16h 4 p.m. 24h 17 17h 5 p.m. 25h 18 18h 6 p.m. 26h 19 19h 7 p.m. 27h 20 20h 8 p.m. 28h 21 21h 9 p.m. 29h 22 22h 10 p.m. 30h 23 23h 11 p.m. 31h the hour register value is set to 12-hour display when the ampm bit is ?0? and to 24-hour display when the ampm bit is ?1?. in 12-hour display, the fifth bit of the ho ur register displays 0 for am and 1 for pm. chapter 9 real-time counter user?s manual u18329ej4v0ud 321 (9) day count register (day) the day register is an 8-bit register that takes a value of 1 to 31 (dec imal) and indicates the count value of days. it counts up when the hour counter overflows. this counter counts as follows. ? 01 to 31 (january, march, may, july, august, october, december) ? 01 to 30 (april, june, september, november) ? 01 to 29 (february, leap year) ? 01 to 28 (february, normal year) when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 01 to 31 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. day can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h. figure 9-10. format of day count register (day) address: ff66h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 day 0 0 day20 day10 day8 day4 day2 day1 chapter 9 real-time counter user?s manual u18329ej4v0ud 322 (10) week count register (week) the week register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. it counts up in synchronization with the day counter. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 06 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. week can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-11. format of week count register (week) address: ff65h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 week 0 0 0 0 0 week4 week2 week1 caution the value corresponding to th e month count register or the day count register is not stored in the week count register automatically. afte r reset release, set the week count register as follow. day week sunday 00h monday 01h tuesday 02h wednesday 03h thursday 04h friday 05h saturday 06h chapter 9 real-time counter user?s manual u18329ej4v0ud 323 (11) month count register (month) the month register is an 8-bit regist er that takes a value of 1 to 12 (decimal) and indicates the count value of months. it counts up when the day counter overflows. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 01 to 12 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. month can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 01h. figure 9-12. format of month count register (month) address: ff67h after reset: 01h r/w symbol 7 6 5 4 3 2 1 0 month 0 0 0 month10 month8 month4 month2 month1 (12) year count register (year) the year register is an 8-bit register that takes a value of 0 to 99 (dec imal) and indicates the count value of years. it counts up when the month counter overflows. values 00, 04, 08, ?, 92, and 96 indicate a leap year. when data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 khz) later. set a decimal value of 00 to 99 to this register in bcd code. if a value outside this range is set, the register value returns to the normal value after 1 period. year can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-13. format of year count register (year) address: ff68h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 year year80 year40 year20 year10 year8 year4 year2 year1 chapter 9 real-time counter user?s manual u18329ej4v0ud 324 (13) watch error correction register (subcud) this register is used to correct the watch with high a ccuracy when it is slow or fast by changing the value (reference value: 7fffh) that overflow s from the sub-count register (rsu bc) to the second count register. subcud can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-14. format of watch e rror correction register (subcud) address: ff82h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 subcud dev f6 f5 f4 f3 f2 f1 f0 dev setting of watch error correction timing 0 corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds). 1 corrects watch error only when the second digits are at 00 (every 60 seconds). f6 setting of watch error correction value 0 increases by {(f5, f4, f3, f2, f1, f0) ? 1} 2. 1 decreases by {(/f5, /f4, /f3, /f2, /f1, /f0) + 1} 2. when (f6, f5, f4, f3, f2, f1, f0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1. /f5 to /f0 are the inverted values of the corresponding bits (000011 when 111100). range of correction value: (when f6 = 0) 2, 4, 6, 8, ? , 120, 122, 124 (when f6 = 1) ?2, ?4, ?6, ?8, ? , ?120, ?122, ?124 the range of value that can be corre cted by using the watch error corre ction register (subcud) is shown below. dev = 0 (correction every 20 seconds) dev = 1 (correction every 60 seconds) correctable range ?189.2 ppm to 189.2 ppm ?63.1 ppm to 63.1 ppm maximum excludes quantization error 1.53 ppm 0.51 ppm minimum resolution 3.05 ppm 1.02 ppm remark set dev to 0 when the correction range is ? 63.1 ppm or less, or 63.1 ppm or more. chapter 9 real-time counter user?s manual u18329ej4v0ud 325 (14) alarm minute register (alarmwm) this register is used to set minutes of alarm. alarmwm can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. caution set a decimal value of 00 to 59 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 9-15. format of ala rm minute register (alarmwm) address: ff86h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmwm 0 wm40 wm20 wm10 wm8 wm4 wm2 wm1 (15) alarm hour register (alarmwh) this register is used to set hours of alarm. alarmwh can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 12h. however, the value of this register is 00h if the ampm bit is set to 1 after reset. caution set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in bcd code. if a value outside the range is set, the alarm is not detected. figure 9-16. format of alarm hour register (alarmwh) address: ff87h after reset: 12h r/w symbol 7 6 5 4 3 2 1 0 alarmwh 0 0 wh20 wh10 wh8 wh4 wh2 wh1 caution bit 5 (wh20) of alarmwh indicates am(0)/pm(1) if ampm = 0 (if the 12-hour system is selected). chapter 9 real-time counter user?s manual u18329ej4v0ud 326 (16) alarm week register (alarmww) this register is used to set date of alarm. alarmww can be set by an 8-bit memory manipulation instruction. reset signal generation clea rs this register to 00h. figure 9-17. format of alarm week register (alarmww) address: ff88h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 alarmww 0 ww6 ww5 ww4 ww3 ww2 ww1 ww0 here is an example of setting the alarm. day 12-hour display 24-hour display time of alarm sunday w w 0 monday w w 1 tuesday w w 2 wednesday w w 3 thursday w w 4 friday w w 5 saturday w w 6 hour 10 hour 1 minute 10 minute 1 hour 10 hour 1 minute 10 minute 1 every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 every day, 11:59 a.m. 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 monday through friday, 0:00 p.m. 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 sunday, 1:30 p.m. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 monday, wednesday, friday, 11:59 p.m. 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 chapter 9 real-time counter user?s manual u18329ej4v0ud 327 9.4 real-time counter operation 9.4.1 starting operation of real-time counter figure 9-18. procedure for starting operation of real-time counter setting rtccl setting min rtce = 0 setting sec (clearing rsubc) start intrtc = 1? stops counter operation. selects clock input of real-time counter (rtc). setting ampm, ct2 to ct0 selects 12-/24-hour system and interrupt (intrtc). sets second count register. sets minute count register. no yes setting hour sets hour count register. setting week sets week count register. setting day sets day count register. setting month sets month count register. setting year sets year count register. clearing if flags of interrupt clears interrupt request flags (rtcif, rtciif). clearing mk flags of interrupt clears interrupt mask flags (rtcmk, rtcimk). rtce = 1 note starts counter operation. reading counter note confirm the procedure described in 9.4.2 shifting to stop mode after starting operation when shifting to stop mode without waiting for intrtc = 1 after rtce = 1. chapter 9 real-time counter user?s manual u18329ej4v0ud 328 yes rtce = 1 rwait = 1 no yes rwait = 0 no rwst = 1 ? rwst = 0 ? stop mode rtce = 1 stop mode waiting at least for 2 f rtc clocks sets to counter operation start shifts to stop mode sets to counter operation start sets to stop the sec to year counters, reads the counter value, write mode checks the counter wait status sets the counter operation shifts to stop mode 9.4.2 shifting to stop mode after starting operation perform one of the following processing when shifting to stop mode immediately after setting rtce to 1. however, after setting rtce to 1, this processing is not required when shifting to stop mode after the first intrtc interrupt has occurred. ? shifting to stop mode when at least two input clocks (f rtc ) have elapsed after setting rtce to 1 (see figure 9- 19 , example 1 ). ? checking by polling rwst to become 1, after setting rtce to 1 and then setting rwait to 1. afterward, setting rwait to 0 and shifting to stop mode after checki ng again by polling that rwst has become 0 (see figure 9- 19 , example 2 ). figure 9-19. procedure for shifting to stop mode after setting rtce to 1 example 1 example 2 chapter 9 real-time counter user?s manual u18329ej4v0ud 329 9.4.3 reading/writing real-time counter read or write the counter after setting 1 to rwait first. figure 9-20. procedure for reading real-time counter reading min rwait = 1 reading sec start rwst = 1? stops sec to year counters. mode to read and write count values reads second count register. reads minute count register. no yes reading hour reads hour count register. reading week reads week count register. reading day reads day count register. reading month reads month count register. reading year reads year count register. rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, and year may be read in any sequence. all the registers do not have to be set and only some registers may be read. chapter 9 real-time counter user?s manual u18329ej4v0ud 330 figure 9-21. procedure for writing real-time counter writing min rwait = 1 writing sec start rwst = 1? stops sec to year counters. mode to read and write count values no yes writing hour writing week writing day writing month writing year rwait = 0 rwst = 0? note no yes sets counter operation. checks wait status of counter. end writes second count register. writes minute count register. writes hour count register. writes week count register. writes day count register. writes month count register. writes year count register. note be sure to confirm that rwst = 0 before setting stop mode. caution complete the series of opera tions of setting rwait to 1 to cl earing rwait to 0 within 1 second. remark sec, min, hour, week, day, month, a nd year may be written in any sequence. all the registers do not have to be set an d only some registers may be written. chapter 9 real-time counter user?s manual u18329ej4v0ud 331 9.4.4 setting alarm of real-time counter set time of alarm after setting 0 to wale first. figure 9-22. alarm setting procedure wale = 0 setting alarmwm start intrtc = 1? match operation of alarm is invalid. sets alarm minute register. alarm processing yes walie = 1 interrupt is generated when alarm matches. setting alarmwh sets alarm hour register. setting alarmww sets alarm week register. wale = 1 match operation of alarm is valid. wafg = 1? no yes constant-period interrupt servicing match detection of alarm no remarks 1. alarmwm, alarmwh, and alarmww may be written in any sequence. 2. fixed-cycle interrupts and alarm match interrupts us e the same interrupt s ource (intrtc). when using these two types of interrupts at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (rif g) and the alarm detection status flag (wafg) upon intrtc occurrence. chapter 9 real-time counter user?s manual u18329ej4v0ud 332 9.4.5 1 hz output of real-time counter set 1 hz output after setting 0 to rtce first. figure 9-23. 1 hz output setting procedure setting rtccl rtce = 0 rtce = 1 start stops counter operation. selects clock input of real-time counter (rtc). rcloe1 = 1 enables output of rtc1hz pin (1 hz). starts counter operation. output start from rtc1hz pin 9.4.6 32.768 khz output of real-time counter set 32.768 khz output after setting 0 to rtce first. figure 9-24. 32.768 khz output setting procedure setting rtccl rtce = 0 rtce = 1 start stops counter operation. selects clock input of real-time counter (rtc). rcloe0 = 1 enables output of rtccl pin (32.768 khz). starts counter operation. 32.768 khz output start from rtccl pin chapter 9 real-time counter user?s manual u18329ej4v0ud 333 9.4.7 512 hz, 16.384 khz output of real-time counter set 512 hz or 16.384 khz output after setting 0 to rtce first. figure 9-25. 512 hz, 16.384 khz output setting procedure setting rtccl rtce = 0 rtce = 1 start stops counter operation. selects clock input of real-time counter (rtc). rcloe2 = 1 output of rtcdiv pin is enabled. 512 hz output: rckdiv = 0 16.384 khz output: rckdiv = 1 selects output frequency of rtcdiv pin. starts counter operation. 512 hz or 16.384 khz output start from rtcdiv pin chapter 9 real-time counter user?s manual u18329ej4v0ud 334 9.4.8 example of watch error correction of real-time counter the watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. example of calculating the correction value the correction value used when correcting the count value of the sub-count register (rsubc) is calculated by using the following expression. set dev to 0 when the correction range is ? 63.1 ppm or less, or 63.1 ppm or more. (when dev = 0) correction value note = number of correction counts in 1 minute 3 = (oscillation frequency target frequency ? 1) 32768 60 3 (when dev = 1) correction value note = number of correction counts in 1 minute = (oscillation frequency target frequency ? 1) 32768 60 note the correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error correction regist er (subcud). (when f6 = 0) correction value = {(f5, f4, f3, f2, f1, f0) ? 1} 2 (when f6 = 1) correction value = ? {(/f5, /f4, /f3, /f 2, /f1, /f0) + 1} 2 when (f6, f5, f4, f3, f2, f1, f0) is (*, 0, 0, 0, 0, 0, *), watch error correction is not performed. ?*? is 0 or 1. /f5 to /f0 are bit-inverted values (000011 when 111100). remarks 1. the correction value is 2, 4, 6, 8, ? 120, 122, 124 or ? 2, ? 4, ? 6, ? 8, ? ? 120, ? 122, ? 124. 2. the oscillation frequency is the input clock (f rtc ) value of the real-time counter (rtc). it can be calculated from the 32 khz output frequency of the rtccl pin or the output frequency of the rtc1hz pin 32768 when the watch error correction register is set to its initial value (00h). 3. the target frequency is the frequency resulting a fter correction performed by using the watch error correction register. chapter 9 real-time counter user?s manual u18329ej4v0ud 335 correction example <1> example of correcting from 32772.3 hz to 32768 hz (32772.3 hz ? 131.2 ppm) [measuring the oscillation frequency] the oscillation frequency note of each product is measured by outputti ng about 32 khz from the rtccl pin or outputting about 1 hz from the rtc1hz pin when the watch erro r correction register is set to its initial value (00h). note see 9.4.5 1 hz output of real-time counter for the setting procedure of outputting about 1 hz from the rtc1hz pin, and 9.4.6 32.768 khz output of real-time counter for the setting procedure of outputting about 32 khz from the rtccl pin. [calculating the correction value] (when the output frequency from t he rtccl pin is 32772.3 hz) if the target frequency is assu med to be 32768 hz (32772.3 hz ? 131.2 ppm), the correction range for ? 131.2 ppm is ? 63.1 ppm or less, so assume dev to be 0. the expression for calculating the correct ion value when dev is 0 is applied. correction value = number of correction counts in 1 minute 3 = (oscillation frequency target frequency ? 1) 32768 60 3 = (32772.3 32768 ? 1) 32768 60 3 = 86 [calculating the values to be set to (f6 to f0)] (when the correction value is 86) if the correction value is 0 or more (w hen delaying), assume f6 to be 0. calculate (f5, f4, f3, f2, f1, f0) from the correction value. { (f5, f4, f3, f2, f1, f0) ? 1} 2 = 86 (f5, f4, f3, f2, f1, f0) = 44 (f5, f4, f3, f2, f1, f0) = (1, 0, 1, 1, 0, 0) consequently, when correcting from 32 772.3 hz to 32768 hz (32772.3 hz ? 131.2 ppm), setting the correction register such that dev is 0 and the correction value is 86 (bits 6 to 0 of subcud: 0101100) results in 32768 hz (0 ppm). figure 9-26 shows the operation when (dev, f6, f5, f4, f3, f2, f1, f0) is (0, 0, 1, 0, 1, 1, 0, 0). chapter 9 real-time counter user?s manual u18329ej4v0ud 336 figure 9-26. operation when (dev, f6, f5, f4, f3 , f2, f1, f0) = (0, 0, 1, 0, 1, 1, 0, 0) rsubc count value sec 00 01 8055h 0000h 0001h 7fffh 0000h 8054h 40 8055h 0000h 8054h 8055h 0000h 8054h 19 0000h 0001h 7fffh 20 39 0000h 0001h 7fffh 0000h 0001h 7fffh 59 00 8055h 0000h 8054h 7fffh + 56h (86) 7fffh + 56h (86) 7fffh + 56h (86) 7fffh+56h (86) count start chapter 9 real-time counter user?s manual u18329ej4v0ud 337 correction example <2> example of correcting from 32767.4 hz to 32768 hz (32767.4 hz + 18.3 ppm) [measuring the oscillation frequency] the oscillation frequency note of each product is measured by outputti ng about 32 khz from the rtccl pin or outputting about 1 hz from the rtc1hz pin when the watch erro r correction register is set to its initial value (00h). note see 9.4.5 1 hz output of real-time counter for the setting procedure of outputting about 1 hz from the rtc1hz pin, and 9.4.6 32.768 khz output of real-time counter for the setting procedure of outputting about 32 khz from the rtccl pin. [calculating the correction value] (when the output frequency from t he rtccl pin is 0.9999817 hz) oscillation frequency = 32768 0.9999817 32767.4 hz assume the target frequency to be 32768 hz (32767.4 hz + 18.3 ppm) and dev to be 1. the expression for calculating the correct ion value when dev is 1 is applied. correction value = number of correction counts in 1 minute = (oscillation frequency target frequency ? 1) 32768 60 = (32767.4 32768 ? 1) 32768 60 = ? 36 [calculating the values to be set to (f6 to f0)] (when the correction value is ? 36) if the correction value is 0 or less (when speeding up), assume f6 to be 1. calculate (f5, f4, f3, f2, f1, f0) from the correction value. ? {(/f5, /f4, /f3, /f2, /f1, /f0) + 1} 2 = ? 36 (/f5, /f4, /f3, /f2, /f1, /f0) = 17 (/f5, /f4, /f3, /f2, /f1, /f0) = (0, 1, 0, 0, 0, 1) (f5, f4, f3, f2, f1, f0) = (1, 0, 1, 1, 1, 0) consequently, when correcting from 32767.4 hz to 327 68 hz (32767.4 hz + 18.3 ppm), setting the correction register such that dev is 1 and the correction value is ? 36 (bits 6 to 0 of subcud: 1101110) results in 32768 hz (0 ppm). figure 9-27 shows the operation when (dev, f6, f5, f4, f3, f2, f1, f0) is (1, 1, 1, 0, 1, 1, 1, 0). chapter 9 real-time counter user?s manual u18329ej4v0ud 338 figure 9-27. operation when (dev, f6, f5, f4, f3 , f2, f1, f0) = (1, 1, 1, 0, 1, 1, 1, 0) rsubc count value sec 00 01 7fdbh 0000h 0001h 7fffh 0000h 7fdah 40 19 0000h 0001h 7fffh 0000h 0001h 7fffh 20 39 0000h 0001h 7fffh 0000h 0001h 7fffh 0000h 0001h 7fffh 59 00 7fdbh 0000h 7fdah 7fffh ? 24h (36) 7fffh ? 24h (36) count start user?s manual u18329ej4v0ud 339 chapter 10 watchdog timer 10.1 functions of watchdog timer the watchdog timer operates on the internal low-speed oscillation clock. the watchdog timer is used to detect an inadvertent program loop. if a program loop is detected, an internal reset signal is generated. program loop is detected in the following cases. ? if the watchdog timer counter overflows ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if data is written to wdte during a window close period ? if the instruction is fetched from an area not set by the ims and ixs registers (detection of an invalid check while the cpu hangs up) ? if the cpu accesses an area that is not set by t he ims and ixs registers (excluding fb00h to ffffh) by executing a read/write instruct ion (detection of an abnormal access during a cpu program loop) when a reset occurs due to the watchdog timer, bit 4 (wdtrf) of the reset control flag register (resf) is set to 1. for details of resf, see chapter 24 reset function . chapter 10 watchdog timer user?s manual u18329ej4v0ud 340 10.2 configuration of watchdog timer the watchdog timer includes the following hardware. table 10-1. configuration of watchdog timer item configuration control register watchdog timer enable register (wdte) how the counter operation is controlled, overflow ti me, and window open period are set by the option byte. table 10-2. setting of op tion bytes and watchdog timer setting of watchdog timer option byte (0080h) window open period bits 6 and 5 (window1, window0) controlling counter operation of watchdog timer bit 4 (wdton) overflow time of watchdog timer bits 3 to 1 (wdcs2 to wdcs0) remark for the option byte, see chapter 27 option byte . figure 10-1. block diag ram of watchdog timer f rl /2 clock input controller reset output controller internal reset signal internal bus selector 17-bit counter 2 10 /f rl to 2 17 /f rl watchdog timer enable register (wdte) clear, reset control wdton of option byte (0080h) window1 and window0 of option byte (0080h) count clear signal wdcs2 to wdcs0 of option byte (0080h) overflow signal cpu access signal cpu access error detector window size determination signal chapter 10 watchdog timer user?s manual u18329ej4v0ud 341 10.3 register controlling watchdog timer the watchdog timer is controlled by the watchdog timer enable register (wdte). (1) watchdog timer enable register (wdte) writing ach to wdte clears the watchdog timer counter and starts counting again. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 9ah or 1ah note . figure 10-2. format of watchdog timer enable register (wdte) 0 1 2 3 4 5 6 7 symbol wdte address: ff99h after reset: 9ah/1ah note r/w note the wdte reset value differs depending on the wdto n setting value of the option byte (0080h). to operate watchdog timer, set wdton to 1. wdton setting value wdte reset value 0 (watchdog timer count operation disabled) 1ah 1 (watchdog timer count operation enabled) 9ah cautions 1. if a value other than ach is written to wdte, an internal reset signal is generated. if the source clock to the watchdog timer is stopped, however, an internal reset signal is generated when the source clock to the watchdog timer resumes operation. 2. if a 1-bit memory manipulation instructio n is executed for wdte, an internal reset signal is generated. if the source clock to the wa tchdog timer is stopped, however, an internal reset signal is genera ted when the source clock to th e watchdog timer resumes operation. 3. the value read from wdte is 9ah/1ah (this differs fr om the written value (ach)). chapter 10 watchdog timer user?s manual u18329ej4v0ud 342 10.4 operation of watchdog timer 10.4.1 controlling operation of watchdog timer 1. when the watchdog timer is used, its operati on is specified by the option byte (0080h). ? enable counting operation of the watchdog timer by se tting bit 4 (wdton) of the option byte (0080h) to 1 (the counter starts operating after a reset release) (for details, see chapter 27 ). wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped after rese t), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled ? set an overflow time by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h) (for details, see 10.4.2 and chapter 27 ). ? set a window open period by using bits 6 and 5 (wi ndow1 and window0) of the opt ion byte (0080h) (for details, see 10.4.3 and chapter 27 ). 2. after a reset release, the watchdog timer starts counting. 3. by writing ?ach? to wdte after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cl eared and starts counting again. 4. after that, write wdte the second time or later afte r a reset release during the window open period. if wdte is written during a window close period, an internal reset signal is generated. 5. if the overflow time expires without ?ach? wri tten to wdte, an internal reset signal is generated. a internal reset signal is generated in the following cases. ? if a 1-bit manipulation instruction is execut ed on the watchdog timer enable register (wdte) ? if data other than ?ach? is written to wdte ? if the instruction is fetched from an area not set by the ims and ixs registers (det ection of an invalid check during a cpu program loop) ? if the cpu accesses an area not set by the ims and ixs registers (excluding fb00h to ffffh) by executing a read/write instruction (det ection of an abnormal access during a cpu program loop) cautions 1. the first writing to wdte after a reset releas e clears the watchdog timer, if it is made before the overflow time regardless of the timing of the writing, and the watchdog timer starts counting again. 2. if the watchdog timer is cleared by writi ng ?ach? to wdte, the actual overflow time may be different from the overflow time set by the option byte by up to 2/f rl seconds. 3. the watchdog timer can be cleared immediately before the count value overflows (ffffh). chapter 10 watchdog timer user?s manual u18329ej4v0ud 343 cautions 4. the operation of the watchdog time r in the halt and stop modes differs as follows depending on the set value of bit 0 (lsrosc) of the option byte. lsrosc = 0 (internal low-speed oscillator can be stopped by software) lsrosc = 1 (internal low-speed oscillator cannot be stopped) in halt mode in stop mode watchdog timer operation stops. watchdog timer operation continues. if lsrosc = 0, the watchdog timer resu mes counting after the halt or stop mode is released. at this time, the counter is not clear ed to 0 but starts counting from the value at which it was stopped. if oscillation of the internal low-speed osc illator is stopped by setting lsrstop (bit 1 of the internal oscillation mode register (rcm) = 1) when lsrosc = 0, the watchdog timer stops operating. at this time, the counter is not cleared to 0. 5. the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow ti me and window size taking this delay into consideration. 10.4.2 setting overflow time of watchdog timer set the overflow time of the watchdog timer by using bits 3 to 1 (wdcs2 to wdcs0) of the option byte (0080h). if an overflow occurs, an internal reset signal is generat ed. the present count is cleared and the watchdog timer starts counting again by writing ?ach? to wdte dur ing the window open period before the overflow time. the following overflow time is set. table 10-3. setting of over flow time of watchdog timer wdcs2 wdcs1 wdcs0 overflow time of watchdog timer 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its operation durin g self-programming and eeprom emulation of the flash memo ry. during processing, th e interrupt acknowledge time is delayed. set the overflow time a nd window size taking this delay into consideration. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.) chapter 10 watchdog timer user?s manual u18329ej4v0ud 344 10.4.3 setting window open period of watchdog timer set the window open period of the watchdog timer by usi ng bits 6 and 5 (window1, window0) of the option byte (0080h). the outline of the window is as follows. ? if ?ach? is written to wdte during the window open per iod, the watchdog timer is cleared and starts counting again. ? even if ?ach? is written to wdte during the window cl ose period, an abnormality is detected and an internal reset signal is generated. example : if the window open period is 25% window close period (75%) window open period (25%) counting starts overflow time counting starts again when "ach" is written to wdte. internal reset signal is generated if "ach" is written to wdte. caution the first writing to wdte after a reset release clears the watchdog timer, if it is made before the overflow time regardless of the timing of th e writing, and the watc hdog timer starts counting again. the window open period to be set is as follows. table 10-4. setting window open period of watchdog timer window1 window0 window open period of watchdog timer 0 0 25% 0 1 50% 1 0 75% 1 1 100% cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its operation durin g self-programming and eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow time a nd window size taking this delay into consideration. chapter 10 watchdog timer user?s manual u18329ej4v0ud 345 remark if the overflow time is set to 2 10 /f rl , the window close time and open time are as follows. (2.6 v v dd 5.5 v) setting of window open period 25% 50% 75% 100% window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 1.19 ms none window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 1.19 to 3.88 ms 0 to 3.88 ms user?s manual u18329ej4v0ud 346 chapter 11 clock output/buzzer output controller 11.1 functions of clock output/buzzer output controller the clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ics. the clock selected with t he clock output selection register (cks) is output. in addition, the buzzer output is intended for square- wave output of buzzer frequency selected with cks. figure 11-1 shows the block diagram of clock output/buzzer output controller. figure 11-1. block diagram of clo ck output/buzzer output controller f prs f prs /2 10 to f prs /2 13 f prs to f prs /2 7 f sub bzoe bcs1 bcs0 cloe cloe bzoe 84 pcl/p10 buz/p33/ti000/rtcdiv /rtccl/intp2 bcs0, bcs1 clock controller prescaler internal bus ccs3 clock output selection register (cks) ccs2 ccs1 ccs0 output latch (p33) pm33 output latch (p10) pm10 selector selector chapter 11 clock output/buzzer output controller user?s manual u18329ej4v0ud 347 11.2 configuration of clock output/buzzer output controller the clock output/buzzer output controller includes the following hardware. table 11-1. configuration of clock output/buzzer output controller item configuration control registers clock output selection register (cks) port mode register 3 (pm3) port register 3 (p3) port mode register 1 (pm1) port register 1 (p1) 11.3 registers controlling clock output/buzzer output controller the following two registers are used to control the clock output/buzzer output controller. ? clock output selection register (cks) ? port mode register 3 (pm3) ? port mode register 1 (pm1) (1) clock output selection register (cks) this register sets output enable/disable for clock out put (pcl) and for the buzzer frequency output (buz), and sets the output clock. cks is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears cks to 00h. chapter 11 clock output/buzzer output controller user?s manual u18329ej4v0ud 348 figure 11-2. format of clock out put selection register (cks) address: ff40h after reset: 00h r/w symbol <7> 6 5 <4> 3 2 1 0 cks bzoe bcs1 bcs0 cloe ccs3 ccs2 ccs1 ccs0 bzoe buz output enable/disable specification 0 clock division circui t operation stopped. buz fixed to low level. 1 clock division ci rcuit operation enabled. buz output enabled. buz output clock selection bcs1 bcs0 f prs = 5 mhz f prs = 10 mhz 0 0 f prs /2 10 4.88 khz 9.77 khz 0 1 f prs /2 11 2.44 khz 4.88 khz 1 0 f prs /2 12 1.22 khz 2.44 khz 1 1 f prs /2 13 0.61 khz 1.22 khz cloe pcl output enable/disable specification 0 clock division circui t operation stopped. pcl fixed to low level. 1 clock division ci rcuit operation enabled. pcl output enabled. pcl output clock selection note 1 ccs3 ccs2 ccs1 ccs0 f sub = 32.768 khz f prs = 5 mhz f prs = 10 mhz 0 0 0 0 f prs note 2 5 mhz 10 mhz 0 0 0 1 f prs /2 2.5 mhz 5 mhz 0 0 1 0 f prs /2 2 1.25 mhz 2.5 mhz 0 0 1 1 f prs /2 3 625 khz 1.25 mhz 0 1 0 0 f prs /2 4 312.5 khz 625 khz 0 1 0 1 f prs /2 5 156.25 khz 312.5 khz 0 1 1 0 f prs /2 6 78.125 khz 156.25 khz 0 1 1 1 f prs /2 7 ? 39.062 khz 78.125 khz 1 0 0 0 f sub 32.768 khz ? other than above setting prohibited notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of ccs3 = ccs2 = ccs1 = ccs0 = 0 (output clock of pcl: f prs ) is prohibited. cautions 1. set bcs1 and bcs0 when the bu zzer output operation is stopped (bzoe = 0). 2. set ccs3 to ccs0 while the clock output operation is stopped (cloe = 0). remarks 1. f prs : peripheral hardware clock frequency 2. f sub : subsystem clock frequency chapter 11 clock output/buzzer output controller user?s manual u18329ej4v0ud 349 (2) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p33/ti000/rtcdiv/rt ccl/buz/intp2 pin for buzzer output, clear pm33 and the output latches of p33 to 0. pm3 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm3 to ffh. figure 11-3. format of port mode register 3 (pm3) address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) (3) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p10/pcl pin for clock output, clear pm10 and the output latches of p10 to 0. pm1 is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm1 to ffh. figure 11-4. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 11 clock output/buzzer output controller user?s manual u18329ej4v0ud 350 11.4 operations of clock output/buzzer output controller 11.4.1 operation as clock output the clock pulse is output as the following procedure. <1> select the clock pulse output frequency with bits 0 to 3 (ccs0 to ccs3) of the clock output selection register (cks) (clock pulse output in disabled status). <2> set bit 4 (cloe) of cks to 1 to enable clock output. remark the clock output controller is designed not to output pulses with a small width during output enable/disable switching of the clock output. as show n in figure 11-5, be sure to start output from the low period of the clock (marked with * in the figure) . when stopping output, do so after the high-level period of the clock. figure 11-5. remote control output application example cloe clock output ** 11.4.2 operation as buzzer output the buzzer frequency is output as the following procedure. <1> select the buzzer output frequency with bits 5 and 6 (b cs0, bcs1) of the clock output selection register (cks) (buzzer output in disabled status). <2> set bit 7 (bzoe) of cks to 1 to enable buzzer output. user?s manual u18329ej4v0ud 351 chapter 12 10-bit successive appr oximation type a/d converter ( pd78f048x and 78f049x only) 12.1 function of 10-bit successive a pproximation type a/d converter the 10-bit successive approximation type a/d converter co nverts an analog input signal into a digital value, and consists of up to eight channels (ani0 to ani7) with a resolution of 10 bits. the a/d converter has the following function. ? 10-bit resolution a/d conversion 10-bit resolution a/d conversion is carried out repeatedly for one analog input channel selected from ani0 to ani7. each time an a/d conversion operation en ds, an interrupt request (intad) is generated. figure 12-1. block diagram of 10-bit successive approximation type a/d converter av ref av ss intad adcs bit sample & hold circuit av ss voltage comparator a/d converter mode register (adm) internal bus 3 ads2 ads1 ads0 analog input channel specification register (ads) ani0/p20 ani1/p21 ani2/p22 ani3/p23 ani4/p24 ani5/p25 ani6/p26 ani7/p27 controller a/d conversion result register (adcr) successive approximation register (sar) a/d port configuration register 0 (adpc0) adpc03 adpc02 adpc01 adpc00 4 selector tap selector adcs fr2 fr3 fr1 adce fr0 lv1 lv0 6 chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 352 12.2 configuration of 10-bit successive approximation type a/d converter the 10-bit successive approximation type a/d converter includes the following hardware. (1) ani0 to ani7 pins these are the 8-channel analog input pins of the 10-bit succ essive approximation type a/ d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin can be used as i/o port pins or segment output pins ( pd78f048x only). (2) sample & hold circuit the sample & hold circuit samples the input voltage of the analog input pin selected by the selector when a/d conversion is started, and holds the samp led voltage value during a/d conversion. (3) series resistor string the series resistor stri ng is connected between av ref and av ss , and generates a voltage to be compared with the sampled voltage value. figure 12-2. circuit configuration of series resistor string adcs series resistor string av ref p-ch av ss (4) voltage comparator the voltage comparator compares the sampled voltage value and the output volt age of the series resistor string. (5) successive approximation register (sar) this register converts the result of comparison by the voltage comparator, starting from the most significant bit (msb). when the voltage value is converted into a digital valu e down to the least significant bit (lsb) (end of a/d conversion), the contents of the sar register are transfe rred to the a/d conversion result register (adcr). (6) 10-bit a/d conversion r esult register (adcr) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcr re gister holds the a/d conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 353 (7) 8-bit a/d conversion result register (adcrh) the a/d conversion result is loaded from the successive approximation register to th is register each time a/d conversion is completed, and the adcrh register stores the higher 8 bi ts of the a/d conversion result. caution when data is read from adcr and adcrh, a wa it cycle is generated. do not read data from adcr and adcrh when the cpu is operating on the subsystem clock and the peripheral hardware clock is stopped. for de tails, see chapter 34 cautions for wait. (8) controller this circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of t he conversion operation. when a/d c onversion has been completed, this controller generates intad. (9) av ref pin this pin inputs an analog power/referenc e voltage to the a/d converter. when using at least one port of port 2 as a digital port or for segment output, se t it to the same potential as the v dd pin. the signal input to ani0 to ani7 is converted into a digital signal, based on the voltage applied across av ref and av ss . (10) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. (11) a/d converter mode register (adm) this register is used to set the conver sion time of the analog input signal to be converted, and to start or stop the conversion operation. (12) a/d port configuration register 0 (adpc0) this register switches the ani0/p20 to ani7 /p27 pins to analog input (analog input of 16-bit ? type a/d converter or analog input of 10-bit successive approx imation type a/d converter) or digital i/o of port. (13) analog input channel sp ecification register (ads) this register is used to specify the port that inputs the analog voltage to be converted into a digital signal. (14) port mode register 2 (pm2) this register switches the ani0/p20 to ani7/p27 pins to input or output. (15) port function register 2 (pf2) ( pd78f048x only) this register switches the ani0/p20 to ani7/p27 pins to i/o of port, analog input of a/d converter, or segment output. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 354 12.3 registers used in 10-bit success ive approximation type a/d converter the a/d converter uses the following seven registers. ? a/d converter mode register (adm) ? a/d port configuration register 0 (adpc0) ? analog input channel specification register (ads) ? port function register 2 (pf2) ( pd78f048x only) ? port mode register 2 (pm2) ? 10-bit a/d conversion result register (adcr) ? 8-bit a/d conversion result register (adcrh) (1) a/d converter mode register (adm) this register sets the conversion time for analog inpu t to be a/d converted, and starts/stops conversion. adm can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 12-3. format of a/d converter mode register (adm) adce lv0 note 1 lv1 note 1 fr0 note 1 fr1 note 1 fr2 note 1 fr3 note 1 adcs a/d conversion operation control stops conversion operation enables conversion operation adcs 0 1 <0> 1 2 3 4 5 6 <7> adm address: ff8dh after reset: 00h r/w symbol comparator operation control note 2 stops comparator operation enables comparator operation adce 0 1 notes 1. for details of fr3 to fr0, lv 1, lv0, and a/d conversion, see table 12-2 a/d conversion time selection . 2. the operation of the compar ator is controlled by adcs and adce, and it takes 1 s from operation start to operation stabilization. theref ore, when adcs is set to 1 after 1 s or more has elapsed from the time adce is set to 1, the conversion result at that time has priority over the first conversion result. otherwise, ignore data of the first conversion. table 12-1. settings of adcs and adce adcs adce a/d co nversion operation 0 0 stop status (dc power consumption path does not exist) 0 1 conversion waiting mode (comparator oper ation, only comparator consumes power) 1 0 conversion mode (comparator operation stopped note ) 1 1 conversion mode (comparator operation) note ignore data of the first conversion. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 355 figure 12-4. timing chart wh en comparator is used adce comparator adcs conversion operation conversion operation conversion stopped conversion waiting comparator operation note note to stabilize the internal circuit, the time from the rising of the adce bit to the falling of the adcs bit must be 1 s or longer. cautions 1. a/d conversion must be stopped before re writing bits fr0 to fr3, lv1, and lv0 to values other than the identical data. 2. if data is written to adm, a wait cycle is generated. do not write data to adm when the cpu is operating on the subsystem clock and the periphera l hardware clock is stopped. for details, see chapter 34 cautions for wait. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 356 table 12-2. a/d conversion time selection (1) 2.7 v av ref 5.5 v a/d converter mode register (adm) conversion time selection fr3 fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 8 mhz f prs = 10 mhz conversion clock (f ad ) 1 0 0 352/f prs 44.0 s 35.2 s f prs /16 0 0 0 0 0 0 264/f prs 33.0 s 26.4 s f prs /12 0 0 0 1 0 0 176/f prs 22.0 s 17.6 s f prs /8 0 0 1 0 0 0 132/f prs setting prohibited 16.5 s 13.2 s f prs /6 0 0 1 1 0 0 88/f prs 44.0 s 11.0 s note 8.8 s note f prs /4 0 1 0 0 0 0 66/f prs 33.0 s 8.3 s note 6.6 s note f prs /3 0 1 0 1 0 0 44/f prs 22.0 s setting prohibited setting prohibited f prs /2 other than above setting prohibited note this can be set only when 4.0 v av ref 5.5 v. (2) 2.3 v av ref < 2.7 v a/d converter mode register (adm) conversion time selection fr3 fr2 fr1 fr0 lv1 lv0 f prs = 2 mhz f prs = 5 mhz f prs = 8 mhz conversion clock (f ad ) 0 0 0 0 0 1 480/f prs setting prohibited 60.0 s f prs /12 0 0 0 1 0 1 320/f prs 64.0 s 40.0 s f prs /8 0 0 1 0 0 1 240/f prs 48.0 s 30.0 s f prs /6 0 0 1 1 0 1 160/f prs setting prohibited 32.0 s f prs /4 0 1 0 0 0 1 120/f prs 60.0 s f prs /3 0 1 0 1 0 1 80/f prs 40.0 s setting prohibited setting prohibited f prs /2 other than above setting prohibited cautions 1. set the conversion ti mes with the following conditions. ? 4.0 v av ref 5.5 v: f ad = 0.6 to 3.6 mhz ? 2.7 v av ref < 4.0 v: f ad = 0.6 to 1.8 mhz ? 2.3 v av ref < 2.7 v: f ad = 0.6 to 1.48 mhz 2. when rewriting fr3 to fr0, lv1, and lv0 to other than the same data, stop a/d conversion once (adcs = 0) beforehand. 3. change lv1 and lv0 from the default value, when 2.3 v av ref < 2.7 v. 4. the above conversion time do es not include clock frequency e rrors. select conversion time, taking clock frequency erro rs into consideration. remark f prs : peripheral hardware clock frequency chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 357 figure 12-5. a/d converter sa mpling and a/d conversion timing adcs wait period note conversion time conversion time sampling sampling timing intad adcs 1 or ads rewrite sampling sar clear sar clear transfer to adcr, intad generation successive conversion note for details of wait period, see chapter 34 cautions for wait . (2) 10-bit a/d conversion r esult register (adcr) this register is a 16-bit register that stores the a/d conversion result. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion result is loaded from the successive approximation register. the higher 8 bits of the conversion result are stor ed in ff07h and the lower 2 bits are st ored in the higher 2 bits of ff06h. adcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 12-6. format of 10-bit a/d conversion result register (adcr) symbol address: ff06h, ff07h after reset: 0000h r ff07h ff06h 0 0 0 0 0 0 adcr cautions 1. when writing to the a/d converter mode register (adm), analog input ch annel specification register (ads), and a/d port configuration re gister 0 (adpc0), the contents of adcr may become undefined. read the conversion resu lt following conversion completion before writing to adm, ads, and adpc0. using timing other than the above m ay cause an incorrect conversion result to be read. 2. if data is read from adcr, a wait cycle is ge nerated. do not read data from adcr when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 34 cautions for wait. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 358 (3) 8-bit a/d conversion result register (adcrh) this register is an 8-bit register that stores the a/d conversion result. the higher 8 bits of 10-bit resolution are stored. adcrh can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 12-7. format of 8-bit a/d c onversion result register (adcrh) symbol adcrh address: ff07h after reset: 00h r 76543210 cautions 1. when writing to the a/d converter mode register (adm), analog input ch annel specification register (ads), and a/d port configuration register 0 (adpc0), the contents of adcrh may become undefined. read the conversion resu lt following conversion completion before writing to adm, ads, and adpc0. using timing other than the above m ay cause an incorrect conversion result to be read. 2. if data is read from adcrh, a wait cycle is generated. do not r ead data from adcrh when the cpu is operating on the subsystem clock a nd the peripheral hardware clock is stopped. for details, see chapter 34 cautions for wait. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 359 (4) analog input channel specification register (ads) this register specifies the input channel of the analog voltage to be a/d converted. ads can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 12-8. format of analog input channel specification register (ads) ads0 ads1 ads2 0 0 0 0 0 analog input channel specification ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads0 0 1 0 1 0 1 0 1 ads1 0 0 1 1 0 0 1 1 ads2 0 0 0 0 1 1 1 1 0 1 2 3 4 5 6 7 ads address: ff8eh after reset: 00h r/w symbol cautions 1. be sure to cl ear bits 3 to 7 to ?0?. 2. set a channel to be used for a/d conversion in the input mode by us ing port mode register 2 (pm2). 3. do not set a pin to be used as a digital i/o pin with adpc with ads. 4. a pin whose channel h as been selected as a 10-bit su ccessive approximation type a/d converter input must not be selected as a 16-bit ? type a/d converter input. 5. if data is written to ads, a wait cycle is generated. do not wr ite data to ads when the cpu is operating on the subsystem clock and the periphera l hardware clock is stopped. for details, see chapter 34 cautions for wait. (5) a/d port configurati on register 0 (adpc0) this register switches the ani0/p20 to ani7 /p27 pins to analog input (analog input of 16-bit ? type a/d converter or analog input of 10-bit successive approx imation type a/d converter) or digital i/o of port. adpc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 08h. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 360 figure 12-9. format of a/d port configuration register 0 (adpc0) adpc00 adpc01 adpc02 adpc03 0 0 0 0 digital i/o (d)/analog input (a) switching setting prohibited adpc03 0 1 2 3 4 5 6 7 adpc0 address: ff8fh after reset: 08h r/w < pd78f048x> symbol p27/ ani7/ seg32 a a a a a a a a d p26/ ani6/ seg33 a a a a a a a d d p25/ ani5/ seg34 a a a a a a d d d p24/ ani4/ seg35 a a a a a d d d d p23/ ani3/ seg36 a a a a d d d d d p22/ ani2/ seg37 a a a d d d d d d p21/ ani1/ seg38 a a d d d d d d d p20/ ani0/ seg39 a d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc02 0 0 0 0 1 1 1 1 0 adpc01 0 0 1 1 0 0 1 1 0 adpc00 0 1 0 1 0 1 0 1 0 other than above digital i/o (d)/analog input (a: successive setting prohibited adpc03 < pd78f049x> p27/ ani7/ ref+ a/ a/ a/ a/ a/ a a a d p26/ ani6/ ref- a/ a/ a/ a/ a/ a a d d p25/ ani5/ ds2+ a/ a/ a/ a/ a/ a d d d p24/ ani4/ ds2- a/ a/ a/ a/ a/ d d d d p23/ ani3/ ds1+ a/ a/ a/ a d d d d d p22/ ani2/ ds1- a/ a/ a/ d d d d d d p21/ ani1/ ds0+ a/ a d d d d d d d p20/ ani0/ ds0- a/ d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc02 0 0 0 0 1 1 1 1 0 adpc01 0 0 1 1 0 0 1 1 0 adpc00 0 1 0 1 0 1 0 1 0 other than above approximation type, : ? type) switching cautions 1. set the channel used for a/d conversion to the input mode by using port mode register 2 (pm2). 2. do not set the pin set by adpc0 as digital i/o by ads, adds1, or adds0. 3. if data is written to adpc0, a wait cycle is generated. do not write data to adpc0 when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 34 cautions for wait. 4. if pins ani0/p20/seg39 to ani7/p27/seg32 are set to seg ment output pins via the pf2 register, output is set to segment outpu t, regardless of the adpc0 setting (for pd78f048x only). chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 361 (6) port mode register 2 (pm2) when using the ani0/p20 to ani7/p27 pins for analog input port, set pm20 to pm27 to 1. the output latches of p20 to p27 at this time may be 0 or 1. if pm20 to pm27 are set to 0, they cannot be used as analog input port pins. pm2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 12-10. format of port mode register 2 (pm2) pm20 pm21 pm22 pm23 pm24 pm25 pm26 pm27 p2n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm2n 0 1 0 1 2 3 4 5 6 7 pm2 address: ff22h after reset: ffh r/w symbol ani0/p20 to ani7/p27 pins are as shown below depend ing on the settings of pf2, adpc0, pm2, ads, and addctl0. table 12-3. setting functions of p20/ani0 to p27/ani7 pins (a) pd78f048x pf2 adpc0 pm2 ads p20/seg39/ani0 to p27/seg32/ani7 pins does not select ani. analog input (not to be converted) input mode selects ani. analog input (to be converted by successive approximation type a/d converter) analog input selection output mode ? setting prohibited input mode ? digital input digital/analog selection digital i/o selection output mode ? digital output seg output selection ? ? ? segment output (b) pd78f049x adpc0 pm2 ads addctl0 p20/ani0/ds0- to p27/ani7/ref+ pins does not select ani. does not select dsn . analog input (not to be converted) selects ani. does not select dsn . analog input (to be converted by successive approximation type a/d converter) does not select ani. selects dsn . analog input (to be converted by ? type a/d converter) input mode selects ani. selects dsn . setting prohibited analog input selection output mode ? setting prohibited input mode ? digital input digital i/o selection output mode ? digital output chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 362 12.4 10-bit successive approximati on type a/d converter operations 12.4.1 basic operations of a/d converter <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1 to start the operation of the comparator. <2> set channels for a/d conversion to analog input by usi ng the a/d port configuration register (adpc0) and set to input mode by using port mode register 2 (pm2). <3> set a/d conversion time by using bits 6 to 1 (fr3 to fr0, lv1, and lv0) of adm. <4> select one channel for a/d conversion using the analog input channel specification register (ads). <5> start the conversion operation by setting bit 7 (adcs) of adm to 1. (<6> to <12> are operations performed by hardware.) <6> the voltage input to the selected analog input c hannel is sampled by the sample & hold circuit. <7> when sampling has been done for a certain time, the sa mple & hold circuit is placed in the hold state and the sampled voltage is held until the a/ d conversion operation has ended. <8> bit 9 of the successive approximation register (sar) is set. the series resistor string voltage tap is set to (1/2) av ref by the tap selector. <9> the voltage difference between the series resistor st ring voltage tap and sampled voltage is compared by the voltage comparator. if the analog input is greater than (1/2) av ref , the msb of sar remains set to 1. if the analog input is smaller than (1/2) av ref , the msb is reset to 0. <10> next, bit 8 of sar is automatically set to 1, and t he operation proceeds to the next comparison. the series resistor string voltage tap is selected according to the preset value of bit 9, as described below. ? bit 9 = 1: (3/4) av ref ? bit 9 = 0: (1/4) av ref the voltage tap and sampled voltage are compared and bit 8 of sar is manipulated as follows. ? analog input voltage voltage tap: bit 8 = 1 ? analog input voltage < voltage tap: bit 8 = 0 <11> comparison is continued in this way up to bit 0 of sar. <12> upon completion of the comparison of 10 bits, an effective digital result value remains in sar, and the result value is transferred to the a/d conversion resu lt register (adcr, adcrh) and then latched. at the same time, the a/d conversion end in terrupt request (intad) can also be generated. <13> repeat steps <6> to <12>, until adcs is cleared to 0. to stop the a/d converter, clear adcs to 0. to restart a/d conversion from the st atus of adce = 1, start from <5>. to start a/d conversion again when adce = 0, set adce to 1, wait for 1 s or longer, and start <5>. to change a channel of a/d conversion, start from <4>. caution make sure the period of <1> to <5> is 1 s or more. remark two types of a/d conversion re sult registers are available. ? adcr (16 bits): store 10-bit a/d conversion value ? adcrh (8 bits): store 8-bit a/d conversion value chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 363 figure 12-11. basic operation of a/d converter conversion time sampling time sampling a/d conversion undefined conversion result a/d converter operation sar adcr intad conversion result a/d conversion operations are performed continuously until bit 7 (adcs) of t he a/d converter mode register (adm) is reset (0) by software. if a write operation is performed to the analog input chan nel specification register (ads) during an a/d conversion operation, the conversion operation is in itialized, and if the adcs bit is set (1), conversion starts again from the beginning. reset signal generation clears the a/d conversion re sult register (adcr, adcrh) to 0000h or 00h. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 364 12.4.2 input voltage and conversion results the relationship between the analog input voltage input to the analog input pins (ani0 to ani7) and the theoretical a/d conversion result (stored in the 10-bit a/d conver sion result register (adcr)) is shown by the following expression. sar = int ( 1024 + 0.5) adcr = sar 64 or ( ? 0.5) v ain < ( + 0.5) where, int( ): function which returns integer part of value in parentheses v ain : analog input voltage av ref : av ref pin voltage adcr: a/d conversion result register (adcr) value sar: successive approximation register figure 12-12 shows the relationship between the analo g input voltage and the a/d conversion result. figure 12-12. relationship between analog i nput voltage and a/d conversion result 1023 1022 1021 3 2 1 0 ffc0h ff80h ff40h 00c0h 0080h 0040h 0000h a/d conversion result sar adcr 1 2048 1 1024 3 2048 2 1024 5 2048 input voltage/av ref 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 v ain av ref av ref 1024 av ref 1024 adcr 64 adcr 64 chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 365 12.4.3 a/d converter operation mode the operation mode of the a/d converter is the select mode. one channe l of analog input is selected from ani0 to ani7 by the analog input channel specification register (ads) and a/d co nversion is executed. (1) a/d conversion operation by setting bit 7 (adcs) of the a/d converter mode regist er (adm) to 1, the a/d conversion operation of the voltage, which is applied to the analog input pin specif ied by the analog input channel specification register (ads), is started. when a/d conversion has been completed, the result of the a/d c onversion is stored in t he a/d conversion result register (adcr), and an interrupt request signal (int ad) is generated. when one a/d conversion has been completed, the next a/d conversion oper ation is immediately started. if ads is rewritten during a/d conversion, the a/d conv ersion operation under execut ion is stopped and restarted from the beginning. if 0 is written to adcs during a/d conversion, a/d conv ersion is immediately stopped. at this time, the conversion result immediat ely before is retained. figure 12-13. a/d conversion operation anin rewriting adm adcs = 1 rewriting ads adcs = 0 anin anin anin anim anin anim anim stopped conversion result immediately before is retained a/d conversion adcr, adcrh intad conversion is stopped conversion result immediately before is retained remarks 1. n = 0 to 7 2. m = 0 to 7 chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 366 the setting methods are described below. <1> set bit 0 (adce) of the a/d converter mode register (adm) to 1. <2> set the channel to be used in the analog input m ode by using bits 3 to 0 (adpc03 to adpc00) of the a/d port configuration register 0 (a dpc0) and bits 7 to 0 (pm27 to pm20) of port mode register 2 (pm2). <3> select conversion time by using bits 6 to 1 (fr3 to fr0, lv1, and lv0) of adm. <4> select a channel to be used by using bits 2 to 0 (ads2 to ads0) of the analog input channel specification register (ads). <5> set bit 7 (adcs) of adm to 1 to start a/d conversion. <6> when one a/d conversion has been completed, an interrupt request signal (intad) is generated. <7> transfer the a/d conversion data to the a/d conversion result register (adcr, adcrh). chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 367 12.5 how to read successive approximation type a/d converter ch aracteristics table here, special terms unique to the successive appr oximation type a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization erro r is not included in the overall error, zero -scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 12-14. overall error figur e 12-15. quanti zation error ideal line 0 ?? 0 1 ?? 1 digital output overall error analog input av ref 0 0 ?? 0 1 ?? 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av ref (4) zero-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (1/2lsb) when the digital output changes from 0......000 to 0......001. if the actual measurement value is greater than the theore tical value, it shows the difference between the actual measurement value of the analog in put voltage and the theoretical val ue (3/2lsb) when the digital output changes from 0??001 to 0??010. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 368 (5) full-scale error this shows the difference between the actual measuremen t value of the analog input vo ltage and the theoretical value (full-scale ? 3/2lsb) when the digital output chan ges from 1......110 to 1......111. (6) integral linearity error this shows the degree to which the conversion charac teristics deviate from the ideal linear relationship. it expresses the maximum value of the di fference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. figure 12-16. zero-scale error figure 12-17. full-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av ref digital output (lower 3 bits) analog input (lsb) 111 110 101 000 0 av ref ? 3 full-scale error ideal line analog input (lsb) digital output (lower 3 bits) av ref ? 2av ref ? 1 av ref figure 12-18. integral linearity error figure 12-19. differential linearity error 0 av ref digital output analog input integral linearity error ideal line 1 ?? 1 0 ?? 0 0 av ref digital output analog input differential linearity error 1 ?? 1 0 ?? 0 ideal 1lsb width (8) conversion time this expresses the time from the start of samp ling to when the digital output is obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the anal og voltage to be sampled by the sample & hold circuit. sampling time conversion time chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 369 12.6 cautions for 10-bit successive approximation type a/d converter (1) operating current in stop mode the a/d converter stops operating in the stop mode. at this time, th e operating current can be reduced by clearing bit 7 (adcs) and bit 0 (adce) of the a/d converter mode register (adm) to 0. to restart from the standby status, clear bit 0 (adif) of interrupt request flag register 1l (if1l) to 0 and start operation. (2) input range of ani0 to ani7 observe the rated range of the ani0 to an i7 input voltage. if a voltage of av ref or higher and av ss or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, the converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result regist er (adcr, adcrh) write and adcr or adcrh read by instruction upon the end of conversion adcr or adcrh read has priority. after the read op eration, the new co nversion result is written to adcr or adcrh. <2> conflict between adcr or adcrh write and a/d converter mode regi ster (adm) write, analog input channel specification register (ads ), or a/d port configuration regist er 0 (adpc0) write upon the end of conversion adm, ads, or adpc0 write has priority. adcr or adcrh write is not performe d, nor is the conversion end interrupt signal (intad) generated. (4) noise countermeasures to maintain the 10-bit resolution, attent ion must be paid to noise input to the av ref pin and pins ani0 to ani7. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external c as shown in figure 12-20 is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy is improved if the halt mode is set immediately after the start of conversion. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 370 figure 12-20. analog input pin connection reference voltage input c = 100 to 1,000 pf if there is a possibility that noise equal to or higher than av ref or equal to or lower than av ss may enter, clamp with a diode with a small v f value (0.3 v or lower). av ref av ss v ss ani0 to ani7 (5) ani0/seg39/p20 to ani7/seg32/p27 pins ( pd78f048x), ani0/ds0 ? /p20 to ani7/ref+/p27 pins ( pd78f049x) <1> the analog input pins (ani0 to ani7) ar e also used as i/o port pins (p20 to p27). when a/d conversion is performed with any of ani0 to ani7 selected, do not access p20 to p27 while conversion is in progress; otherwis e the conversion resolution may be degraded. it is recommended to any pin of p20 to p27 used as digi tal i/o port starting with the ani0/p 20 that is the furthest from av ref . <2> if a digital pulse is input or outpu t, or segment-output to the pins adjacent to the pins currently used for a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. therefore, do not input or output a pulse, or segment-output to the pins adjacent to the pin undergoing a/d conversion. (6) input impedance of ani0 to ani7 pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current fl ows when sampling is not in progre ss, and a current that charges the capacitor flows during sampling. consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 10 k , and to connect a capacitor of about 100 pf to the ani0 to ani7 pins (see figure 12- 20 ). (7) av ref pin input impedance a series resistor string of several tens of k is connected between the av ref and av ss pins. therefore, if the output impedance of t he reference voltage source is high, this will result in a series connection to the series resistor string between the av ref and av ss pins, resulting in a large reference voltage error. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 371 (8) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if th e analog input channel specification register (ads) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the ads rewrit e. caution is therefore re quired since, at this time, when adif is read immediately after the ads rewrite, ad if is set despite the fact a/d conversion for the post- change analog input has not ended. when a/d conversion is stopped and then resumed, clear ad if before the a/d conversion operation is resumed. figure 12-21. timing of a/d conver sion end interrupt request generation ads rewrite (start of anin conversion) a/d conversion adcr adif anin anin anim anim anin anin anim anim ads rewrite (start of anim conversion) adif is set but anim conversion has not ended. remarks 1. n = 0 to 7 2. m = 0 to 7 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the adcs bit is set to 1 within 1 s after the adce bit was set to 1, or if t he adcs bit is set to 1 with the adce bit = 0. take measures such as pollin g the a/d conversion end interrupt r equest (intad) and removing the first conversion result. (10) a/d conversion result regist er (adcr, adcrh) read operation when a write operation is performed to the a/d conver ter mode register (adm), analog input channel specification register (ads), and a/ d port configuration register 0 (adpc0 ), the contents of adcr and adcrh may become undefined. read the conversion result foll owing conversion completion before writing to adm, ads, and adpc0. using a timing other than the above ma y cause an incorrect conversion result to be read. chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) user?s manual u18329ej4v0ud 372 (11) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 12-22. internal equi valent circuit of anin pin anin c1 r1 c2 table 12-4. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 c1 c2 4.0 v av ref 5.5 v 8.1 k 8 pf 5 pf 2.7 v av ref < 4.0 v 31 k 8 pf 5 pf 2.3 v av ref < 2.7 v 381 k 8 pf 5 pf remarks 1. the resistance and capacitance values shown in table 12-4 are not guaranteed values. 2. n = 0 to 7 (12) simultaneous use of the 10-bit successive approximation type a/d converter and the 16-bit ? type a/d converter ( pd78f049x only) the a/d conversion accuracy may deteriorate when the 10 -bit successive approximation type a/d converter and the 16-bit ? type a/d converter are used at the same time. stop the 16-bit ? type a/d converter during 10-bit successive ap proximation type a/d converter operation, because the accuracy cannot be guaranteed. also, stop the 10-bit successive approximation type a/d converter during 16-bit ? type a/d converter operation. (do not operate them simultaneously.) user?s manual u18329ej4v0ud 373 chapter 13 16-bit ? type a/d converter ( pd78f049x only) 13.1 function of 16-bit ? type a/d converter the 16-bit ? type a/d converter converts an analog input signal in to a digital value, and consists of up to three channels (ds0 ? /ds0+, ds1 ? /ds1+, ds2 ? /ds2+) with a resolution of 16 bits. the a/d converter has the following function. ? 16-bit resolution a/d conversion 16-bit resolution a/d conversion is carried out repeat edly for one analog input channel selected from ds0 ? /ds0+, ds1 ? /ds1+, and ds2 ? /ds2+. each time an a/d conversion operat ion ends, an interrupt request (intdsad) is generated. the conversion time can be shortened by lowering the resolution. figure 13-1. block diagram of 16-bit ? type a/d converter ds0-/p20 addfs0, addfs1 intdsad addts addn0 to addn2 ds0+/p21 ds1-/p22 ds1+/p23 ds2-/p24 ds2+/p25 adpc03 adpc02 adpc01 adpc00 addpon addce hac animod adds1 adds0 addfs1 addfs0 addts addn2 addn1 addn0 16-bit ? type a/d conversion result register (addcr) 4 2 av ref ref-/p26 ref+/p27 addce control circuit addpon hac animod ? a/d converter control register 0 (addctl0) ? a/d converter control register 1 (addctl1) 16-bit ? type a/d reference 16-bit ? type a/d power supply select input+ select input- 16-bit ? type a/d circuit a/d port configuration register 0 (adpc0) internal bus selector 16-bit ? type a/d conversion status register (addstr) chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 374 13.2 configuration of 16-bit ? type a/d converter the 16-bit ? type a/d converter includes the following hardware. (1) ds0 ? /ds0+, ds1 ? /ds1+, and ds2 ? /ds2+ pins these are the 3-channel analog input pins of the 16-bit ? type a/d converter. they input analog signals to be converted into digital signals. pins other than the one selected as the analog input pin can be used as i/o port pins. when using these pins in differential input mode, input analog signals to ds ? and ds+. when using them in single input mode, input analog signals to ds+ and set ds ? to the same potential as v ss and av ss . (2) 16-bit ? type a/d circuit a 16-bit ? type a/d circuit converts voltage values sampled according to the reference voltage to digital values and outputs them to the control circuit. (3) control circuit a control circuit controls the conv ersion time and starting/stopping of conv ersion operation of analog input to be a/d converted. when a/d conversion is completed, the conversion result is transferred to the 16-bit ? type a/d conversion result register (addcr) wher eby an interrupt (intdsad) is generated. (4) 16-bit ? type a/d conversion result register (addcr) the a/d conversion result is loaded from the control circuit to this register each time a/d conversion is completed, and the addcr register holds the a/d conv ersion result in its higher 16 bits. (5) 8-bit ? type a/d conversion result register (addcrh) the a/d conversion result is loaded from the control circuit to this register each time a/d conversion is completed, and the addcrh register stores the higher 8 bits of the a/d conversion result. caution when data is read from addcr and addcrh, a wa it cycle is generated. do not read data from addcr and addcrh when the cpu is operating on the subsystem clock and the peripheral hardware clock is stopped. (6) av ref pin this pin inputs an analog power to the 16-bit ? type a/d circuit. when using at least one port of port 2 as a digital port or for segment output, set it to the same potential as the v dd pin. (7) ref ? and ref+ pins this pin inputs the reference voltage of the 16-bit ? type a/d converter. signals input to ds0 ? /ds0+, ds1 ? /ds1+ and ds2 ? /ds2+ are converted to digital signals, according to the voltage applied across ref ? and ref+. the ref ? and ref+ pins must be used at the same potential as the v ss /av ss and av ref pins, respectively. (8) av ss pin this is the ground potential pin of the a/d converter. al ways use this pin at the same potential as that of the v ss pin even when the a/d converter is not used. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 375 (9) 16-bit ? type a/d converter cont rol register 0 (addctl0) this register sets the 16-bit ? type a/d circuit or control circuit power on/off state, conversi on start/stop state, high-accuracy mode on/off state, ? input mode control, and analog input channel. (10) 16-bit ? type a/d converter cont rol register 1 (addctl1) this register sets the sampling clock to be a/d conv erted, serial/parallel mode state and sampling count (resolution). (11) 16-bit ? type a/d conversion status register (addstr) this register checks which channel has completed conversi on, when a 16-bit ? type a/d conversion operation completion (conversion completion interrupt generation) and a conversion channel change occur at the same time. (12) a/d port configuration register 0 (adpc0) this register switches the ani0/p20/ds0 ? to ani7/p27/ref+ pins to analog input (analog input of 16-bit ? type a/d converter or analog input of 10- bit successive approximation type a/ d converter) or digital i/o of port. (13) port mode register 2 (pm2) this register switches the ani0/p20/ds0 ? to ani7/p27/ref+ pins to input or output. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 376 13.3 registers used in 16-bit ? type a/d converter the 16-bit ? type a/d converter uses the following nine registers. ? 16-bit ? type a/d converter control register 0 (addctl0) ? 16-bit ? type a/d converter control register 1 (addctl1) ? 16-bit ? type a/d conversion result register (addcr) ? 8-bit ? type a/d conversion result register (addcrh) ? 16-bit ? type a/d conversion status register (addstr) ? a/d port configuration register 0 (adpc0) ? 16-bit ? type a/d sampling delay time setting enable register ? 16-bit ? type a/d sampling delay time setting register ? port mode register 2 (pm2) (1) 16-bit ? type a/d converter cont rol register 0 (addctl0) this register sets the 16-bit ? type a/d circuit or control circuit power on/off state, conversi on start/stop state, high-accuracy mode on/off state, ? input mode control, and analog input channel. addctl0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 377 figure 13-2. format of 16-bit ? type a/d converter control register 0 (addctl0) adds0 adds1 0 0 ainmcd hac addce adpon 16-bit ? type a/d conversion operation control stops conversion operation starts conversion operation addce 0 1 0 1 2 3 <4> <5> <6> <7> addctl0 address: ff7ch after reset: 00h r/w symbol setting 16-bit ? type a/d conversion high-accuracy mode high-accuracy mode off high-accuracy mode on hac 0 1 16-bit ? type a/d circuit power supply control power supply off power supply on addpon 0 1 16-bit ? type a/d conversion input mode control single input differential input ainmod 0 1 16-bit ? type analog input specification ds0+/ds0- ds1+/ds1- ds2+/ds2- setting prohibited adds1 0 0 1 1 adds0 0 1 0 1 cautions 1. do not set the addpon and addce bits to 1 at the same time. addce must be set to 1, at least 1.2 s after addpon has been set to 1. 2. setting the ? analog input channel to be set by adds1 and adds0 to a pin which has been selected to be used in the analog input mode by the adpc 0 register is prohibited. 3. operating 16-bit ? type a/d conversion and 10-bit su ccessive approximation type a/d conversions at the same time (addce = 1 and adcs = 1) is prohibited. 4. if addctl0 is rewritten (inc luding identical data), a/d conver sion operation is resumed after it has been initialized. 5. set the input voltag e in accordance with table 13-4 input voltage range. 6. when executing a stop inst ruction, power to the 16-bit ? type a/d converter must be turned off (addpon = 0). chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 378 (2) 16-bit ? type a/d converter cont rol register 1 (addctl1) this register sets the samp ling clock to be 16-bit ? type a/d converted, serial/parallel mode state and sampling count (resolution). addctl1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-3. format of 16-bit ? type a/d converter control register (addctl1) addn0 addn1 addn2 0 0 addts addfs0 addfs1 setting 16-bit ? type a/d serial/parallel mode serial mode parallel mode addts 0 1 0 1 2 3 4 <5> 6 7 addctl1 address: ff7dh after reset: 00h r/w symbol 16-bit ? type a/d sampling clock (f vp ) selection f prs /4 f prs /8 f prs /16 f sub /2 addfs1 0 0 1 1 addfs0 0 1 0 1 number of times of 16-bit ? type a/d sampling n (resolution) 256 (8 bits) 1024 (10 bits) 2048 (11 bits) 4096 (12 bits) 8192 (13 bits) 16384 (14 bits) 32768 (15 bits) 65536 (16 bits) addn2 0 0 0 0 1 1 1 1 addn1 0 0 1 1 0 0 1 1 addn0 0 1 0 1 0 1 0 1 cautions 1. set the sampling clock (conversion time) so that it satisfies the conditions in table 13-1. when selecting the conversion time, take clo ck frequency errors in to consideration. 2. writing to the addctl1 register during 16-bit ? type a/d conversion operation is prohibited. be sure to write after 16-bit ? type a/d conversion operation has been stopped (addce = 0). 3. setting the parallel m ode is prohibited when f sub is selected as the 16-bit ? type a/d sampling clock (f vp ). chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 379 the conversion time can be derived from the sampling clock (f vp ) and sampling count (n) via the following calculations. caution if addctl0 is rewritten (including the same values), con version is assumed to have been restarted from that point an d the conversion time of the first conversion is applied. sampling time = 1/f vp n initialization time = 1/operation clock + 1/f vp 256 operation clock addfs1-0 selected as 1, 1: f sub addfs1-0 selected as other than the above: f prs in serial mode chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 380 table 13-1. sampling clock (sampling time) setting conditions addn2 av ref condition sampling clock: f vp (conversion time in 16-bit resolution) 3.5 v av ref 5.5 v 1.25 mhz max. (52.42 ms min.) differential input 2.7 v av ref < 3.5 v 625 khz max. (104.85 ms min.) 2.85 v av ref 5.5 v 625 khz max. (104.85 ms min.) single input 2.7 v av ref < 2.85 v 525 khz max. (124.83 ms min.) table 13-2. examples of sampling time under setting conditions number of times of 16-bit ? type a/d sampling: n (resolution) f prs f vp 65536 (16-bit) 32768 (15-bit) 16384 (14-bit) 8192 (13-bit) 4096 (12-bit) 2048 (11-bit) 1024 (10-bit) 256 (8-bit) f prs /4 setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited f prs /8 note 1 52.42 ms 26.21 ms 13.10 ms 6.55 ms 3.27 ms 1.63 ms 0.81 ms 0.20 ms 10 mhz f prs /16 note 2 104.85 ms 52.42 ms 26.21 ms 13.10 ms 6.55 ms 3.27 ms 1.63 ms 0.41 ms f prs /4 setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited setting prohibited f prs /8 note 1 65.53 ms 32.76 ms 16.38 ms 8.19 ms 4.09 ms 2.04 ms 1.02 ms 0.25 ms 8 mhz f prs /16 131.07 ms 65.53 ms 32.76 ms 16.38 ms 8.19 ms 4.09 ms 2.04 ms 0.51 ms f prs /4 note 1 52.42 ms 26.21 ms 13.10 ms 6.55 ms 3.27 ms 1.63 ms 0.81 ms 0.40 ms f prs /8 note 2 104.85 ms 52.42 ms 26.21 ms 13.10 ms 6.55 ms 3.27 ms 1.63 ms 0.81 ms 5 mhz f prs /16 209.71 ms 104.85 ms 52.42 ms 26.21 ms 13.10 ms 6.55 ms 3.27 ms 1.63 ms f prs /4 note 1 65.53 ms 32.76 ms 16.38 ms 8.19 ms 4.09 ms 2.04 ms 1.02 ms 0.25 ms f prs /8 131.07 ms 65.53 ms 32.76 ms 16.38 ms 8.19 ms 4.09 ms 2.04 ms 0.51 ms 4 mhz f prs /16 262.14 ms 131.07 ms 65.53 ms 32.76 ms 16.38 ms 8.19 ms 4.09 ms 1.02 ms f prs /4 131.07 ms 65.53 ms 32.76 ms 16.38 ms 8.19 ms 4.09 ms 2.04 ms 0.51 ms f prs /8 262.14 ms 131.07 ms 65.53 ms 32.76 ms 16.38 ms 8.19 ms 4.09 ms 1.02 ms 2 mhz f prs /16 524.28 ms 262.14 ms 131.07 ms 65.53 ms 32.76 ms 16.38 ms 8.19 ms 2.04 ms ? f sub /2 4 s 2 s 1 s 500 ms 250 ms 125 ms 62.5 ms 15.62 ms notes 1. setting the differential input mode (2.7 v av ref < 3.5 v) and single input mode is prohibited since the sampling time conditions are not satisfied in these modes. 2. setting the single input mode (2.7 v av ref < 2.85 v) is prohibited since the sampling time conditions are not satisfied in this modes. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 381 (3) 16-bit ? type a/d conversion result register (addcr) this register is a 16-bit register t hat stores the a/d conversion result. each time a/d conversion ends, the conversion result is loaded from the ? a/d circuit. the higher 8 bits of the conversion result are stored in ff7fh and the lower 8 bits are stored in ff7eh. addcr can be read by a 16-bit memory manipulation instruction. reset signal generation clears this register to 0000h. figure 13-4. format of 16-bit ? type a/d conversion result register (addcr) symbol address: ff7eh, ff7fh after reset: 0000h r ff7fh ff7eh addcr cautions 1. when n-bit resolution is set, conversion results are stored starting from the higher bits and the remaining 16-n bits are fixed to ?0?. 2. if the conversion completion interrupt and conversion result read operation conflict, the conversion result may be undefine d. read the conversion result after the generation of the conversion result completion interrupt, and before the next conversion completion. (4) 8-bit ? type a/d conversion result register (addcrh) this register is an 8-bit register that stores the a/d conversion result. the higher 8 bits of 16-bit resolution are stored. addcrh can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-5. format of 8-bit ? type a/d conversion result register (addcrh) symbol addcrh address: ff7fh after reset: 00h r 76543210 caution if the conversion completion interrupt and c onversion result read operation conflict, the read value of the conversion result may be undefine d. read the conversion result after the generation of the conversion result completion interrupt, and before the next conversion completion. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 382 (5) 16-bit ? type a/d conversion status register (addstr) this register holds the channel for which a/d conversi on has been completed. it al so checks which channel has completed conversion. addstr can be read by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 13-6. format of 16-bit ? type a/d conversion status register (addstr) addit0 addit1 0 0 0 0 0 0 0 1 2 3 4 5 6 7 addstr address: ff75h after reset: 00h r symbol when differential input is selected when single input is selected channel converted by 16-bit ? type a/d conversion ds0+/ds0- ds1+/ds1- ds2+/ds2- ds0+ ds1+ ds2+ addit1 0 0 1 addit0 0 1 0 chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 383 (6) a/d port configurati on register 0 (adpc0) this register switches the ani0/p20/ds0- to ani7/p27/ ref+ pins to analog input (analog input of 16-bit ? type a/d converter or analog input of 10- bit successive approximation type a/ d converter) or digital i/o of port. adpc0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 08h. figure 13-7. format of a/d port configuration register 0 (adpc0) adpc00 adpc01 adpc02 adpc03 0 0 0 0 digital i/o (d)/analog input (a: successive setting prohibited adpc03 0 1 2 3 4 5 6 7 adpc0 address: ff8fh after reset: 08h r/w symbol p27/ ani7/ ref+ a/ a/ a/ a/ a/ a a a d p26/ ani6/ ref- a/ a/ a/ a/ a/ a a d d p25/ ani5/ ds2+ a/ a/ a/ a/ a/ a d d d p24/ ani4/ ds2- a/ a/ a/ a/ a/ d d d d p23/ ani3/ ds1+ a/ a/ a/ a d d d d d p22/ ani2/ ds1- a/ a/ a/ d d d d d d p21/ ani1/ ds0+ a/ a d d d d d d d p20/ ani0/ ds0- a/ d d d d d d d d 0 0 0 0 0 0 0 0 1 adpc02 0 0 0 0 1 1 1 1 0 adpc01 0 0 1 1 0 0 1 1 0 adpc00 0 1 0 1 0 1 0 1 0 other than above approximation type, : ? type) switching cautions 1. set the channel used for a/d conversion to the input mode by using port mode register 2 (pm2). 2. do not set the pin set by adpc0 as digital i/o by ads, adds1, or adds0. 3. if data is written to adpc0, a wait cycle is generated. do not write data to adpc0 when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 34 cautions for wait. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 384 (7) 16-bit ? type a/d sampling delay time setting enable register this register enables the setting of the sampling delay time. the address of this register is dire ctly specified and set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. remark this register is not required to be set if the a/d conversion accuracy is sufficient. figure 13-8. format of 16-bit ? type a/d sampling delay ti me setting enable register address: fa26h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 add0ten 0 0 0 0 0 0 0 add0ten control to set delay time 0 disables delay time setting 1 enables delay time setting caution be sure to set this register after turning off the power of the 16-bit ? type a/d circuit (addpon = 0) and stopping conversion operation (addce = 0). (8) 16-bit ? type a/d sampling delay time setting register this register sets the sampling delay time. the accuracy can be improved by setting the optimal delay time. the address of this register is dire ctly specified and set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 20h. remark this register is not required to be set if the a/d conversion accuracy is sufficient. figure 13-9. format of 16-bit ? type a/d sampling delay time setting register address: fa27h after reset: 20h r/w symbol 7 6 5 4 3 2 1 0 0 add0dly2 add0dly1 add0dly0 0 0 0 0 add0dly2 add0dly1 add0dly0 setting delay time [nsec] 0 0 0 2 0 0 1 4 0 1 0 6 (default) 0 1 1 8 1 0 0 10 1 0 1 12 1 1 0 14 1 1 1 16 caution be sure to set this register after turning off the power of the 16-bit ? type a/d circuit (addpon = 0), stopping conversion operation ( addce = 0), and enabling the delay time setting (add0ten = 1). chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 385 (9) port mode register 2 (pm2) when using the ani0/p20/ds0 ? to ani7/p27/ref+ pins for analog input port, set pm20 to pm27 to 1. the output latches of p20 to p27 at this time may be 0 or 1. if pm20 to pm27 are set to 0, they cannot be used as analog input port pins. pm2 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 13-10. format of port mode register 2 (pm2) pm20 pm21 pm22 pm23 pm24 pm25 pm26 pm27 p2n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) pm2n 0 1 0 1 2 3 4 5 6 7 pm2 address: ff22h after reset: ffh r/w symbol p20/ani0/ds0 ? to p27/ani7/ref+ pins are as shown below de pending on the settings of adpc0, pm2, ads, and addctl0. table 13-3. setting functions of p20/ani0/ds0 ? to p27/ani7/ref+ pins adpc0 pm2 ads addctl0 p20/ani0/ds0 ? to p27/ani7/ref+ pins does not select ani does not select dsn . analog input (not to be converted) selects ani does not select dsn . analog input (to be converted by successive approximation type a/d converter) does not select ani selects dsn . analog input (to be converted by ? type a/d converter) input mode selects ani selects dsn . setting prohibited analog input selection output mode ? setting prohibited input mode ? digital input digital i/o selection output mode ? digital output remark n = 0 to 2 chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 386 13.4 circuit configur ation example of 16-bit ? type a/d converter figures 13-11 shows the circuit config uration example when using the 16-bit ? type a/d converter. figure 13-11. circuit configuration example when using 16-bit ? type a/d converter (differential input) reference voltage input ref+ ref ? 0.1 f 0.1 f + + 10 f 0.1 f 10 f analog signal input dsn+ dsn ? av ref av ss av ss 0.1 f 0.1 f analog signal input chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 387 13.5 16-bit ? type a/d converter operations 13.5.1 basic operations of 16-bit ? type a/d converter <1> set add0ten note 1 = 1 (enable the delay time setting). note 2 <2> use add0dly2 to add0dly0 note 1 to set the delay time. note 2 <3> set the ? a/d conversion target channel. <4> set addpon to 1 ( ? a/d power-on). <5> set the conversion operation modes, such as the input mode, operation mode and sampling counts via the addctl1 and addctl0 registers. <6> conversion operation starts when addce is set to 1, at least 1.2 s after addpon has been set to 1. (conversion operation also starts when addce is set to 1 before 1.2 s elapse after addpon has been set to 1, but the conversion result is not guaranteed in this case). note 3 <7> when conversion is completed, an interrupt (intdsad ) is generated and the result is stored in the addcr register. read the addcr register value. <8> if addce is not to be set to 0 (conversion operation st op), repeat step 5. if c onversion operation is to be stopped, set addce to 0. <9> when the current is to be reduced without using ? a/d, set addpon to 0 ( ? a/d power-off). notes 1. directly specify the addresses and write to add0ten and add0dly2 to add0dly0 by using an 8-bit memory manipulation instruction. 2. setting of the delay time is not required if the conversion accuracy is sufficient. 3. writing to addctl1 during conver sion operation is prohibited. when the pin settings subject to ? a/d conversion are altered during conversion operation, conversion results are not stored. when the target pin settings are altered, restart conversion operation. 13.5.2 operation mode of 16-bit ? type a/d converter several operation modes can be set for the 16-bit ? type a/d converter. (1) differential input mode/single input mode differential input mode or single input mode c an be selected as the input mode for the 16-bit ? type a/d converter. the accuracy is higher in differential input mode than in single input mode. when using the differential input mode, input analog signals to dsn- and dsn+. when using the single input mode, input analog signals to dsn+ and set dsn- to the same potential as v ss and av ss . make sure that the central values of the dsn- and dsn+ input voltages are 0.5 ref+ in differential input mode. (2) 16-bit ? type a/d high-accuracy mode high-accuracy mode on or off can be selected as the conversion accuracy mode for the 16-bit ? type a/d converter. the accuracy is higher when set to high- accuracy mode on than when set to high-accuracy mode off. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 388 table 13-4. input voltage range input voltage range to dsn+ input voltage range to dsn- high-accuracy mode on 0.5 (ref+) + x1 0.5 (ref+) ? x1 differential input high-accuracy mode off 0.5 (ref+) + x2 0.5 (ref+) ? x2 high-accuracy mode on 0.1 (ref+) to 0.9 (ref+) single input high-accuracy mode off 0 to ref+ fixed to av ss remark x1 = ? 0.4 (ref+) to 0.4 (ref+) x2 = ? 0.5 (ref+) to 0.5 (ref+) n = 0 to 2 figure 13-12. example of application circuit ? adc differential input single input av ref : ? ad power supply ref+ ref- ds0+ ds0- ds1+ ds1- reference voltage figure 13-13. enabled input ra nge by a/d converter mode < differential input > < single input > 50% ref+ 90% ref+ analog input (dsn+, dsn-) ref+ = av ref dsn+ voltage dsn- voltage digital output 10% ref+ (dsn+) ? (dsn-) 50% ref+ 90% ref+ ref+ = av ref dsn+ voltage dsn- voltage (= av ss ) 10% ref+ (dsn+) analog input (dsn+) conversion result : input in high-accuracy mode is prohibited. : input in high-accuracy mode is prohibited. digital output conversion result remark n = 0 to 2 chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 389 (3) serial mode/parallel mode serial or parallel mode can be sele cted as the input mode for the 16-bit ? type a/d converter. the parallel mode can reduce the conversion time to a fourth of that in the serial mode. the conversion time of the first conversion, however, is the same as t hat in the serial mode. also, the sampling time itself is the same as in the serial mode. figure 13-14. conversion time and sampling time d4 d5 d3 d2 d1 d0 d4 d3 d2 d1 d0 conversion result register intdsad intdsad conversion start serial mode sampling time conversion time after second conversion first conversion time d16 d12 d8 d4 d0 conversion result register conversion start parallel mode sampling time d17 d13 d9 d5 d1 conversion time after second conversion first conversion time d14 d10 d6 d2 d15 d11 d7 d3 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 initialization time initialization time chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 390 13.6 how to read ? type a/d converter characteristics table here, special terms unique to the ? type a/d converter are explained. (1) resolution this is the minimum analog input vo ltage that can be identif ied. that is, the perce ntage of the analog input voltage per bit of digital output is called 1lsb (least si gnificant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). 1lsb is as follows when the resolution is 16 bits. 1lsb = 1/2 16 = 1/65536 ? 0.0015%fsr (2) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same digita l code, so a quantization error cannot be avoided. note that the quantization error is not included in the offset, gain error, in tegral linearity error, and differential linearity error in the characteristics table. figure 13-15. quan tization error 1 ...... 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 ref+ 0 ...... 0 chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 391 (3) offset (single input) the offset represents the difference between the approximation line of the actually measured analog input voltage values and the theoretical values (1/2 lsb). if the approximation line is greater than the theoretical values, it shows the difference between the approximation line of the actually measured analog input voltage values and the theoretical values (3/2 lsb). figure 13-16. offset (single input) 111 011 010 001 000 0 1 2 3 ref+ offset approximation line ideal line digital output (lower 3 bits) analog input (lsb) (4) offset (differential input) the offset represents the difference between the approximation line of the actually measured analog input voltage values and the theoretical values (1/2 full-scale). in the case of 16-bit resolution, the offset represents the difference between the approxim ation line of the actually measured analog input voltage values and the theoretical values (8000h ? 1/2 lsb). if the approximation line is greater than the theoretical values, it shows the difference between the approximation line of the actually measured analog input voltage val ues and the theoretical values (8000h + 1/2 lsb). figure 13-17. offset (differential input) ffffh 8001h 8000h 7fffh 0000h 7fffh 8000h 8001h ref+ digital output (lsb) analog input (lsb) approximation line offset ideal line chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 392 (5) gain error the gain error is the ratio of the ideal inclinat ion to the inclination of the approximation line. figure 13-18. gain error ref+ ideal line inclination of approximation line inclination of ideal line ideal 1lsb analog input digital output gain error = inclination of approximation line ? 1 inclination of ideal line 100 [%] 0 1 ...... 1 0 ...... 0 approximation line (6) integral linearity error this shows the degree to which the conversion characteri stics deviate from the approximation line. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the offset and gain error are 0. figure 13-19. integral linearity error 0 ref+ integral linearity error 1 ...... 1 0 ...... 0 ideal line analog input digital output chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 393 (7) differential linearity error while the ideal width of code output is 1lsb, this indi cates the difference between the actual measurement value and the ideal value. however, excluding the gain error. figure 13-20. differential linearity error 0 digital output analog input differential linearity error ideal 1lsb width 1 ...... 1 0 ...... 0 ref+ (8) conversion time the conversion time is the time from starting conversion or obtaining the conversion result to obtaining the next conversion result. for details, see figure 13-14. conversion time and sampling time . (9) sampling time the sampling time is the time required to perform one conversion. for details, see figure 13-14. conversion time and sampling time . (10) approximation line the approximation line is the line defined by applying the least-squares method to the actually measured values. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 394 13.7 cautions for 16-bit ? type a/d converter (1) setting standby mode clear bit 7 (addpon) and bit 6 (addce) of the 16-bit ? type a/d converter control register 0 (addctl0) to 0 before setting to the stop mode. to restart from the standby status, clear bit 6 (dsadif) of interrupt request flag register 1l (if1l) to 0 and start operation. (2) input range of ds0 ? , ds0+, ds1 ? , ds1+, ds2 ? , and ds2+ observe the rated range of the ds0 ? , ds0+, ds1 ? , ds1+, ds2 ? , and ds2+ input voltage. if a voltage of ref+ (av ref ) or higher, or ref ? (av ss ) or lower (even in the range of absolut e maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. in addition, t he converted values of the other channels may also be affected. (3) conflicting operations <1> conflict between a/d conversion result regi ster (addcr, addcrh) writ e and addcr or addcrh read by instruction upon the end of conversion addcr or addcrh read has priority. after the read operation, the new conversion result is written to addcr or addcrh. <2> conflict between addcr or addcrh write and 16-bit ? type a/d converter control register 0 (addctl0) write or a/d port configurat ion register 0 (adpc0) write upon the end of conversion addctl0 or adpc0 write has priority. addcr or ad dcrh write is not performed, nor is the conversion end interrupt signal (intdsad) generated. (4) noise countermeasures to maintain the accuracy of specification, at tention must be paid to noise input to the ds0 ? , ds0+, ds1 ? , ds1+, ds2 ? , ds2+, ref ? (av ss ), and ref+ (av ref ) pins. <1> connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> the higher the output impedance of the analog input source, the greater the influence. to reduce the noise, connecting external capacitor is recommended. <3> do not switch these pins wit h other pins during conversion. <4> the accuracy may be improved if the halt mode is set immediately after the start of conversion. (5) ds0 ? /ani0/p20, ds0+ /ani1/p21, ds1 ? /ani2/p22, ds1+ /ani3/p23, ds2 ? /ani4/p24, ds 2+/ani5/p25, ref ? /ani6/p26, and ref+/ani7/p27 <1> the analog input pins (ds0 ? , ds0+, ds1 ? , ds1+, ds2 ? , ds2+, ref ? , and ref+) are also used as i/o port pins (p20 to p27). when 16-bit ? type a/d conversion is pe rformed with any of ds0 ? /ds0+, ds1 ? /ds1+, or ds2 ? /ds2+ selected, do not access p20 to p27 while conversi on is in progress; otherwise the accuracy may be degraded. it is recommended to any pin of p20 to p27 used as digital i/o port starting with the ds0 ? /ani0/p20 that is the furthest from ref+. <2> if any pin among pins p20 to p27 is used as a digital i/o port during 16-bit ? type a/d conversion, the expected value of the a/d conversion may not be obtained due to coupling noise. make sure that digital pulses are not input to or output from pins p20 to p27 during a/d conversion. chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 395 (6) input impedance of ds0+, ds1+, ds2+, ds0 ? , ds1 ? , and ds2 ? pins this a/d converter charges a sampling capacitor for sampling during sampling time. therefore, only a leakage current flow when sampling is not in progress, and a current that charges the capacitor flows during sampling. consequently, the input impeda nce fluctuates depending on whether sampling is in progress, and on the other states. to make sure that sampling is effective, however, it is recommended to keep the ou tput impedance of the analog input source to within 5 k . (7) av ref pin input impedance a current flows to the av ref pin while the 16-bit ? type a/d converter operates. if the output impedance of the reference voltage source is high, the error of the reference voltage between the av ref pin/ref+ pin and av ss pin/ref ? pin increases. (8) interrupt request flag (dsadif) the interrupt request flag (dsadif) is not cleared ev en if bit 1 and 0 (adds1 and adds0) of the 16-bit ? type a/d converter control register 0 (addctl0) is changed. therefore, if an analog input pin is changed during a/d conversion, the a/d conversi on result and dsadif for the pre-change analog input may be set just before the addctl0 re write. caution is therefor e required since, at this time, when dsadif is read immediately after the addc tl0 rewrite, dsadif is set despite the fact a/d conversion for the post-change analog input has not ended. when a/d conversion is stopped and then resumed, clear dsadif before the a/d conversion operation is resumed. figure 13-21. timing of a/d conver sion end interrupt request generation dsn-/dsn+ dsn-/dsn+ dsn-/dsn+ dsm-/dsm+ dsm-/dsm+ dsn-/dsn+ dsm-/dsm+ dsm-/dsm+ a/d conversion addcr, addcrh dsadif addctl0 rewrite (start of dsn-/dsn+ conversion) addctl0 rewrite (start of dsm-/dsm+ conversion) dsadif is set but dsm-/dsm+ conversion has not ended. remarks 1. n = 0 to 2 2. m = 0 to 2 chapter 13 16-bit ? type a/d converter ( pd78f049x only) user?s manual u18329ej4v0ud 396 (9) conversion results just after a/d conversion start the first a/d conversion value immediately after a/d conv ersion starts may not fall wit hin the rating range if the addce bit is set to 1 within 1.2 s after the addpon bit was set to 1, or if the addce bit is set to 1 with the addpon bit = 0. take measures such as polling the a/d conversion end interrupt request (intdsad) and removing the first conversion result. (10) internal equivalent circuit the equivalent circuit of the analog input block is shown below. figure 13-22. internal eq uivalent circuit of dsn ? and dsn+ pin dsn-, dsn+ c1 c2 r1 c3 r2 table 13-5. resistance and capacitance valu es of equivalent circui t (reference values) av ref r1 r2 c1 c2 c3 4.0 v av ref 5.5 v 8.1 k 6.8 k 8 pf 1.3 pf 0.22 pf 2.7 v av ref < 4.0 v 31 k 36 k 8 pf 1.3 pf 0.22 pf remarks 1. the resistance and capacitance values shown in table 13-5 are not guaranteed values. 2. n = 0 to 2 (11) simultaneous use of the 10-bit successive approximation type a/d converter and the 16-bit ? type a/d converter the a/d conversion accuracy may deteriorate when the 10 -bit successive approximation type a/d converter and the 16-bit ? type a/d converter are used at the same time. stop the 16-bit ? type a/d converter during 10-bit successive ap proximation type a/d converter operation, because the accuracy cannot be guaranteed. also, stop the 10-bit successive approximation type a/d converter during 16-bit ? type a/d converter operation. (do not operate them simultaneously.) user?s manual u18329ej4v0ud 397 chapter 14 serial interface uart0 14.1 functions of serial interface uart0 serial interface uart0 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 14.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode the functions of this mode are outlined below. for details, see 14.4.2 asynchronous seri al interface (uart) mode and 14.4.3 dedicated baud rate generator . ? maximum transfer rate: 625 kbps ? two-pin configuration t x d0: transmit data output pin r x d0: receive data input pin ? length of communication data can be selected from 7 or 8 bits. ? dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full-duplex operation). ? fixed to lsb-first communication cautions 1. if clock supply to serial interface uart0 is not stopped (e.g., in the halt mode), normal operation continues. if clock supply to serial interface uart0 is stopped (e.g., in the stop mode), each register stops operating, and hold s the value immediatel y before clock supply was stopped. the t x d0 pin also holds the value imme diately before clock supply was stopped and outputs it. however, the operati on is not guaranteed after clock supply is resumed. therefore, reset the circuit so th at power0 = 0, rxe0 = 0, and txe0 = 0. 2. set power0 = 1 and then set txe0 = 1 (tr ansmission) or rxe0 = 1 (reception) to start communication. 3. txe0 and rxe0 are synch ronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least tw o clocks of base clock after txe0 or rxe0 has been clear ed to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission ci rcuit or reception circui t may not be initialized. 4. set transmit data to t xs0 at least one base clock (f xclk0 ) after setting txe0 = 1. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 398 14.2 configuration of serial interface uart0 serial interface uart0 includes the following hardware. table 14-1. configurati on of serial interface uart0 item configuration registers receive buffer register 0 (rxb0) receive shift register 0 (rxs0) transmit shift register 0 (txs0) control registers asynchronous serial interface o peration mode register 0 (asim0) asynchronous serial interface recepti on error status register 0 (asis0) baud rate generator control register 0 (brgc0) port function register 1 (pf1) port mode register 1 (pm1) port register 1 (p1) chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 399 figure 14-1. block diagram of serial interface uart0 intst0 intsr0 transmit shift register 0 (txs0) receive shift register 0 (rxs0) receive buffer register 0 (rxb0) asynchronous serial interface reception error status register 0 (asis0) asynchronous serial interface operation mode register 0 (asim0) baud rate generator control register 0 (brgc0) 8-bit timer/ event counter 50 output registers selector baud rate generator baud rate generator reception unit reception control filter internal bus transmission control transmission unit output latch (p13) pm13 7 7 selector csi10 output signal pf13 port function register 1 (pf1) t x d0/ so10/p13 r x d0/ si10/p12 f prs /2 5 f prs /2 3 f prs /2 f xclk0 chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 400 (1) receive buffer register 0 (rxb0) this 8-bit register stores parallel data conv erted by receive shift register 0 (rxs0). each time 1 byte of data has been received, new receive dat a is transferred to this r egister from receive shift register 0 (rxs0). if the data length is set to 7 bits the receive data is tran sferred to bits 0 to 6 of rxb0 and the msb of rxb0 is always 0. if an overrun error (ove0) occurs, the rece ive data is not transferred to rxb0. rxb0 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation and power0 = 0 set this register to ffh. (2) receive shift register 0 (rxs0) this register converts the serial data input to the r x d0 pin into parallel data. rxs0 cannot be directly manipulated by a program. (3) transmit shift register 0 (txs0) this register is used to set transmit data. transmission is started when data is written to txs0, and serial data is transmitted from the t x d0 pins. txs0 can be written by an 8-bit memory manipulatio n instruction. this register cannot be read. reset signal generation, power0 = 0, and txe0 = 0 set this register to ffh. cautions 1. set transmit data to txs0 at least one base clock (f xclk0 ) after setting txe0 = 1. 2. do not write the next transmit data to t xs0 before the transmissi on completion interrupt signal (intst0) is generated. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 401 14.3 registers controlling serial interface uart0 serial interface uart0 is controlled by the following six registers. ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port function register 1 (pf1) ? port mode register 1 (pm1) ? port register 1 (p1) (1) asynchronous serial interface ope ration mode register 0 (asim0) this 8-bit register controls the serial comm unication operations of serial interface uart0. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. figure 14-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (1/2) address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of the internal operation clock. txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission. rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception. notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status register 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 402 figure 14-2. format of asynchronous serial inte rface operation mode register 0 (asim0) (2/2) ps01 ps00 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl0 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl0 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe0) of asynchronous serial interface reception error status register 0 (asis0) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set power0 to 1 and then set txe0 to 1. to stop the transmission, clear txe0 to 0, and then clear power0 to 0. 2. to start the reception, set power0 to 1 and th en set rxe0 to 1. to stop the reception, clear rxe0 to 0, and then clear power0 to 0. 3. set power0 to 1 and then set rxe0 to 1 wh ile a high level is input to the rxd0 pin. if power0 is set to 1 and rxe0 is set to 1 wh ile a low level is input, reception is started. 4. txe0 and rxe0 are synch ronized by the base clock (f xclk0 ) set by brgc0. to enable transmission or reception again, set txe0 or rxe0 to 1 at least two cl ocks of base clock after txe0 or rxe0 has been cleared to 0. if txe0 or rxe0 is set within two clocks of base clock, the transmission circuit or recepti on circuit may not be initialized. 5. set transmit data to t xs0 at least one base clock (f xclk0 ) after setting txe0 = 1. 6. clear the txe0 and rxe0 bits to 0 be fore rewriting the ps01, ps00, and cl0 bits. 7. make sure that txe0 = 0 when rewriting th e sl0 bit. reception is always performed with ?number of stop bits = 1?, and therefore, is not affected by the set value of the sl0 bit. 8. be sure to set bit 0 to 1. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 403 (2) asynchronous serial interface recepti on error status register 0 (asis0) this register indicates an error status on completion of re ception by serial interface uart0. it includes three error flag bits (pe0, fe0, ove0). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power0) or bi t 5 (rxe0) of asim0 to 0 clears this register to 00h. 00h is read when this register is read. if a recept ion error occurs, read asis0 and then read receive buffer register 0 (rxb0) to clear the error flag. figure 14-3. format of asynchronous serial inte rface reception error status register 0 (asis0) address: ff73h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis0 0 0 0 0 0 pe0 fe0 ove0 pe0 status flag indicating parity error 0 if power0 = 0 or rxe0 = 0, or if asis0 register is read. 1 if the parity of transmit data does not match the parity bit on completion of reception. fe0 status flag indicating framing error 0 if power0 = 0 or rxe0 = 0, or if asis0 register is read. 1 if the stop bit is not detected on completion of reception. ove0 status flag indicating overrun error 0 if power0 = 0 and rxe0 = 0, or if asis0 register is read. 1 if receive data is set to the rxb0 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe0 bit differs depending on the set values of the ps01 and ps00 bits of asynchronous serial interface operati on mode register 0 (asim0). 2. only the first bit of the receive data is checked as the stop bit, re gardless of the number of stop bits. 3. if an overrun error occurs , the next receive data is not wr itten to receive buffer register 0 (rxb0) but discarded. 4. if data is read from asis0, a wait cycle is generated. do not read data from asis0 when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 34 cautions for wait. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 404 (3) baud rate generator c ontrol register 0 (brgc0) this register selects the base clock of serial interf ace uart0 and the division value of the 5-bit counter. brgc0 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 1fh. figure 14-4. format of baud rate ge nerator control register 0 (brgc0) address: ff71h after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 brgc0 tps01 tps00 0 mdl04 mdl03 mdl02 mdl01 mdl00 base clock (f xclk0 ) selection note 1 tps01 tps00 f prs = 2 mhz f prs = 5 mhz f prs = 8 mhz f prs = 10 mhz 0 0 tm50 output note 2 0 1 f prs /2 1 mhz 2.5 mhz 4 mhz 5 mhz 1 0 f prs /2 3 250 khz 625 khz 1 mhz 1.25 mhz 1 1 f prs /2 5 62.5 khz 156.25 khz 250 khz 312.5 khz mdl04 mdl03 mdl02 mdl01 mdl00 k selection of 5-bit counter output clock 0 0 setting prohibited 0 1 0 0 0 8 f xclk0 /8 0 1 0 0 1 9 f xclk0 /9 0 1 0 1 0 10 f xclk0 /10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 1 0 26 f xclk0 /26 1 1 0 1 1 27 f xclk0 /27 1 1 1 0 0 28 f xclk0 /28 1 1 1 0 1 29 f xclk0 /29 1 1 1 1 0 30 f xclk0 /30 1 1 1 1 1 31 f xclk0 /31 notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counte r 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit time r/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 405 cautions 1. make sure that bit 6 (txe0) and bit 5 (rxe0) of the asim0 register = 0 when rewriting the mdl04 to mdl00 bits. 2. the baud rate value is the output clock of the 5-bit c ounter divided by 2. remarks 1. f xclk0 : frequency of base clock selected by the tps01 and tps00 bits 2. f prs : peripheral hardware clock frequency 3. k: value set by the mdl04 to md l00 bits (k = 8, 9, 10, ..., 31) 4. : don?t care 5. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 (4) port function register 1 (pf1) this register sets the pin f unctions of p13/so10/txd0 pin. pf1 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pf1 to 00h. figure 14-5. format of port function register 1 (pf1) address: ff20h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pf1 0 pf16 0 0 pf13 0 0 0 pf16 port (p16), csia0, and uart6 output specification 0 used as p16 or soa0 1 used as txd6 pf13 port (p13), csi10, and uart0 output specification 0 used as p13 or so10 1 used as txd0 chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 406 (5) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p13/so10/txd0 pin for serial interface data output, clear pm13 to 0. the output latch of p13 at this time may be 0 or 1. when using the p12/si10/rxd0 pin for seri al interface data input, set pm12 to 1. the output latch of p12 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 14-6. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 407 14.4 operation of serial interface uart0 serial interface uart0 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 14.4.1 operation stop mode in this mode, serial communication cannot be executed, thus reducing the power consumption. in addition, the pins can be used as ordinary port pins in this mode. to se t the operation stop mode, clear bits 7, 6, and 5 (power0, txe0, and rxe0) of asim0 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 0 (asim0). asim0 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff70h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim0 power0 txe0 rxe0 ps01 ps00 cl0 sl0 1 power0 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe0 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). rxe0 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the input from the r x d0 pin is fixed to high level when power0 = 0. 2. asynchronous serial interface reception error status register 0 (asis0), transmit shift register 0 (txs0), and receive buffer register 0 (rxb0) are reset. caution clear power0 to 0 after clearing txe0 and rxe0 to 0 to set the operation stop mode. to start the communication, set power0 to 1, and then set txe0 or rxe0 to 1. remark to use the rxd0/si10/p12 and txd0/so10/ p13 pins as general-purpose port pins, see chapter 4 port functions . chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 408 14.4.2 asynchronous serial interface (uart) mode in this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 0 (asim0) ? asynchronous serial interface recept ion error status register 0 (asis0) ? baud rate generator control register 0 (brgc0) ? port mode register 1 (pm1) ? port register 1 (p1) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the brgc0 register (see figure 14-4 ). <2> set bits 1 to 4 (sl0, cl0, ps00, and ps01) of the asim0 register (see figure 14-2 ). <3> set bit 7 (power0) of the asim0 register to 1. <4> set bit 6 (txe0) of the asim0 register to 1. transmission is enabled. set bit 5 (rxe0) of the asim0 register to 1. reception is enabled. <5> write data to the txs0 register. data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 14-2. relationship between register settings and pins pin function power0 txe0 rxe0 pm13 p13 pm12 p12 uart0 operation txd0/so10/p13 rxd0/si10/p12 0 0 0 note note note note stop so10/p13 si10/p12 0 1 note note 1 reception so10/p13 rxd0 1 0 0 note note transmission txd0 si10/p12 1 1 1 0 1 transmission/ reception txd0 rxd0 note can be set as port function or serial interface csi10. remark : don?t care power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 pm1 : port mode register p1 : port output latch chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 409 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 14-7 and 14-8 show the format and waveform example of the normal transmit/receive data. figure 14-7. format of normal uart transmit/receive data start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits (lsb first) ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 0 (asim0). figure 14-8. example of normal uart transmit/receive data waveform 1. data length: 8 bits, parity: even pari ty, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 7 bits, parity: odd parity , stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 3. data length: 8 bits, pa rity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 410 (b) parity types and operation the parity bit is used to detect a bit error in communicati on data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 411 (c) transmission if bit 7 (power0) of asynchronous serial interface op eration mode register 0 (asim0) is set to 1 and bit 6 (txe0) of asim0 is then set to 1, transmission is enabl ed. transmission can be star ted by writing transmit data to transmit shift register 0 (txs0). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the start bit is output from the t x d0 pin, and the transmit data is output followed by the rest of the data in order starting from the lsb. when tr ansmission is completed, the parity and stop bits set by asim0 are appended and a transmi ssion completion interrupt request (intst0) is generated. transmission is stopped until the data to be transmitted next is written to txs0. figure 14-9 shows the timing of the transmission comp letion interrupt request (intst0). this interrupt occurs as soon as the last stop bit has been output. caution after transmit data is written to txs0, do not write the next transmit data before the transmission completion interrupt signal (intst0) is generated. figure 14-9. transmission comple tion interrupt request timing 1. stop bit length: 1 intst0 d0 start d1 d2 d6 d7 stop t x d0 (output) parity 2. stop bit length: 2 t x d0 (output) intst0 d0 start d1 d2 d6 d7 parity stop chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 412 (d) reception reception is enabled and the r x d0 pin input is sampled when bit 7 (power0) of asynchronous serial interface operation mode register 0 (asim0) is set to 1 and then bit 5 (rxe0) of asim0 is set to 1. the 5-bit counter of the baud rate generator st arts counting when the falling edge of the r x d0 pin input is detected. when the set value of baud rate generator control register 0 (brgc0) has been counted, the r x d0 pin input is sampled again ( in figure 14-10). if the r x d0 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, recept ion is started, and serial data is sequentially stored in receive shift register 0 (rxs0) at the set baud rate. when the st op bit has been received, the reception completion interrupt (intsr0) is generated and t he data of rxs0 is written to receive buffer register 0 (rxb0). if an overrun error (ove0) occurs, however, the receive data is not written to rxb0. even if a parity error (pe0) occurs while reception is in progress, reception continues to the reception position of the stop bit, and an recepti on error interrupt (intsr0) is generat ed after completion of reception. intsr0 occurs upon completion of reception and in case of a reception error. figure 14-10. reception completi on interrupt request timing r x d0 (input) intsr0 start d0 d1 d2 d3 d4 d5 d6 d7 parity stop rxb0 cautions 1. if a reception erro r occurs, read asynchronous serial interface receptio n error status register 0 (asis0) and then read receive buffe r register 0 (rxb0) to clear the error flag. otherwise, an overrun error will occur when the next data is received, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1? . the second stop bit is ignored. chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 413 (e) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 0 (asis0) is set as a result of data reception, a reception error inte rrupt (intsr0) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis0 in the reception error interrupt (intsr0) servicing (see figure 14-3 ). the contents of asis0 are cleared to 0 when asis0 is read. table 14-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 0 (rxb0). (f) noise filter of receive data the r x d0 signal is sampled using the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 14- 11, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 14-11. noise filter circuit internal signal b internal signal a match detector in base clock r x d0 q in ld_en q chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 414 14.4.3 dedicated baud rate generator the dedicated baud rate generator consis ts of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of uart0. separate 5-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 7 and 6 (tps01 and tps00) of baud rate generator control register 0 (brgc0) is supplied to each module when bit 7 (power0) of asyn chronous serial interface operation mode register 0 (asim0) is 1. this clock is called the base clock and its frequency is called f xclk0 . the base clock is fixed to low level when power0 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power0) or bit 6 (txe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when power0 = 1 and txe0 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit shift register 0 (txs0). ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power0) or bit 5 (rxe0) of asynchronous serial interface operation mode register 0 (asim0) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. figure 14-12. configuration of baud rate generator f xclk0 selector power0 5-bit counter match detector baud rate brgc0: mdl04 to mdl00 1/2 power0, txe0 (or rxe0) brgc0: tps01, tps00 8-bit timer/ event counter 50 output f prs /2 5 f prs /2 f prs /2 3 baud rate generator remark power0: bit 7 of asynchronous serial interface operation mode register 0 (asim0) txe0: bit 6 of asim0 rxe0: bit 5 of asim0 brgc0: baud rate generator control register 0 chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 415 (2) generation of serial clock a serial clock to be generated can be specified by usi ng baud rate generator control register 0 (brgc0). select the clock to be input to the 5-bit counter by using bits 7 and 6 (tps01 and tps00) of brgc0. bits 4 to 0 (mdl04 to mdl00) of brgc0 can be used to select the division value (f xclk0 /8 to f xclk0 /31) of the 5-bit counter. 14.4.4 calculation of baud rate (1) baud rate calculation expression the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk0 : frequency of base clock selected by the tps 01 and tps00 bits of the brgc0 register k: value set by the mdl04 to mdl00 bits of t he brgc0 register (k = 8, 9, 10, ..., 31) table 14-4. set value of tps01 and tps00 base clock (f xclk0 ) selection note 1 tps01 tps00 f prs = 2 mhz f prs = 5 mhz f prs = 8 mhz f prs = 10 mhz 0 0 tm50 output note 2 0 1 f prs /2 1 mhz 2.5 mhz 4 mhz 5 mhz 1 0 f prs /2 3 250 khz 625 khz 1 mhz 1.25 mhz 1 1 f prs /2 5 62.5 khz 156.25 khz 250 khz 312.5 khz notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counte r 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit time r/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. (2) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within th e permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies th e range shown in (4) permissible baud rate ra nge during reception. f xclk0 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate) chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 416 example: frequency of base clock = 2.5 mhz = 2,500,000 hz set value of mdl04 to mdl00 bits of brgc0 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78,125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] (3) example of setting baud rate table 14-5. set data of baud rate generator f prs = 2.0 mhz f prs = 5.0 mhz f prs = 10.0 mhz baud rate [bps] tps01, tps00 k calculate d value err [%] tps01, tps00 k calculate d value err [%] tps01, tps00 k calculate d value err [%] 1200 3h 26 1202 0.16 ? ? ? ? ? ? ? ? 2400 3h 13 2404 0.16 ? ? ? ? ? ? ? ? 4800 2h 26 4808 0.16 3h 16 4883 1.73 ? ? ? ? 9600 2h 13 9615 0.16 3h 8 9766 1.73 3h 16 9766 1.73 10400 2h 12 10417 0.16 2h 30 10417 0.16 3h 15 10417 0.16 19200 1h 26 19231 0.16 2h 16 19531 1.73 3h 8 19531 1.73 24000 1h 21 23810 ? 0.79 2h 13 24038 0.16 2h 26 24038 0.16 31250 1h 16 31250 0 2h 10 31250 0 2h 20 31250 0 33600 1h 15 33333 ? 0.79 2h 9 34722 3.34 2h 19 32895 ? 2.1 38400 1h 13 38462 0.16 2h 8 39063 1.73 2h 16 39063 1.73 56000 1h 9 55556 ? 0.79 1h 22 56818 1.46 2h 11 56818 1.46 62500 1h 8 62500 0 1h 20 62500 0 2h 10 62500 0 76800 ? ? ? ? 1h 16 78125 1.73 2h 8 78125 1.73 115200 ? ? ? ? 1h 11 113636 ? 1.36 1h 22 113636 ? 1.36 153600 ? ? ? ? 1h 8 156250 1.73 1h 16 156250 1.73 312500 ? ? ? ? ? ? ? ? 1h 8 312500 0 remark tps01, tps00: bits 7 and 6 of baud rate generator control register 0 (brgc0) (setting of base clock (f xclk0 )) k: value set by the mdl04 to mdl00 bits of brgc0 (k = 8, 9, 10, ..., 31) f prs : peripheral hardware clock frequency err: baud rate error chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 417 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 14-13. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart0 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 14-13, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 0 (brgc0) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart0 k: set value of brgc0 fl: 1-bit data length margin of latch timing: 2 clocks chapter 14 serial interface uart0 user?s manual u18329ej4v0ud 418 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart0 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 14-6. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 8 +3.53% ? 3.61% 16 +4.14% ? 4.19% 24 +4.34% ? 4.38% 31 +4.44% ? 4.47% remarks 1. the permissible error of reception depends on t he number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc0 k ? 2 2k 21k + 2 2k 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 user?s manual u18329ej4v0ud 419 chapter 15 serial interface uart6 15.1 functions of serial interface uart6 serial interface uart6 has the following two modes. (1) operation stop mode this mode is used when serial communication is not executed and can enable a reduction in the power consumption. for details, see 15.4.1 operation stop mode . (2) asynchronous serial interface (uart) mode this mode supports the lin (local interconnect network) -bus. the functions of this mode are outlined below. for details, see 15.4.2 asynchronous seri al interface (uart) mode and 15.4.3 dedicated baud rate generator . ? maximum transfer rate: 625 kbps ? two-pin configuration t x d6: transmit data output pin r x d6: receive data input pin ? txd6/rxd6 pins can be selected from p112/p113 (d efault) or p16/p15 by using the registers. ? data length of communication data can be selected from 7 or 8 bits. ? dedicated internal 8-bit baud rate generator allowing any baud rate to be set ? transmission and reception can be performe d independently (full duplex operation). ? msb- or lsb-first communication selectable ? inverted transmission operation ? sync break field transmission from 13 to 20 bits ? more than 11 bits can be identified for sync break field reception (sbf reception flag provided). cautions 1. the t x d6 output inversion function inverts only th e transmission side a nd not the reception side. to use this f unction, the reception side must be ready for reception of inverted data. 2. if clock supply to serial interface uart6 is not stopped (e .g., in the halt mode), normal operation continues. if clock supply to serial interface uart6 is stopped (e.g., in the stop mode), each register stops operating, and hold s the value immediatel y before clock supply was stopped. the t x d6 pin also holds the value imme diately before clock supply was stopped and outputs it. however, the operati on is not guaranteed after clock supply is resumed. therefore, reset the circuit so th at power6 = 0, rxe6 = 0, and txe6 = 0. 3. set power6 = 1 and then set txe6 = 1 (tr ansmission) or rxe6 = 1 (reception) to start communication. 4. txe6 and rxe6 are sync hronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or r xe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circui t may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. if data is continuously tr ansmitted, the communicat ion timing from the stop bit to the next start bit is extended two operating clocks of the macro. however, th is does not affect the result of communication because the reception side initializ es the timing when it has detected a start bit. do no t use the continuous transmissi on function if the interface is used in lin communication operation. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 420 remark lin stands for local interconnect network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. lin communication is single-master communication, and up to 15 slaves can be connected to one master. the lin slaves are used to contro l the switches, actuator s, and sensors, and thes e are connected to the lin master via the lin network. normally, the lin master is connected to a network such as can (controller area network). in addition, the lin bus uses a single-wire method and is connected to the nodes via a transceiver that complies with iso9141. in the lin protocol, the master tr ansmits a frame with baud rate information and the slave receives it and corrects the baud rate error. theref ore, communication is possible when the baud rate error in the slave is 15% or less. figures 15-1 and 15-2 outline the transmissi on and reception operations of lin. figure 15-1. lin transmission operation lin bus wakeup signal frame 8 bits note 1 55h transmission data transmission data transmission data transmission data transmission 13-bit note 2 sbf transmission sync break field sync field identifier field data field data field checksum field tx6 (output) intst6 note 3 notes 1. the wakeup signal frame is substituted by 80h transmission in the 8-bit mode. 2. the sync break field is output by har dware. the output width is the bit length set by bits 4 to 2 (sbl62 to sbl60) of asynchronous serial inte rface control register 6 (asicl6) (see 15.4.2 (2) (h) sbf transmission ). 3. intst6 is output on completion of each transmissi on. it is also output when sbf is transmitted. remark the interval between each field is controlled by software. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 421 figure 15-2. lin reception operation lin bus 13-bit sbf reception sf reception id reception data reception data reception data reception wakeup signal frame sync break field sync field identifier field data field data field checksum field r x d6 (input) reception interrupt (intsr6) edge detection (intp0) capture timer disable enable disable enable <1> <2> <3> <4> <5> reception processing is as follows. <1> the wakeup signal is detected at the edge of t he pin, and enables uart6 and sets the sbf reception mode. <2> reception continues until the stop bi t is detected. when an sbf with low- level data of 11 bits or more has been detected, it is assum ed that sbf reception has been complet ed correctly, and an interrupt signal is output. if an sbf with low-level dat a of less than 11 bits has been detect ed, it is assumed that an sbf reception error has occurred. the interrupt signal is not output and the sbf reception mode is restored. <3> if sbf reception has been completed correctly, an interru pt signal is output. start 16-bit timer/event counter 00 by the sbf reception end interrupt servicing and meas ure the bit interval (pulse width) of the sync field (see 6.4.8 pulse width measurement operation ). detection of errors ove6, pe6, and fe6 is suppressed, and error detection proc essing of uart communication and dat a transfer of the shift register and rxb6 is not performed. the shift register holds the reset value ffh. <4> calculate the baud rate error from the bit interval of the sync field, disable ua rt6 after sf reception, and then re-set baud rate generator control register 6 (brgc6). <5> distinguish the checksum field by software. also perform processing by software to initialize uart6 after reception of the checksum field and to set the sbf reception mode again. figure 15-3 shows the port configurat ion for lin reception operation. the wakeup signal transmitted from the lin master is received by detecting the edge of the external interrupt (intp0). the length of the sync field transmitted from the lin master can be measured using the external event capture operation of 16-bit timer/event counte r 00, and the baud rate error can be calculated. the input source of t he reception port input (r x d6) can be input to the external interrupt (intp0) and 16-bit timer/event counter 00 by port input swit ch control (isc0/isc1), without connecting r x d6 and intp0/ti000 externally. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 422 figure 15-3. port configurati on for lin reception operation rxd6 input intp0 input ti000 input p120/intp0/ exlvi p33/ti000/rtcdiv/ rtccl/buz/intp2 port input switch control (isc0) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 423 the peripheral functions used in the lin communication operation are shown below. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 424 figure 15-4. block diagram of serial interface uart6 internal bus asynchronous serial interface control register 6 (asicl6) transmit buffer register 6 (txb6) transmit shift register 6 (txs6) intst6 baud rate generator asynchronous serial interface control register 6 (asicl6) reception control receive shift register 6 (rxs6) receive buffer register 6 (rxb6) intsr6 baud rate generator filter intsre6 asynchronous serial interface reception error status register 6 (asis6) asynchronous serial interface operation mode register 6 (asim6) asynchronous serial interface transmission status register 6 (asif6) transmission control registers 8 reception unit transmission unit clock selection register 6 (cksr6) baud rate generator control register 6 (brgc6) 8 selector rxd6/p15/sia0 intp0 ti000 isc1 isc0 isc5 isc4 input switch control register (isc) input switch control register (isc) selector selector output latch (p16) pm16 selector csia0 output signal pf16 port function register 1 (pf1) selector isc5 isc4 txd6/p112/seg18 r x d6/p113/seg19 t x d6/p16/soa0 f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output f xclk6 pm112 output latch (p112) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 425 (1) receive buffer register 6 (rxb6) this 8-bit register stores parallel data conv erted by receive shift register 6 (rxs6). each time 1 byte of data has been received, new receive data is transferred to this register from rxs6. if the data length is set to 7 bits, data is transferred as follows. ? in lsb-first reception, the receive data is transferred to bits 0 to 6 of rxb6 and the msb of rxb6 is always 0. ? in msb-first reception, the receive data is transferred to bits 1 to 7 of rxb6 and the lsb of rxb6 is always 0. if an overrun error (ove6) occurs, the rece ive data is not transferred to rxb6. rxb6 can be read by an 8-bit memory manipulation inst ruction. no data can be written to this register. reset signal generation sets this register to ffh. (2) receive shift register 6 (rxs6) this register converts the serial data input to the r x d6 pin into parallel data. rxs6 cannot be directly manipulated by a program. (3) transmit buffer register 6 (txb6) this buffer register is used to set transmit data. tr ansmission is started when data is written to txb6. this register can be read or written by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. cautions 1. do not write data to txb6 when bi t 1 (txbf6) of asynchronous serial interface transmission status register 6 (asif6) is 1. 2. do not refresh (write the same value to) txb6 by software during a communication operation (when bits 7 and 6 (power6, txe6 ) of asynchronous serial interface operation mode register 6 (asim6) are 1 or when bits 7 and 5 (power6, rxe6) of asim6 are 1). 3. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. (4) transmit shift register 6 (txs6) this register transmits the data transferred from txb6 from the t x d6 pin as serial data. data is transferred from txb6 immediately after txb6 is written for the first tr ansmission, or immediately before intst6 occurs after one frame was transmitted for continuous transmission. da ta is transferred from txb6 and transmitted from the t x d6 pin at the falling edge of the base clock. txs6 cannot be directly manipulated by a program. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 426 15.3 registers controlling serial interface uart6 serial interface uart6 is controlled by the following twelve registers. ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port function register 1 (pf1) ? port mode register 1 (pm1) ? port register 1 (p1) ? port mode register 11 (pm11) ? port register 11 (p11) (1) asynchronous serial interface ope ration mode register 6 (asim6) this 8-bit register controls the serial comm unication operations of serial interface uart6. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. remark asim6 can be refreshed (the same value is wr itten) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (1/2) address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the intern al operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . 1 enables operation of t he internal operation clock txe6 enables/disables transmission 0 disables transmission (synchronously resets th e transmission circuit). 1 enables transmission rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). 1 enables reception notes 1. the output of the t x d6 pin goes high level and the input from the r x d6 pin is fixed to the high level when power6 = 0 during transmission. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 ( asif6), bit 7 (sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 427 figure 15-5. format of asynchronous serial inte rface operation mode register 6 (asim6) (2/2) ps61 ps60 transmission oper ation reception operation 0 0 does not output parity bit. reception without parity 0 1 outputs 0 parity. reception as 0 parity note 1 0 outputs odd parity. judges as odd parity. 1 1 outputs even parity. judges as even parity. cl6 specifies character length of transmit/receive data 0 character length of data = 7 bits 1 character length of data = 8 bits sl6 specifies number of stop bits of transmit data 0 number of stop bits = 1 1 number of stop bits = 2 isrm6 enables/disables occurr ence of reception completion interrupt in case of error 0 ?intsre6? occurs in case of error (at this time, intsr6 does not occur). 1 ?intsr6? occurs in case of error (at this time, intsre6 does not occur). note if ?reception as 0 parity? is selected, the parity is not judged. therefore, bit 2 (pe6) of asynchronous serial interface reception error status register 6 (asis6) is not set and the error interrupt does not occur. cautions 1. to start the transmission, set power6 to 1 and then set txe6 to 1. to stop the transmission, clear txe6 to 0, and then clear power6 to 0. 2. to start the reception, set power6 to 1 and th en set rxe6 to 1. to stop the reception, clear rxe6 to 0, and then clear power6 to 0. 3. set power6 to 1 and then set rxe6 to 1 while a high level is input to the r x d6 pin. if power6 is set to 1 and rxe6 is set to 1 wh ile a low level is input, reception is started. 4. txe6 and rxe6 are synch ronized by the base clock (f xclk6 ) set by cksr6. to enable transmission or reception again, set txe6 or r xe6 to 1 at least two clocks of the base clock after txe6 or rxe6 has been cleared to 0. if txe6 or rxe6 is set within two clocks of the base clock, the transmission circuit or reception circui t may not be initialized. 5. set transmit data to txb6 at least one base clock (f xclk6 ) after setting txe6 = 1. 6. clear the txe6 and rxe6 bits to 0 be fore rewriting the ps61, ps60, and cl6 bits. 7. fix the ps61 and ps60 bits to 0 when used in lin communication operation. 8. clear txe6 to 0 before re writing the sl6 bit. reception is always performed with ?the number of stop bits = 1?, and therefore, is not affected by the set value of the sl6 bit. 9. make sure that rxe6 = 0 when rewriting the isrm6 bit. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 428 (2) asynchronous serial interface recepti on error status register 6 (asis6) this register indicates an error status on completion of re ception by serial interface uart6. it includes three error flag bits (pe6, fe6, ove6). this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6) or bi t 5 (rxe6) of asim6 to 0 clears this register to 00h. 00h is read when this register is read. if a recept ion error occurs, read asis6 and then read receive buffer register 6 (rxb6) to clear the error flag. figure 15-6. format of asynchronous serial inte rface reception error status register 6 (asis6) address: ff53h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asis6 0 0 0 0 0 pe6 fe6 ove6 pe6 status flag indicating parity error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if the parity of transmit data does not match the parity bit on completion of reception fe6 status flag indicating framing error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if the stop bit is not detected on completion of reception ove6 status flag indicating overrun error 0 if power6 = 0 or rxe6 = 0, or if asis6 register is read 1 if receive data is set to the rxb6 register and the next reception operation is completed before the data is read. cautions 1. the operation of the pe6 bit differs depending on the set values of the ps61 and ps60 bits of asynchronous serial interface operati on mode register 6 (asim6). 2. for the stop bit of the recei ve data, only the first stop bit is checked regardless of the number of stop bits. 3. if an overrun error occurs , the next receive data is not wr itten to receive buffer register 6 (rxb6) but discarded. 4. if data is read from asis6, a wait cycle is generated. do not read data from asis6 when the cpu is operating on the subsystem clock and th e peripheral hardware clock is stopped. for details, see chapter 34 cautions for wait. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 429 (3) asynchronous serial interface tran smission status register 6 (asif6) this register indicates the status of transmission by se rial interface uart6. it includes two status flag bits (txbf6 and txsf6). transmission can be continued without disruption even during an interrupt period, by writing the next data to the txb6 register after data has been transferred from the txb6 register to the txs6 register. this register is read-only by an 8-bit memory manipulation instruction. reset signal generation, or clearing bit 7 (power6) or bit 6 (txe6) of asim6 to 0 clears this register to 00h. figure 15-7. format of asynchronous serial in terface transmission status register 6 (asif6) address: ff55h after reset: 00h r symbol 7 6 5 4 3 2 1 0 asif6 0 0 0 0 0 0 txbf6 txsf6 txbf6 transmit buffer data flag 0 if power6 = 0 or txe6 = 0, or if data is tr ansferred to transmit shift register 6 (txs6) 1 if data is written to transmit buffer register 6 (txb6) (if data exists in txb6) txsf6 transmit shift register data flag 0 if power6 = 0 or txe6 = 0, or if the next data is not transferred from transmit buffer register 6 (txb6) after completion of transfer 1 if data is transferred from transmit buffer regist er 6 (txb6) (if data transmi ssion is in progress) cautions 1. to transmit data conti nuously, write the first transmit data (first byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit data (second byte) to the txb6 register. if data is written to th e txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. 2. to initialize the transmission unit upon comple tion of continuous transmission, be sure to check that the txsf6 flag is ?0 ? after generation of the tran smission completion interrupt, and then execute initializat ion. if initiali zation is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 430 (4) clock selection register 6 (cksr6) this register selects the base cl ock of serial interface uart6. cksr6 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. remark cksr6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 15-8. format of clock selection register 6 (cksr6) address: ff56h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 cksr6 0 0 0 0 tps63 tps62 tps61 tps60 base clock (f xclk6 ) selection note 1 tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 5 mhz f prs = 8 mhz f prs = 10 mhz 0 0 0 0 f prs note 2 2 mhz 5 mhz 8 mhz 10 mhz 0 0 0 1 f prs /2 1 mhz 2.5 mhz 4 mhz 5 mhz 0 0 1 0 f prs /2 2 500 khz 1.25 mhz 2 mhz 2.5 mhz 0 0 1 1 f prs /2 3 250 khz 625 khz 1 mhz 1.25 mhz 0 1 0 0 f prs /2 4 125 khz 312.5 khz 500 khz 625 khz 0 1 0 1 f prs /2 5 62.5 khz 156.25 khz 250 khz 312.5 khz 0 1 1 0 f prs /2 6 31.25 khz 78.13 khz 125 khz 156.25 khz 0 1 1 1 f prs /2 7 15.625 khz 39.06 khz 62.5 khz 78.13 khz 1 0 0 0 f prs /2 8 7.813 khz 19.53 khz 31.25 khz 39.06 khz 1 0 0 1 f prs /2 9 3.906 khz 9.77 khz 15.625 khz 19.53 khz 1 0 1 0 f prs /2 10 1.953 khz 4.88 khz 7.513 khz 9.77 khz 1 0 1 1 tm50 output note 3 other than above setting prohibited notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tps63 = tps 62 = tps61 = tps60 = 0 (base clock: f prs ) is prohibited. 3. note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counte r 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit time r/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 431 caution make sure power6 = 0 wh en rewriting tps63 to tps60. remarks 1. f prs : peripheral hardware clock frequency 2. tmc506: bit 6 of 8-bit timer mode control register 50 (tmc50) tmc501: bit 1 of tmc50 (5) baud rate generator c ontrol register 6 (brgc6) this register sets the division value of t he 8-bit counter of serial interface uart6. brgc6 can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. remark brgc6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). figure 15-9. format of baud rate ge nerator control register 6 (brgc6) address: ff57h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 brgc6 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 mdl67 mdl66 mdl65 mdl64 mdl63 mdl62 mdl61 mdl60 k output clock selection of 8-bit counter 0 0 0 0 0 0 setting prohibited 0 0 0 0 0 1 0 0 4 f xclk6 /4 0 0 0 0 0 1 0 1 5 f xclk6 /5 0 0 0 0 0 1 1 0 6 f xclk6 /6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 1 0 0 252 f xclk6 /252 1 1 1 1 1 1 0 1 253 f xclk6 /253 1 1 1 1 1 1 1 0 254 f xclk6 /254 1 1 1 1 1 1 1 1 255 f xclk6 /255 cautions 1. make sure that bit 6 (txe6) and bit 5 (rxe6) of the asim6 register = 0 when rewriting the mdl67 to mdl60 bits. 2. the baud rate is the output clo ck of the 8-bit counter divided by 2. remarks 1. f xclk6 : frequency of base clock selected by the t ps63 to tps60 bits of cksr6 register 2. k: value set by mdl67 to mdl60 bits (k = 4, 5, 6, ..., 255) 3. : don?t care chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 432 (6) asynchronous serial interface control register 6 (asicl6) this register controls the serial communicati on operations of serial interface uart6. asicl6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 16h. caution asicl6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (power6, txe6) of asim6 = 1 or bits 7 and 5 (power6, rxe6) of asim6 = 1). however, do not set both sbrt6 and sbtt6 to 1 by a refresh operation during sbf reception (sbrt6 = 1) or sbf transmission (until intst6 occurs since sb tt6 has been set (1)), because it may re-trigger sbf r eception or sbf transmission. figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (1/2) address: ff58h after reset: 16h r/w note symbol <7> <6> 5 4 3 2 1 0 asicl6 sbrf6 sbrt6 sbtt6 sbl62 sbl61 sbl60 dir6 txdlv6 sbrf6 sbf reception status flag 0 if power6 = 0 and rxe6 = 0 or if sbf reception has been completed correctly 1 sbf reception in progress sbrt6 sbf reception trigger 0 ? 1 sbf reception trigger sbtt6 sbf transmission trigger 0 ? 1 sbf transmission trigger note bit 7 is read-only. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 433 figure 15-10. format of asynchronous serial interface control register 6 (asicl6) (2/2) sbl62 sbl61 sbl60 sbf transmission output width control 1 0 1 sbf is output with 13-bit length. 1 1 0 sbf is output with 14-bit length. 1 1 1 sbf is output with 15-bit length. 0 0 0 sbf is output with 16-bit length. 0 0 1 sbf is output with 17-bit length. 0 1 0 sbf is output with 18-bit length. 0 1 1 sbf is output with 19-bit length. 1 0 0 sbf is output with 20-bit length. dir6 first-bit specification 0 msb 1 lsb txdlv6 enables/disables inverting t x d6 output 0 normal output of t x d6 1 inverted output of t x d6 cautions 1. in the case of an sbf reception error, the mode return s to the sbf reception mode. the status of the sbrf6 flag is held (1). 2. before setting the sbrt6 bit, make sure that bit 7 (power6) and bit 5 (rxe6) of asim6 = 1. after setting the sbrt6 bit to 1, do not clear it to 0 before sbf reception is completed (before an interrupt request signal is generated). 3. the read value of the sbrt6 bit is always 0. sbrt6 is auto matically cleared to 0 after sbf reception has been co rrectly completed. 4. before setting the sbtt6 bit to 1, make sure that bit 7 (pow er6) and bit 6 (txe6) of asim6 = 1. after setting the sbtt6 bit to 1, do not clear it to 0 before sbf transmission is completed (before an interrupt requ est signal is generated). 5. the read value of the sbtt6 bit is always 0. sbtt6 is automatically clear ed to 0 at the end of sbf transmission. 6. do not set the sbrt6 bit to 1 during reception, and do not set the sbtt6 bit to 1 during transmission. 7. before rewriting the dir6 and txdlv6 bits, clear the txe6 a nd rxe6 bits to 0. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 434 (7) input switch control register (isc) by setting isc4 to 1, the uart6 i/o pins are swit ched from p113/seg19/rxd6 and p112/seg18/txd6 to p15/sia0/ chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 435 (8) port function register 1 (pf1) this register sets the pin f unctions of p16/soa0/txd6 pin. pf1 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pf1 to 00h. figure 15-12. format of port function register 1 (pf1) address: ff20h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pf1 0 pf16 0 0 pf13 0 0 0 pf16 port (p16), csia0, and uart6 output specification 0 used as p16 or soa0 1 used as txd6 pf13 port (p13), csi10, and uart0 output specification 0 used as p13 or so10 1 used as txd0 (9) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using the p16/soa0/t x d6 pin for serial interface data output, clear pm16 to 0. the out put latch of p16 at this time may be 0 or 1. when using the p15/sia0/r x d6 pin for serial interface da ta input, set pm15 to 1. the output latch of p15 at this time may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 15-13. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 436 (10) port mode register 11 (pm11) this register sets port 11 input/output in 1-bit units. when using the p112/seg18/t x d6 pin for serial interface data output, clear pm112 to 0 and set the output latch of p112 to 1. when using the p113/seg19/r x d6 pin for serial interface data input, se t pm113 to 1. the output latch of p113 at this time may be 0 or 1. pm11 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 15-14. format of port mode register 11 (pm11) address: ff2bh after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm11 1 1 1 1 pm113 pm112 pm111 pm110 pm11n p11n pin i/o mode selection (n = 0 to 3) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 437 15.4 operation of serial interface uart6 serial interface uart6 has the following two modes. ? operation stop mode ? asynchronous serial interface (uart) mode 15.4.1 operation stop mode in this mode, serial communication cannot be executed; theref ore, the power consumption can be reduced. in addition, the pins can be used as ordinary po rt pins in this mode. to set the operation stop mode, clear bits 7, 6, and 5 (power6, txe6, and rxe6) of asim6 to 0. (1) register used the operation stop mode is set by asynchronous serial interface operation mode register 6 (asim6). asim6 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 01h. address: ff50h after reset: 01h r/w symbol <7> <6> <5> 4 3 2 1 0 asim6 power6 txe6 rxe6 ps61 ps60 cl6 sl6 isrm6 power6 enables/disables operati on of internal operation clock 0 note 1 disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit note 2 . txe6 enables/disables transmission 0 disables transmission o peration (synchronously resets the transmission circuit). rxe6 enables/disables reception 0 disables reception (synchronous ly resets the reception circuit). notes 1. the output of the t x d6 pin goes high and the input from the r x d6 pin is fixed to high level when power6 = 0 during transmission. 2. asynchronous serial interface reception error status register 6 (asis6), asynchronous serial interface transmission status register 6 (asif6), bit 7 ( sbrf6) and bit 6 (sbrt6) of asynchronous serial interface control register 6 (asicl6), and receive buffer register 6 (rxb6) are reset. caution clear power6 to 0 after clearing t xe6 and rxe6 to 0 to stop the operation. to start the communication, set power6 to 1, and then set txe6 or rxe6 to 1. remark to use the r x d6/p15 and t x d6/p16 or r x d6/p113 and t x d6/p112 pins as general-purpose port pins, see chapter 4 port functions . chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 438 15.4.2 asynchronous serial interface (uart) mode in this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. a dedicated uart baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates. (1) registers used ? asynchronous serial interface operation mode register 6 (asim6) ? asynchronous serial interface recept ion error status register 6 (asis6) ? asynchronous serial interface transmission status register 6 (asif6) ? clock selection register 6 (cksr6) ? baud rate generator control register 6 (brgc6) ? asynchronous serial interface control register 6 (asicl6) ? input switch control register (isc) ? port mode register 1 (pm1) ? port register 1 (p1) ? port mode register 11 (pm11) ? port register 11 (p11) the basic procedure of setting an operatio n in the uart mode is as follows. <1> set the cksr6 register (see figure 15-8 ). <2> set the brgc6 register (see figure 15-9 ). <3> set bits 0 to 4 (isrm6, sl6, cl6, ps60, ps61) of the asim6 register (see figure 15-5 ). <4> set bits 0 and 1 (txdlv6, di r6) of the asicl6 register (see figure 15-10 ). <5> set bit 7 (power6) of the asim6 register to 1. <6> set bit 6 (txe6) of the asim6 register to 1. transmission is enabled. set bit 5 (rxe6) of the asim6 register to 1. reception is enabled. <7> write data to transmit buffer register 6 (txb6). data transmission is started. caution take relationship with the other party of communication when setting the port mode register and port register. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 439 the relationship between the register settings and pins is shown below. table 15-2. relationship between register settings and pins (a) when the p16 and p15 are selected as the uart6 pins using the bits 4, 5 (isc4, isc5) of the isc register pin function power6 txe6 rxe6 pm16 p16 pm15 p15 uart6 operation t x d6/soa0/p16 r x d6/sia0/p15 0 0 0 note note note note stop soa0/p16 sia0/p15 0 1 note note 1 reception soa0/p16 r x d6 1 0 0 note note transmission t x d6 sia0/p15 1 1 1 0 1 transmission/ reception t x d6 r x d6 note can be set as port function or serial interface csia0. caution txd6/seg18/p112 and rxd6/seg19/p113 pins function as the seg 18/p112 and seg19/p113. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm1 : port mode register p1 : port output latch (b) when the p112 and p113 are selected as the uart6 pins us ing the bits 4, 5 (isc4, isc5) of the isc register pin function power6 txe6 rxe6 pm112 p112 pm113 p113 uart6 operation t x d6/seg18/p112 r x d6/seg19/p113 0 0 0 note note note note stop seg18/p112 seg19/p113 0 1 note note 1 reception seg18/p112 r x d6 1 0 0 1 note note transmission t x d6 seg19/p113 1 1 1 0 1 1 transmission/ reception t x d6 r x d6 note can be set as port function or segment output. caution txd6/soa0/p16 and rxd6/sia0/p15 pi ns function as the soa0/p16 and sia0/p15. remark : don?t care power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 pm11 : port mode register p11 : port output latch chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 440 (2) communication operation (a) format and waveform example of normal transmit/receive data figures 15-15 and 15-16 show the format and waveform example of the normal transmit/receive data. figure 15-15. format of normal uart transmit/receive data 1. lsb-first transmission/reception start bit parity bit d0 d1 d2 d3 d4 1 data frame character bits d5 d6 d7 stop bit 2. msb-first transmission/reception start bit parity bit d7 d6 d5 d4 d3 1 data frame character bits d2 d1 d0 stop bit one data frame consists of the following bits. ? start bit ... 1 bit ? character bits ... 7 or 8 bits ? parity bit ... even parity, odd parity, 0 parity, or no parity ? stop bit ... 1 or 2 bits the character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 (asim6). whether data is communicated with the lsb or msb first is specified by bit 1 (dir6) of asynchronous serial interface control register 6 (asicl6). whether the t x d6 pin outputs normal or inverted data is s pecified by bit 0 (txdlv6) of asicl6. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 441 figure 15-16. example of normal uart transmit/receive data waveform 1. data length: 8 bits, lsb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 parity stop 2. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 3. data length: 8 bits, msb first, parity: even parity, stop bit: 1 bit, communication data: 55h, t x d6 pin inverted output 1 data frame start d7 d6 d5 d4 d3 d2 d1 d0 parity stop 4. data length: 7 bits, lsb first, parity: o dd parity, stop bit: 2 bits, communication data: 36h 1 data frame start d0 d1 d2 d3 d4 d5 d6 parity stop stop 5. data length: 8 bits, lsb first, parity: none, stop bit: 1 bit, communication data: 87h 1 data frame start d0 d1 d2 d3 d4 d5 d6 d7 stop chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 442 (b) parity types and operation the parity bit is used to detect a bit error in communicati on data. usually, the same type of parity bit is used on both the transmission and reception sides. with even parity and odd parity, a 1-bit (odd number) error can be detected. with zero parity and no parity, an error cannot be detected. caution fix the ps61 and ps60 bits to 0 when the device is used in lin communication operation. (i) even parity ? transmission transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is even. the value of the parity bit is as follows. if transmit data has an odd number of bits that are ?1?: 1 if transmit data has an even number of bits that are ?1?: 0 ? reception the number of bits that are ?1? in the receive dat a, including the parity bit, is counted. if it is odd, a parity error occurs. (ii) odd parity ? transmission unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that are ?1? is odd. if transmit data has an odd number of bits that are ?1?: 0 if transmit data has an even number of bits that are ?1?: 1 ? reception the number of bits that are ?1? in the receive data, including the parit y bit, is counted. if it is even, a parity error occurs. (iii) 0 parity the parity bit is cleared to 0 when data is transmitted, regardless of the transmit data. the parity bit is not detected when the data is received. therefore, a parity error does not occur regardless of whether the parity bit is ?0? or ?1?. (iv) no parity no parity bit is appended to the transmit data. reception is performed assuming t hat there is no parity bit when data is received. because there is no parity bit, a parity error does not occur. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 443 (c) normal transmission when bit 7 (power6) of asynchronous serial interface o peration mode register 6 (asim6) is set to 1 and bit 6 (txe6) of asim6 is then set to 1, transmission is enabl ed. transmission can be started by writing transmit data to transmit buffer register 6 (txb6 ). the start bit, parity bit, and stop bit are automatically appended to the data. when transmission is started, the data in txb6 is transferred to transmit sh ift register 6 (txs6). after that, the transmit data is sequentially output from txs6 to the t x d6 pin. when transmission is completed, the parity and stop bits set by asim6 are appended and a transmission completion interrupt request (intst6) is generated. transmission is stopped until the data to be transmitted next is written to txb6. figure 15-17 shows the timing of the transmission comp letion interrupt request (intst6). this interrupt occurs as soon as the last stop bit has been output. figure 15-17. normal transmission comp letion interrupt request timing 1. stop bit length: 1 intst6 d0 start d1 d2 d6 d7 stop t x d6 (output) parity 2. stop bit length: 2 t x d6 (output) intst6 d0 start d1 d2 d6 d7 parity stop chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 444 (d) continuous transmission the next transmit data can be written to transmit buffer re gister 6 (txb6) as soon as transmit shift register 6 (txs6) has started its shift operation. consequently, even while the intst6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized. in addition, the txb6 register can be e fficiently written twice (2 bytes) without having to wait for the transmission time of one data frame, by readi ng bit 0 (txsf6) of asynchronous serial interface transmission status register 6 (asif6) when the transmission completion interrupt has occurred. to transmit data continuously, be sure to reference t he asif6 register to check the transmission status and whether the txb6 register can be written, and then write the data. cautions 1. the txbf6 and txsf6 flags of the asif6 register change from ?10? to ?11?, and to ?01? during continuous transmission. to check the status, therefore, do not use a combination of the txbf6 a nd txsf6 flags for judgment. read only the txbf6 flag when executing continuous transmission. 2. when the device is use in lin communi cation operation, the continuous transmission function cannot be used. m ake sure that asynchronous ser ial interface transmission status register 6 (asif6) is 00h before writin g transmit data to transmit buffer register 6 (txb6). txbf6 writing to txb6 register 0 writing enabled 1 writing disabled caution to transmit data continuously, write the first transmit data (fi rst byte) to the txb6 register. be sure to check that the txbf6 fl ag is ?0?. if so, write the next transmit da ta (second byte) to the txb6 register. if data is written to the txb6 register while the txbf6 flag is ?1?, the transmit data cannot be guaranteed. the communication status can be checked using the txsf6 flag. txsf6 transmission status 0 transmission is completed. 1 transmission is in progress. cautions 1. to initialize the transm ission unit upon completion of continuous transmission, be sure to check that the txsf 6 flag is ?0? after generation of the transmission completion interrupt, and then execute initialization. if initialization is executed while the txsf6 flag is ?1?, the transmit data cannot be guaranteed. 2. during continuous transmi ssion, the next transmission m ay complete before execution of intst6 interrupt servicing after tran smission of one data frame. as a countermeasure, detection can be performe d by developing a program that can count the number of transmit data and by referencing the txsf6 flag. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 445 figure 15-18 shows an example of the continuous transmission processing flow. figure 15-18. example of contin uous transmission processing flow write txb6. set registers. write txb6. transfer executed necessary number of times? yes read asif6 txbf6 = 0? no no yes transmission completion interrupt occurs? read asif6 txsf6 = 0? no no no yes yes yes yes completion of transmission processing transfer executed necessary number of times? remark txb6: transmit buffer register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 (transmit buffer data flag) txsf6: bit 0 of asif6 (trans mit shift register data flag) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 446 figure 15-19 shows the timing of starting continuous transmission, and figure 15-20 shows the timing of ending continuous transmission. figure 15-19. timing of starting continuous transmission t x d6 start intst6 data (1) data (1) data (2) data (3) data (2) data (1) data (3) ff ff parity stop data (2) parity stop txb6 txs6 txbf6 txsf6 start start note note when asif6 is read, there is a period in which t xbf6 and txsf6 = 1, 1. therefore, judge whether writing is enabled using only the txbf6 bit. remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 447 figure 15-20. timing of ending continuous transmission t x d6 start intst6 data (n ? 1) data (n ? 1) data (n) data (n) data (n ? 1) ff parity stop stop data (n) parity stop txb6 txs6 txbf6 txsf6 power6 or txe6 start remark t x d6: t x d6 pin (output) intst6: interrupt request signal txb6: transmit buffer register 6 txs6: transmit shift register 6 asif6: asynchronous serial interface transmission status register 6 txbf6: bit 1 of asif6 txsf6: bit 0 of asif6 power6: bit 7 of asynchronous serial interface operation mode register (asim6) txe6: bit 6 of asynchronous serial interface operation mode register (asim6) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 448 (e) normal reception reception is enabled and the r x d6 pin input is sampled when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is set to 1. the 8-bit counter of the baud rate generator st arts counting when the falling edge of the r x d6 pin input is detected. when the set value of baud rate generator control register 6 (brgc6) has been counted, the r x d6 pin input is sampled again ( in figure 15-21). if the r x d6 pin is low level at this time, it is recognized as a start bit. when the start bit is detected, receptio n is started, and serial data is sequ entially stored in the receive shift register (rxs6) at the set baud rate. when the stop bi t has been received, the reception completion interrupt (intsr6) is generated and the data of rxs6 is written to receive buffer register 6 (rxb6). if an overrun error (ove6) occurs, however, the receiv e data is not written to rxb6. even if a parity error (pe6) occurs while reception is in progress, reception continues to the reception position of the stop bit, and a recept ion error interrupt (intsr6/intsre 6) is generated on completion of reception. figure 15-21. reception completi on interrupt request timing r x d6 (input) intsr6 start d0 d1 d2 d3 d4 d5 d6 d7 parity rxb6 stop cautions 1. if a reception error occu rs, read asis6 and then rxb6 to clear the error flag. otherwise, an overrun error will occur when the next data is r eceived, and the reception error status will persist. 2. reception is always performed with the ?num ber of stop bits = 1? . the second stop bit is ignored. 3. be sure to read asynchro nous serial interface reception e rror status register 6 (asis6) before reading rxb6. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 449 (f) reception error three types of errors may occur during reception: a parity error, framing error, or ov errun error. if the error flag of asynchronous serial interface reception error st atus register 6 (asis6) is set as a result of data reception, a reception error interrupt r equest (intsr6/intsre6) is generated. which error has occurred during reception can be identifi ed by reading the contents of asis6 in the reception error interrupt (intsr6/intsre6) servicing (see figure 15-6 ). the contents of asis6 are cleared to 0 when asis6 is read. table 15-3. cause of reception error reception error cause parity error the parity specifi ed for transmission does not match the parity of the receive data. framing error stop bit is not detected. overrun error reception of the next data is completed before data is read from receive buffer register 6 (rxb6). the reception error interrupt can be separated into reception completion interrupt (intsr6) and error interrupt (intsre6) by clearing bit 0 (isrm6) of asynch ronous serial interface operation mode register 6 (asim6) to 0. figure 15-22. reception error interrupt 1. if isrm6 is cleared to 0 (recep tion completion interr upt (intsr6) and error interrupt (intsre6) are separated) (a) no error during recepti on (b) error during reception intsr6 intsre6 intsr6 intsre6 2. if isrm6 is set to 1 (error interrupt is included in intsr6) (a) no error during recepti on (b) error during reception intsre6 intsr6 intsre6 intsr6 chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 450 (g) noise filter of receive data the rxd6 signal is sampled with the base clock output by the prescaler block. if two sampled values are the same, the output of t he match detector changes, and the data is sampled as input data. because the circuit is configured as shown in figure 15- 23, the internal processing of the reception operation is delayed by two clocks from the external signal status. figure 15-23. noise filter circuit internal signal b internal signal a match detector in base clock r x d6 q in ld_en q (h) sbf transmission when the device is use in lin communication operati on, the sbf (synchronous break field) transmission control function is used for transmission. for the transmission operation of lin, see figure 15-1 lin transmission operation . when bit 7 (power6) of asynchronous serial interf ace mode register 6 (asim6) is set to 1, the t x d6 pin outputs high level. next, when bit 6 (txe6) of asim6 is set to 1, the transmission e nabled status is entered, and sbf transmission is started by setting bit 5 (sbtt6) of asynchronous serial interface control register 6 (asicl6) to 1. thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (sbl62 to sbl60) of asicl6) is output. following the end of sbf transmission, the transmission completi on interrupt request (i ntst6) is generated and sbtt6 is automatically cleared. thereafter, the normal transmission mode is restored. transmission is suspended until the dat a to be transmitted next is written to transmit buffer register 6 (txb6), or until sbtt6 is set to 1. figure 15-24. sbf transmission t x d6 intst6 sbtt6 1 2 3 4 5 6 7 8 9 10 11 12 13 stop remark t x d6: t x d6 pin (output) intst6: transmission completion interrupt request sbtt6: bit 5 of asynchronous serial interface control register 6 (asicl6) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 451 (i) sbf reception when the device is used in lin communication operat ion, the sbf (synchronous break field) reception control function is used for reception. for the reception oper ation of lin, see figure 15-2 lin reception operation . reception is enabled when bit 7 (power6) of asynch ronous serial interface operation mode register 6 (asim6) is set to 1 and then bit 5 (rxe6) of asim6 is se t to 1. sbf reception is enabled when bit 6 (sbrt6) of asynchronous serial interface contro l register 6 (asicl6) is set to 1. in the sbf reception enabled status, the r x d6 pin is sampled and the start bit is detected in the same manner as the normal reception enable status. when the start bit has been detected, reception is started, and serial data is sequentially stored in the receive shift register 6 (rxs6) at the set baud rate. w hen the stop bit is received and if the width of sbf is 11 bits or more, a reception completion interrupt reques t (intsr6) is generated as normal processing. at this time, the sbrf6 and sbrt6 bits are automatical ly cleared, and sbf reception ends. detection of errors, such as ove6, pe6, and fe6 (bits 0 to 2 of as ynchronous serial interface reception error status register 6 (asis6)) is suppressed, and error detection processing of uart communication is not performed. in addition, data transfer between receive shift register 6 (rxs6) and receive buffer register 6 (rxb6) is not performed, and the reset value of ffh is retained. if the width of sbf is 10 bits or less, an interrupt does not occur as error processing after the stop bit has been re ceived, and the sbf reception mode is restored. in this case, the sbrf6 and sbrt6 bits are not cleared. figure 15-25. sbf reception 1. normal sbf reception (stop bit is detect ed with a width of more than 10.5 bits) r x d6 sbrt6 /sbrf6 intsr6 1234567891011 2. sbf reception error (stop bit is detect ed with a width of 10.5 bits or less) r x d6 sbrt6 /sbrf6 intsr6 12345678910 ?0? remark r x d6: r x d6 pin (input) sbrt6: bit 6 of asynchronous serial interface control register 6 (asicl6) sbrf6: bit 7 of asicl6 intsr6: reception completion interrupt request chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 452 15.4.3 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of uart6. separate 8-bit counters are provided for transmission and reception. (1) configuration of ba ud rate generator ? base clock the clock selected by bits 3 to 0 (tps63 to tps60) of clock selectio n register 6 (cksr6) is supplied to each module when bit 7 (power6) of asynchronous serial interface operation mode register 6 (asim6) is 1. this clock is called the base clock and its frequency is called f xclk6 . the base clock is fixed to low level when power6 = 0. ? transmission counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 6 (txe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when power6 = 1 and txe6 = 1. the counter is cleared to 0 when the first data transmi tted is written to transmit buffer register 6 (txb6). if data are continuously transmitted, the counter is cleared to 0 agai n when one frame of data has been completely transmitted. if there is no data to be transmitted next, the count er is not cleared to 0 and continues counting until power6 or txe6 is cleared to 0. ? reception counter this counter stops operation, clear ed to 0, when bit 7 (power6) or bit 5 (rxe6) of asynchronous serial interface operation mode register 6 (asim6) is 0. it starts counting when the start bit has been detected. the counter stops operation after one frame has been received, until the next start bit is detected. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 453 figure 15-26. configuration of baud rate generator selector power6 8-bit counter match detector baud rate baud rate generator brgc6: mdl67 to mdl60 1/2 power6, txe6 (or rxe6) cksr6: tps63 to tps60 f prs f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 f prs /2 8 f prs /2 9 f prs /2 10 8-bit timer/ event counter 50 output f xclk6 remark power6: bit 7 of asynchronous serial interface operation mode register 6 (asim6) txe6: bit 6 of asim6 rxe6: bit 5 of asim6 cksr6: clock selection register 6 brgc6: baud rate generator control register 6 (2) generation of serial clock a serial clock to be generated can be specified by usin g clock selection register 6 (cksr6) and baud rate generator control register 6 (brgc6). the clock to be input to the 8-bit counter can be set by bits 3 to 0 (tps63 to tps60) of cksr6 and the division value (f xclk6 /4 to f xclk6 /255) of the 8-bit counter can be set by bits 7 to 0 (mdl67 to mdl60) of brgc6. chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 454 15.4.4 calculation of baud rate (1) baud rate calculation expression the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk6 : frequency of base clock selected by tps63 to tps60 bits of cksr6 register k: value set by mdl67 to mdl60 bits of brgc6 register (k = 4, 5, 6, ..., 255) table 15-4. set value of tps63 to tps60 base clock (f xclk6 ) selection note 1 tps63 tps62 tps61 tps60 f prs = 2 mhz f prs = 5 mhz f prs = 8 mhz f prs = 10 mhz 0 0 0 0 f prs note 2 2 mhz 5 mhz 8 mhz 10 mhz 0 0 0 1 f prs /2 1 mhz 2.5 mhz 4 mhz 5 mhz 0 0 1 0 f prs /2 2 500 khz 1.25 mhz 2 mhz 2.5 mhz 0 0 1 1 f prs /2 3 250 khz 625 khz 1 mhz 1.25 mhz 0 1 0 0 f prs /2 4 125 khz 312.5 khz 500 khz 625 khz 0 1 0 1 f prs /2 5 62.5 khz 156.25 khz 250 khz 312.5 khz 0 1 1 0 f prs /2 6 31.25 khz 78.13 khz 125 khz 156.25 khz 0 1 1 1 f prs /2 7 15.625 khz 39.06 khz 62.5 khz 78.13 khz 1 0 0 0 f prs /2 8 7.813 khz 19.53 khz 31.25 khz 39.06 khz 1 0 0 1 f prs /2 9 3.906 khz 9.77 khz 15.625 khz 19.53 khz 1 0 1 0 f prs /2 10 1.953 khz 4.88 khz 7.813 khz 9.77 khz 1 0 1 1 tm50 output note 3 other than above setting prohibited notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of tps63 = tps 62 = tps61 = tps60 = 0 (base clock: f prs ) is prohibited. 3. note the following points when selecting the tm50 output as the base clock. ? mode in which the count clock is cleared and started upon a match of tm50 and cr50 (tmc506 = 0) start the operation of 8-bit timer/event counte r 50 first and then enable the timer f/f inversion operation (tmc501 = 1). ? pwm mode (tmc506 = 1) start the operation of 8-bit time r/event counter 50 first and then set the count clock to make the duty = 50%. it is not necessary to enable (toe50 = 1) to50 output in any mode. f xclk6 2 k chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 455 (2) error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] cautions 1. keep the baud rate error during transmission to within th e permissible error range at the reception destination. 2. make sure that the baud rate error dur ing reception satisfies th e range shown in (4) permissible baud rate ra nge during reception. example: frequency of base clock = 10 mhz = 10,000,000 hz set value of mdl67 to mdl60 bits of brgc6 register = 00100001b (k = 33) target baud rate = 153600 bps baud rate = 10 m / (2 33) = 10000000 / (2 33) = 151,515 [bps] error = (151515/153600 ? 1) 100 = ? 1.357 [%] actual baud rate (baud rate with error) desired baud rate (correct baud rate) chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 456 (3) example of setting baud rate table 15-5. set data of baud rate generator f prs = 2.0 mhz f prs = 5.0 mhz f prs = 10.0 mhz baud rate [bps] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] tps63- tps60 k calculated value err [%] 300 8h 13 301 0.16 7h 65 301 0.16 8h 65 301 0.16 600 7h 13 601 0.16 6h 65 601 0.16 7h 65 601 0.16 1200 6h 13 1202 0.16 5h 65 1202 0.16 6h 65 1202 0.16 2400 5h 13 2404 0.16 4h 65 2404 0.16 5h 65 2404 0.16 4800 4h 13 4808 0.16 3h 65 4808 0.16 4h 65 4808 0.16 9600 3h 13 9615 0.16 2h 65 9615 0.16 3h 65 9615 0.16 19200 2h 13 19231 0.16 1h 65 19231 0.16 2h 65 19231 0.16 24000 1h 21 23810 ? 0.79 3h 13 24038 0.16 4h 13 24038 0.16 31250 1h 16 31250 0 4h 5 31250 0 5h 5 31250 0 38400 1h 13 38462 0.16 0h 65 38462 0.16 1h 65 38462 0.16 48000 0h 21 47619 ? 0.79 2h 13 48077 0.16 3h 13 48077 0.16 76800 0h 13 76923 0.16 0h 33 75758 ? 1.36 0h 65 76923 0.16 115200 0h 9 111111 ? 3.55 1h 11 113636 ? 1.36 0h 43 116279 0.94 153600 ? ? ? ? 1h 8 156250 1.73 0h 33 151515 ? 1.36 312500 ? ? ? ? 0h 8 312500 0 1h 8 312500 0 625000 ? ? ? ? 0h 4 625000 0 1h 4 625000 0 remark tps63 to tps60: bits 3 to 0 of clock select ion register 6 (cksr6) (setting of base clock (f xclk6 )) k: value set by mdl67 to mdl60 bits of baud rate generator control register 6 (brgc6) (k = 4, 5, 6, ..., 255) f prs : peripheral hardware clock frequency err: baud rate error chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 457 (4) permissible baud rate range during reception the permissible error from the baud rate at the trans mission destination during reception is shown below. caution make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. figure 15-27. permissible baud rate range during reception fl 1 data frame (11 fl) flmin flmax data frame length of uart6 start bit bit 0 bit 1 bit 7 parity bit minimum permissible data frame length maximum permissible data frame length stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit as shown in figure 15-27, the latch timing of the re ceive data is determined by t he counter set by baud rate generator control register 6 (brgc6) a fter the start bit has been detected. if the last data (stop bit) meets this latch timing, the data can be correctly received. assuming that 11-bit data is received, the theoretical values can be calculated as follows. fl = (brate) ? 1 brate: baud rate of uart6 k: set value of brgc6 fl: 1-bit data length margin of latch timing: 2 clocks chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 458 minimum permissible data frame length: flmin = 11 fl ? fl = fl therefore, the maximum receivable baud rate at the transmission destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, the maximum permissible data fr ame length can be calculated as follows. 10 k + 2 21k ? 2 11 2 k 2 k flmax = fl 11 therefore, the minimum receivable baud rate at the transmission destination is as follows. brmin = (flmax/11) ? 1 = brate the permissible baud rate error between uart6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions, as follows. table 15-6. maximum/minimum permissible baud rate error division ratio (k) maximum perm issible baud rate error minimu m permissible baud rate error 4 +2.33% ? 2.44% 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the permissible error of reception depends on t he number of bits in one frame, input clock frequency, and division ratio (k). the higher t he input clock frequency and the higher the division ratio (k), the higher the permissible error. 2. k: set value of brgc6 22k 21k + 2 flmax = 11 fl ? fl = fl 21k ? 2 20k 20k 21k ? 2 k ? 2 2k 21k + 2 2k chapter 15 serial interface uart6 user?s manual u18329ej4v0ud 459 (5) data frame length during continuous transmission when data is continuously transmitted, th e data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. howeve r, the result of communica tion is not affected because the timing is initialized on the recepti on side when the start bit is detected. figure 15-28. data frame length during continuous transmission start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of second byte start bit bit 0 where the 1-bit data length is fl, the stop bit length is flstp, and base clock frequency is f xclk6 , the following expression is satisfied. flstp = fl + 2/f xclk6 therefore, the data frame length during continuous transmission is: data frame length = 11 fl + 2/f xclk6 user?s manual u18329ej4v0ud 460 chapter 16 serial interface csi10 16.1 functions of serial interface csi10 serial interface csi10 has the following two modes. (1) operation stop mode this mode is used when serial communication is not performed and can enable a reduction in the power consumption. for details, see 16.4.1 operation stop mode . (2) 3-wire serial i/o mode (ms b/lsb-first selectable) this mode is used to communicate 8-bit data using three lines: a serial clock line (sck10) and two serial data lines (si10 and so10). the processing time of data communication can be s hortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is communicated with the msb or lsb first can be specified, so this interface can be connected to any device. the 3-wire serial i/o mode is used for connecting periphe ral ics and display controllers with a clocked serial interface. for details, see 16.4.2 3-wire serial i/o mode . 16.2 configuration of serial interface csi10 serial interface csi10 includes the following hardware. table 16-1. configuration of serial interface csi10 item configuration controller transmit controller clock start/stop controller & clock phase controller registers transmit buffer register 10 (sotb10) serial i/o shift re gister 10 (sio10) control registers serial operation mode register 10 (csim10) serial clock selection register 10 (csic10) port function register 1 (pf1) port mode register 1 (pm1) port register 1 (p1) chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 461 figure 16-1. block diagram of serial interface csi10 internal bus si10/p12/r x d0 intcsi10 transmit buffer register 10 (sotb10) transmit controller clock start/stop controller & clock phase controller serial i/o shift register 10 (sio10) output selector output latch 8 transmit data controller 8 pm11 selector so10/p13/txd0 output latch (p13) pm13 selector uart0 output signal pf13 port function register 1 (pf1) baud rate generator output latch (p11) selector ckp10 serial clock selection register 10 (csic10) f prs /2 f prs /2 2 f prs /2 3 f prs /2 4 f prs /2 5 f prs /2 6 f prs /2 7 sck10/p11 so10 output (1) transmit buffer register 10 (sotb10) this register sets the transmit data. transmission/reception is started by wr iting data to sotb10 when bit 7 (csie 10) and bit 6 (trmd10) of serial operation mode register 10 (csim10) is 1. the data written to sotb10 is converted from parallel data into serial data by serial i/o shift register 10, and output to the serial output pin (so10). sotb10 can be written or read by an 8- bit memory manipulation instruction. reset signal generation sets this register to 00h. caution do not access sotb10 when csot 10 = 1 (during serial communication). (2) serial i/o shift register 10 (sio10) this is an 8-bit register that converts data from parallel data into serial data and vice versa. this register can be read by an 8-bit memory manipulation instruction. reception is started by reading data fr om sio10 if bit 6 (trmd10) of serial operation mode register 10 (csim10) is 0. during reception, the data is read from the serial input pin (si10) to sio10. reset signal generation sets this register to 00h. caution do not access sio10 when csot 10 = 1 (during serial communication). chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 462 16.3 registers controlli ng serial interface csi10 serial interface csi10 is controlled by the following five registers. ? serial operation mode register 10 (csim10) ? serial clock selection register 10 (csic10) ? port function register 1 (pf1) ? port mode register 1 (pm1) ? port register 1 (p1) (1) serial operation mode register 10 (csim10) csim10 is used to select the operation m ode and enable or disable operation. csim10 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 16-2. format of serial oper ation mode register 10 (csim10) address: ff80h after reset: 00h r/w note 1 symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 note 2 operation control in 3-wire serial i/o mode 0 disables operation and asynchronous ly resets the internal circuit note 3 . 1 enables operation trmd10 note 4 transmit/receive mode control 0 note 5 receive mode (transmission disabled). 1 transmit/receive mode dir10 note 6 first bit specification 0 msb 1 lsb csot10 communication status flag 0 communication is stopped. 1 communication is in progress. notes 1. bit 0 is a read-only bit. 2. to use p11/sck10, p12/si10/rxd0, and p13/so10/ txd0 as general-purpose port, clear csie10 to 0. 3. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. 4. do not rewrite trmd10 when csot10 = 1 (during serial communication). 5. the so10 output (see figure 16-1 ) is fixed to the low level when trmd10 is 0. reception is started when data is read from sio10. 6. do not rewrite dir10 when csot10 = 1 (during serial communication). cautions 1. when resuming operation from standby status, do so after having cleared (0) bit 2 (csiif10) of interrupt request flag register 0h (if0h). 2. be sure to clear bit 5 to 0. chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 463 (2) serial clock selecti on register 10 (csic10) this register specifies the timing of the data transmission/reception and sets the serial clock. csic10 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 00h. figure 16-3. format of serial clo ck selection register 10 (csic10) address: ff81h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 csic10 0 0 0 ckp10 dap10 cks102 cks101 cks100 ckp10 dap10 specification of data transmission/reception timing type 0 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 3 1 1 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 si10 input timing 4 csi10 serial clock selection notes 1, 2 cks102 cks101 cks100 f prs = 2 mhz f prs = 5 mhz f prs = 8 mhz f prs = 10 mhz mode 0 0 0 f prs /2 1 mhz 2.5 mhz 4 mhz setting prohibited 0 0 1 f prs /2 2 500 khz 1.25 mhz 2 mhz 2.5 mhz 0 1 0 f prs /2 3 250 khz 625 khz 1 mhz 1.25 mhz 0 1 1 f prs /2 4 125 khz 312.5 khz 500 khz 625 khz 1 0 0 f prs /2 5 62.5 khz 156.25 khz 250 khz 312.5 khz 1 0 1 f prs /2 6 31.25 khz 78.13 khz 125 khz 156.25 khz 1 1 0 f prs /2 7 15.63 khz 39.06 khz 62.5 khz 78.13 khz master mode 1 1 1 external clock input to sck10 slave mode notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 464 notes 2. set the serial clock to satisfy the following conditions. ? v dd = 2.7 to 5.5 v: serial clock 4 mhz ? v dd = 1.8 to 2.7 v: serial clock 2 mhz cautions 1. do not write to csic10 while csie10 = 1 (operation enabled). 2. to use p11/sck10 and p13/so10/t x d0 as general-purpose ports, set csic10 in the default status (00h). 3. the phase type of the data clock is type 1 after reset. remark f prs : peripheral hardware clock oscillation frequency (3) port function register 1 (pf1) this register sets the pin f unctions of p13/so10/txd0 pin. pf1 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pf1 to 00h. figure 16-4. format of port function register 1 (pf1) address: ff20h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pf1 0 pf16 0 0 pf13 0 0 0 pf16 port (p16), csia0, and uart6 output specification 0 used as p16 or soa0 1 used as txd6 pf13 port (p13), csi10, and uart0 output specification 0 used as p13 or so10 1 used as txd0 chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 465 (4) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using p11/sck10 as the clock output pin of the serial interface, clear pm11 to 0, and set the output latches of p11 to 1. when using p13/so10/txd0 as the data output pin of the serial interface, clear pm13 and the output latches of p13 to 0. when using p11/sck10 as the clock input pin of the serial interface and p12/si10/rxd0 as the data input pin, set pm11 and pm12 to 1. at this time, the out put latches of p11 and p12 may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 16-5. format of port mode register 1 (pm1) 7 pm17 6 pm16 5 pm15 4 pm14 3 pm13 2 pm12 1 pm11 0 pm10 symbol pm1 address: ff21h after reset: ffh r/w pm1n 0 1 p1n pin i/o mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 466 16.4 operation of serial interface csi10 serial interface csi10 can be used in the following two modes. ? operation stop mode ? 3-wire serial i/o mode 16.4.1 operation stop mode serial communication is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p11/sc k10, p12/si10/r x d0, and p13/so10/t x d0 pins can be used as ordinary i/o port pins in this mode. (1) register used the operation stop mode is set by serial operation mode register 10 (csim10). to set the operation stop mode, clear bit 7 (csie10) of csim10 to 0. (a) serial operation mode register 10 (csim10) csim10 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets csim10 to 00h. address: ff80h after reset: 00h r/w symbol <7> 6 5 4 3 2 1 0 csim10 csie10 trmd10 0 dir10 0 0 0 csot10 csie10 operation control in 3-wire serial i/o mode 0 disables operation note 1 and asynchronously resets the internal circuit note 2 . notes 1. to use p11/sck10, p12/ si10/rxd0, and p13/so10/t x d0 as general-purpose ports, set csim10 in the default status (00h). 2. bit 0 (csot10) of csim10 and serial i/o shift register 10 (sio10) are reset. 16.4.2 3-wire serial i/o mode the 3-wire serial i/o mode is used for connecting peripheral ics and display controll ers with a clocked serial interface. in this mode, communication is executed by using three lin es: the serial clock (sck10), serial output (so10), and serial input (si10) lines. (1) registers used ? serial operation mode register 10 (csim10) ? serial clock selection register 10 (csic10) ? port mode register 1 (pm1) ? port register 1 (p1) chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 467 the basic procedure of setting an operation in the 3-wire se rial i/o mode is as follows. <1> set the csic10 register (see figures 16-3 ). <2> set bits 4 and 6 (dir10 and trmd10) of the csim10 register (see figures 16-2 ). <3> set bit 7 (csie10) of the csim10 register to 1. transmission/reception is enabled. <4> write data to transmit buffer register 10 (sotb10). data transmission/reception is started. read data from serial i/o shift register 10 (sio10). data reception is started. caution take relationship with the other party of communication when setting the port mode register and port register. the relationship between the register settings and pins is shown below. table 16-2. relationship between register settings and pins pin function csie10 trmd10 pm12 p12 pm13 p13 pm11 p11 csi10 operation si10/rxd0/ p12 so10/ txd0/p13 sck10/ p11 0 note 1 note 1 note 1 note 1 note 1 note 1 stop rxd0/p12 txd0/p13 p11 note 2 1 0 1 note 1 note 1 1 slave reception note 3 si10 txd0/p13 sck10 (input) note 3 1 1 note 1 note 1 0 0 1 slave transmission note 3 rxd0/p12 so10 sck10 (input) note 3 1 1 1 0 0 1 slave transmission/ reception note 3 si10 so10 sck10 (input) note 3 1 0 1 note 1 note 1 0 1 master reception si10 txd0/p13 sck10 (output) 1 1 note 1 note 1 0 0 0 1 master transmission rxd0/p12 so10 sck10 (output) 1 1 1 0 0 0 1 master transmission/ reception si10 so10 sck10 (output) notes 1. can be set as port function. 2. to use p11/sck10 as port pins, clear ckp10 to 0. 3. to use the slave mode, set cks102, cks101, and cks100 to 1, 1, 1. remark : don?t care csie10: bit 7 of serial operation mode register 10 (csim10) trmd10: bit 6 of csim10 ckp10: bit 4 of serial clock selection register 10 (csic10) cks102, cks101, cks100: bits 2 to 0 of csic10 pm1 : port mode register p1 : port output latch chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 468 (2) communication operation in the 3-wire serial i/o mode, data is tr ansmitted or received in 8-bit units. each bit of the dat a is transmitted or received in synchronization with the serial clock. data can be transmitted or received if bit 6 (trmd10) of serial operation mode register 10 (csim10) is 1. transmission/reception is started when a value is writt en to transmit buffer register 10 (sotb10). in addition, data can be received when bit 6 (trmd10) of seri al operation mode register 10 (csim10) is 0. reception is started when dat a is read from serial i/o shift register 10 (sio10). after communication has been started, bit 0 (csot10) of csim10 is set to 1. when communication of 8-bit data has been completed, a communication completion interrupt request flag (csiif10) is set, and csot10 is cleared to 0. then the next communication is enabled. caution do not access the control register and data register when cs ot10 = 1 (during serial communication). figure 16-6. timing in 3-wire serial i/o mode (1/2) (a) transmission/reception ti ming (type 1: trmd10 = 1, di r10 = 0, ckp10 = 0, dap10 = 0) aah abh 56h adh 5ah b5h 6ah d5h 55h (communication data) 55h is written to sotb10. sck10 sotb10 sio10 csot10 csiif10 so10 si10 (receive aah) read/write trigger intcsi10 chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 469 figure 16-6. timing in 3-wire serial i/o mode (2/2) (b) transmission/reception timi ng (type 2: trmd10 = 1, di r10 = 0, ckp10 = 0, dap10 = 1) abh 56h adh 5ah b5h 6ah d5h sck10 sotb10 sio10 csot10 csiif10 so10 si10 (input aah) aah 55h (communication data) 55h is written to sotb10. read/write trigger intcsi10 chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 470 figure 16-7. timing of clock/data phase (a) type 1: ckp10 = 0, dap10 = 0, dir10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (b) type 2: ckp10 = 0, dap10 = 1, dir10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (c) type 3: ckp10 = 1, dap10 = 0, dir10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 (d) type 4: ckp10 = 1, dap10 = 1, dir10 = 0 d7 d6 d5 d4 d3 d2 d1 d0 sck10 so10 writing to sotb10 or reading from sio10 si10 capture csiif10 csot10 remark the above figure illustrates a communication operati on where data is transmitted with the msb first. chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 471 (3) timing of output to so10 pin (first bit) when communication is started, the value of transmit buffe r register 10 (sotb10) is output from the so10 pin. the output operation of the first bit at this time is described below. figure 16-8. output operation of first bit (1/2) (a) type 1: ckp10 = 0, dap10 = 0 sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 first bit 2nd bit output latch (b) type 3: ckp10 = 1, dap10 = 0 sck10 sotb10 sio10 output latch so10 writing to sotb10 or reading from sio10 first bit 2nd bit the first bit is directly latched by the sotb10 register to the output latch at the falling (or rising) edge of sck10, and output from the so10 pin via an output selector. then, the value of the sotb10 regi ster is transferred to the sio10 register at the next rising (or fa lling) edge of sck10, and shifted one bit. at the same time, the first bit of the receive data is stored in the s io10 register via the si10 pin. the second and subsequent bits are latc hed by the sio10 register to the output latch at the next falling (or rising) edge of sck10, and the data is output from the so10 pin. chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 472 figure 16-8. output operation of first bit (2/2) (c) type 2: ckp10 = 0, dap10 = 1 sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 first bit 2nd bit 3rd bit output latch (d) type 4: ckp10 = 1, dap10 = 1 first bit 2nd bit 3rd bit sck10 sotb10 sio10 output latch so10 writing to sotb10 or reading from sio10 the first bit is directly latched by the sotb10 register at the falling edge of the write signal of the sotb10 register or the read signal of the sio10 register, and output from the so10 pin via an output selector. then, the value of the sotb10 register is transfe rred to the sio10 register at the next falling (or rising) edge of sck10, and shifted one bit. at the same time, the first bit of the rece ive data is stored in the sio10 register via the si10 pin. the second and subsequent bits are latc hed by the sio10 register to the out put latch at the next rising (or falling) edge of sck10, and the data is output from the so10 pin. chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 473 (4) output value of so10 pin (last bit) after communication has been completed, the so10 pin holds the output value of the last bit. figure 16-9. output value of so10 pin (last bit) (1/2) (a) type 1: ckp10 = 0, dap10 = 0 sck10 sotb10 sio10 so10 writing to sotb10 or reading from sio10 ( next request is issued.) last bit output latch (b) type 3: ckp10 = 1, dap10 = 0 last bit ( next request is issued.) sck10 sotb10 sio10 output latch so10 writing to sotb10 or reading from sio10 chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 474 figure 16-9. output value of so10 pin (last bit) (2/2) (c) type 2: ckp10 = 0, dap10 = 1 sck10 sotb10 sio10 so10 last bit writing to sotb10 or reading from sio10 ( next request is issued.) output latch (d) type 4: ckp10 = 1, dap10 = 1 last bit ( next request is issued.) sck10 sotb10 sio10 output latch so10 writing to sotb10 or reading from sio10 chapter 16 serial interface csi10 user?s manual u18329ej4v0ud 475 (5) so10 output (see figure 16-1) the status of the so10 output is as follows if bit 7 (csie10) of seri al operation mode register 10 (csim10) is cleared to 0. table 16-3. so10 output status trmd10 dap10 dir10 so10 output note 1 trmd10 = 0 note 2 ? ? outputs low level note 2 dap10 = 0 ? value of so10 latch (low-level output) dir10 = 0 value of bit 7 of sotb10 trmd10 = 1 dap10 = 1 dir10 = 1 value of bit 0 of sotb10 notes 1. the actual output of the so10/p13 pin is determined according to pm13 and p13, as well as the so10 output. 2. status after reset caution if a value is written to trmd10, dap10, and dir10, the output value of so10 changes. user?s manual u18329ej4v0ud 476 chapter 17 serial interface csia0 17.1 functions of serial interface csia0 serial interface csia0 has the following three modes. (1) operation stop mode this mode is used when serial communication is not performed and can enable a reduction in the power consumption. for details, see 17.4.1 operation stop mode . (2) 3-wire serial i/o mode (ms b/lsb-first selectable) this mode is to communicate data successively in 8-bit units, by using three lines: serial clock (scka0) and serial data (sia0 and soa0) lines. the processing time of data communication can be shortened in the 3-wire serial i/o mode because transmission and reception can be simultaneously executed. in addition, whether 8-bit data is communicated msb or lsb first can be specified, so this interface can be connected to any device. for details, see 17.4.2 3-wire serial i/o mode . (3) 3-wire serial i/o mode with automatic transmit/receive functi on (msb/lsb-first selectable) this mode is used to communicate data continuously in 8-bit units using three lines: a serial clock line (scka0) and two serial data lines (sia0 and soa0). the processing time of data communication can be s hortened in the 3-wire serial i/o mode with automatic transmit/receive function because transmission an d reception can be simultaneously executed. in addition, whether 8-bit data is communicated msb or lsb first can be specified, so this interface can be connected to any device. data can be communicated to/from a display driver etc. without using software since a 32-byte transfer buffer ram is incorporated. for details, see 17.4.3 3-wire serial i/o mode with au tomatic transmit/receive function . the features of serial interface csia0 are as follows. ? master mode/slave mode selectable ? communication data length: 8 bits ? msb/lsb-first selectab le for communication data ? automatic transmit/receive function: number of transfer bytes c an be specified between 1 and 32 transfer interval can be specified (0 to 63 clocks) single communication/repeat communication selectable internal 32-byte buffer ram ? on-chip dedicated baud rate generator (6/8/16/32 divisions) ? 3-wire soa0: serial data output sia0: seri al data input scka0: serial clock i/o ? transmission/reception completion interrupt: intacsi chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 477 17.2 configuration of serial interface csia0 serial interface csia0 consists of the following hardware. table 17-1. configuration of serial interface csia0 item configuration controller serial transfer controller registers serial i/o sh ift register 0 (sioa0) control registers serial operation mode specification register 0 (csima0) serial status register 0 (csis0) serial trigger register 0 (csit0) divisor selection register 0 (brgca0) automatic data transfer address point specification register 0 (adtp0) automatic data transfer interval specification register 0 (adti0) automatic data transfer address count register 0 (adtc0) port function register 1 (pf1) port mode register 1 (pm1) port register 1 (p1) chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 478 figure 17-1. block diagram of serial interface csia0 internal bus baud rate generator selector master0 p14 pm14 scka0/p14 sia0/p15 dir0 ate0 6-bit counter buffer ram interrupt generator serial transfer controller atm0 serial clock counter atstp0 atsta0 tsf0 automatic data transfer address point specification register 0 (adtp0) automatic data transfer address count register 0 (adtc0) divisor selection register 0 (brgca0) serial i/o shift register 0 (sioa0) automatic data transfer interval specification register 0 (adti0) intacsi rxae0 2 serial trigger register 0 (csit0) serial status register 0 (csis0) cks000 atm0 master0 txea0 rxea0 dir0 ate0 csiae0 serial operation mode specification register 0 (csima0) internal bus selector uart6 output signal port function register 1 (pf1) selector f w /6 to f w /32 f prs f prs /2 f w pm16 soa0/p16 txae0 p16 pf16 chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 479 (1) serial i/o shift register 0 (sioa0) this is an 8-bit register used to store transmit/receive data in 1-byte transfer mode (bit 6 (ate0) of serial operation mode specification regist er 0 (csima0) = 0). writing transmit data to sioa0 starts the communication. in addition, after a communication completion interrupt r equest (intacsi) is output (bit 0 (tsf0) of serial status register 0 (csis0) = 0), data can be received by reading data from sioa0. this register can be written or read by an 8-bit memory manipulation instruction. however, writing to sioa0 is prohibited when bit 0 (tsf0) of seri al status register 0 (csis0) = 1. reset signal generation clears this register to 00h. cautions 1. a communication opera tion is started by writing to sioa0. consequently, when transmission is disabled (bit 3 (txea0) of cs ima0 = 0), write dummy data to the sioa0 register to start the communication operati on, and then perform a receive operation. 2. do not write data to sioa0 while the au tomatic transmit/receive function is operating. 17.3 registers controlling serial interface csia0 serial interface csia0 is controlle d by the following ten registers. ? serial operation mode specif ication register 0 (csima0) ? serial status register 0 (csis0) ? serial trigger register 0 (csit0) ? divisor selection register 0 (brgca0) ? automatic data transfer address point specification register 0 (adtp0) ? automatic data transfer interval specification register 0 (adti0) ? automatic data transfer address count register 0 (adtc0) ? port function register 1 (pf1) ? port mode register 1 (pm1) ? port register 1 (p1) chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 480 (1) serial operation mode speci fication register 0 (csima0) this is an 8-bit register used to cont rol the serial communication operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 17-2. format of serial operation mode specification register 0 (csima0) csiae0 csia0 operation disabled (soa0: low level, scka0: high level) and asynchronously resets the internal circuit note . csia0 operation enabled csiae0 0 1 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 1-byte communication mode automatic communication mode ate0 0 1 control of automatic communication operation enable/disable single transfer mode (stops at the address specified by the adtp0 register) repeat transfer mode (after transfer is complete, clear the adtc0 register to 00h to resume transfer) atm0 0 1 automatic communication mode specification slave mode (synchronous with scka0 input clock) master mode (synchronous with internal clock) master0 0 1 csia0 master/slave mode specification transmit operation disabled (soa0: low level) txea0 0 1 control of transmit operation enable/disable receive operation disabled receive operation enabled rxea0 0 1 control of receive operation enable/disable msb lsb dir0 0 1 first bit specification address: ff90h after reset: 00h r/w transmit operation enabled symbol < > < > < > note automatic data transfer address count register 0 (adtc0 ), serial trigger register 0 (csit0), serial i/o shift register 0 (sioa0), and bit 0 (tsf0) of serial status register 0 (csis0) are reset. cautions 1. when csiae0 = 0, the buffer ram cannot be accessed. 2. when csiae0 is changed from 1 to 0, th e registers and bits mentioned in note above are asynchronously initialized. to set csiae0 = 1 again, be sure to re-set the initialized registers. 3. when csiae0 is re-set to 1 after csiae0 is changed from 1 to 0, it is not guaranteed that the value of the buffer ram will be retained. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 481 (2) serial status register 0 (csis0) this is an 8-bit register used to select the base clo ck, control the communication operation, and indicate the status of serial interface csia0. this register can be set by a 1-bit or 8-bit memory m anipulation instruction. ho wever, rewriting csis0 is prohibited when bit 0 (tsf0) is 1. reset signal generation clears this register to 00h. figure 17-3. format of serial status register 0 (csis0) 0 csis0 symbol cks00 0 0 0 0 0 tsf0 f prs note 3 f prs /2 f prs = 2 mhz 2 mhz 1 mhz f prs = 5 mhz 5 mhz 2.5 mhz f prs = 8 mhz 8 mhz 4 mhz f prs = 10 mhz 10 mhz 5 mhz cks00 0 1 base clock (f w ) selection note 2 address: ff91h after reset: 00h r/w note 1 43 21 0 6 75 ? bit 7 (csiae0) of serial operation mode specification register 0 (csima0) = 0 ? at reset input ? at the end of the specified transfer ? when transfer is stopped by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1 from the transfer start to the end of the specified transfer tsf0 0 1 transfer status detection flag notes 1. bit 0 is read-only. 2. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 3. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of cks00 = 0 (base clock: f prs ) is prohibited. cautions 1. be sure to clear bits 7 and 5 to 1. 2. during transfer (tsf0 = 1), rewriting serial operation mode specification register 0 (csima0), serial status register 0 (csis0), divisor sel ection register 0 (brgca0), automatic data transfer address point specification register 0 (adtp0), automatic data transfer interval specification register 0 (adti0), and serial i/o shift register 0 (sioa0) are prohibited. however, these registers can be read and re-w ritten to the same value. in addition, the buffer ram can be rewr itten during transfer. remark f prs : peripheral hardware clock frequency chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 482 (3) serial trigger register 0 (csit0) this is an 8-bit register used to control executi on/stop of automatic data tr ansfer between buffer ram and serial i/o shift register 0 (sioa0). this register can be set by a 1-bit or 8-bit memory mani pulation instruction. this register can be set when bit 6 (ate0) of serial operation mode spec ification register 0 (csima0) is 1. reset signal generation clears this register to 00h. figure 17-4. format of serial trigger register 0 (csit0) 0 csit0 symbol 0 0 0 0 0 atstp0 atsta0 automatic data transfer stopped atstp0 0 1 automatic data transfer stop automatic data transfer started atsta0 0 1 automatic data transfer start address: ff92h after reset: 00h r/w 4 3 2 <1> <0> 6 75 ? ? cautions 1. even if atstp0 or atsta0 is set to 1, automatic transfer cannot be started/stopped until 1- byte transfer is complete. 2. atstp0 and atsta0 change to 0 automatically after th e interrupt signal intacsi is generated. 3. after automatic data transfer is stopped, the data address when the transfer stopped is stored in automatic data transfer address c ount register 0 (adtc0). however, since no function to restart automatic data transfer is incorporated, when transfer is stopped by setting atstp0 = 1, start automa tic data transfer by setting at sta0 to 1 after re-setting the registers. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 483 (4) divisor selection register 0 (brgca0) this is an 8-bit register used to select the base clock divisor of csia0. this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting brgca0 is prohibited. reset signal generation sets this register to 03h. figure 17-5. format of divisor selection register 0 (brgca0) 0 brgca0 symbol 0 0 0 0 0 brgca01 brgca00 brgca01 0 0 1 1 brgca00 0 1 0 1 selection of base clock (f w ) divisor of csia0 note f w /6 f w /2 3 f w /2 4 f w /2 5 166.67 khz 125 khz 62.5 khz 31.25 khz 333.3 khz 250 khz 125 khz 62.5 khz 416.67 khz 312.5 khz 156.25 khz 78.125 khz 833.33 khz 625 khz 312.5 khz 156.25 khz f w = 1 mhz f w = 2 mhz f w = 5 mhz f w = 2.5 mhz address: ff93h after reset: 03h r/w 43 21 0 6 75 1.67 mhz 1.25 mhz 625 khz 312.5 khz f w = 10 mhz note set the transfer clock so as to satisfy the following conditions. ? when 2.7 v v dd < 4.0 v: transfer clock 833.33 khz ? when 1.8 v v dd < 2.7 v: transfer clock 555.56 khz remark f w : base clock frequency selected by cks00 bit of csis0 register f prs : peripheral hardware clock frequency chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 484 (5) automatic data transfer address point specification register 0 (adtp0) this is an 8-bit register used to specify the buffe r ram address that ends transfer during automatic data transfer (bit 6 (ate0) of serial operation mo de specification register 0 (csima0) = 1). this register can be set by an 8-bit memory manipulatio n instruction. however, during transfer (tsf0 = 1), rewriting adtp0 is prohibited. in the 78k0/lf3, 00h to 1fh c an be specified because 32 bytes of buffer ram are incorporated. example when adtp0 is set to 07h 8 bytes of fa00h to fa07h are transferred. in repeat transfer mode (bit 5 (atm0) of csima0 = 1), transfer is performed repeatedly up to the address specified with adtp0. example when adtp0 is set to 07h (repeat transfer mode) transfer is repeated as fa00h to fa07h, fa00h to fa07h, ? . figure 17-6. format of automatic data transfer address point specificat ion register 0 (adtp0) 0 adtp0 0 0 adtp04 adtp03 adtp02 adtp01 adtp00 address: ff94h after reset: 00h r/w symbol 43 21 0 6 75 caution be sure to clea r bits 7 to 5 to ?0?. the relationship between transfer end buffer ram address values and adtp0 setting values is shown below. table 17-2. relationship between transfer end buffer ram address values and adtp0 setting values transfer end buffer ram address value adtp0 setting value faxxh xxh remark xx: 00 to 1f chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 485 (6) automatic data transfer inter val specification register 0 (adti0) this is an 8-bit register used to specify the interval time for byte data transfer during automatic data transfer (bit 6 (ate0) of serial operation mode specification register 0 (csima0) = 1). set this register when in master mode (bit 4 (master0) of csima0 = 1) (setting is unnecessary in slave mode). setting in 1-byte communication mode (bit 6 (ate0) of csima0 = 0) is also valid. when the interval time specified by adti0 after the end of 1-byte communication has elapsed, an interrupt request signal (intacsi) is output. the number of clocks for t he interval can be set to between 0 and 63 clocks. this register can be set by an 8-bit memory manipulation instruction. however, when bit 0 (tsf0) of serial status register 0 (csis0) is 1, rewriting adti0 is prohibited. figure 17-7. format of automatic data transf er interval specificatio n register 0 (adti0) 0 adti0 0 adti05 adti04 adti03 adti02 adti01 adti00 address: ff95h after reset: 00h r/w symbol 43 21 0 6 75 the specified interval time is the serial clock (specifie d by divisor selection register 0 (brgca0)) multiplied by an integer value. example when adti0 = 03h scka0 interval time of 3 clocks chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 486 (7) automatic data transfer a ddress count register 0 (adtc0) this is a register used to indicate buffer ram addresses during automatic transfer. when automatic transfer is stopped, the data position when transfer stopped can be ascertained by reading adtc0 register value. this register can be read by an 8-bi t memory manipulation instruction. reset signal generation clears this register to 00h. however, reading from adtc0 is prohibited when bit 0 (tsf0) of serial status register 0 (csis0) = 1. figure 17-8. format of automatic data tr ansfer address count register 0 (adtc0) 0 adtc0 0 0 adtc04 adtc03 adtc02 adtc01 adtp00 address: ff97h after reset: 00h r symbol 43 21 0 6 75 (8) port function register 1 (pf1) this register sets the pin f unctions of p16/soa0/txd6 pin. pf1 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pf1 to 00h. figure 17-9. format of port function register 1 (pf1) address: ff20h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pf1 0 pf16 0 0 pf13 0 0 0 pf16 port (p16), csia0, and uart6 output specification 0 used as p16 or soa0 1 used as txd6 pf13 port (p13), csi10, and uart0 output specification 0 used as p13 or so10 1 used as txd0 chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 487 (9) port mode register 1 (pm1) this register sets port 1 input/output in 1-bit units. when using p14/scka0 pin as the clock output of the serial interface, clear pm14 to 0 and set the output latch of p14 to 1. when using p16/soa0 pin as the data output of the serial interface, cl ear pm16 and the output latches of p16 to 0. when using p14/scka0 and p15/sia0 pins as the clock i nput, or data input of the serial interface, set pm14 and pm15 to 1. at this time, the output latches of p14 and p15 may be 0 or 1. pm1 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. figure 17-10. format of port mode register 1 (pm1) address: ff21h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm1 pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm1n p1n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 488 17.4 operation of serial interface csia0 serial interface csia0 has the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 17.4.1 operation stop mode serial communication is not executed in this mode. therefore, the power consumption can be reduced. in addition, the p14/scka0, p15/sia0, and p16/ soa0 pins can be used as ordinary i/o port pins in this mode. (1) register used the operation stop mode is set by serial operation mode specification register 0 (csima0). to set the operation stop mode, clear bit 7 (csiae0) of csima0 to 0. (a) serial operation mode speci fication register 0 (csima0) this is an 8-bit register used to cont rol the serial communication operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. csiae0 csia0 operation disabled (soa0: low level, scka0: high level) and asynchronously resets the internal circuit csiae0 0 control of csia0 operation enable/disable csima0 ate0 atm0 master0 txea0 rxea0 dir0 0 address: ff90h after reset: 00h r/w < > < > < > chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 489 17.4.2 3-wire serial i/o mode the one-byte data transmission/reception is executed in the mode in which bit 6 (ate0) of serial operation mode specification register 0 (csima0) is cleared to 0. the 3-wire serial i/o mode is useful for connecting peripher al ics and display controllers with a clocked serial interface. in this mode, communication is executed by using three lines: serial clock (scka0), serial output (soa0), and serial input (sia0) lines. (1) registers used ? serial operation mode specif ication register 0 (csima0) note 1 ? serial status register 0 (csis0) note 2 ? divisor selection register 0 (brgca0) ? port mode register 1 (pm1) ? port register 1 (p1) notes 1. bits 7, 6, and 4 to 1 (csiae0, ate0, master0, txea0, rxea0, and dir0) are used. setting of bit 5 (atm0) is invalid. 2. only bit 0 (tsf0) and bit 6 (cks00) are used. the basic procedure of setting an operation in the 3-wire se rial i/o mode is as follows. <1> set bit 6 (cks00) of the csis0 register (see figure 17-3 ) note 1 . <2> set the brgca0 register (see figure 17-5 ) note 1 . <3> set bits 4 to 1 (master0, txea0, rxea0 , and dir0) of the csima0 register (see figure 17-2 ). <4> set bit 7 (csiae0) of the csima0 register to 1 and clear bit 6 (ate0) to 0. <5> write data to serial i/o shift register 0 (sioa0). data transmission/reception is started note 2 . notes 1. this register does not have to be set when the slave mode is specified (master0 = 0). 2. write dummy data to sioa0 only for reception. caution take relationship with the other part y of communication when setting the port mode register and port register. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 490 the relationship between the register settings and pins is shown below. table 17-3. relationship between register settings and pins pin function csiae0 ate0 master0 pm 15 p15 pm16 p16 pm14 p14 serial i/o shift register 0 operation serial clock counter operation control sia0/p15 soa0/p16 scka0/p14 /intp4 0 note 1 note 1 note 1 note 1 note 1 note 1 operation stopped clear p15 p16 p14/intp4 0 1 scka0 (input) 1 0 1 1 note 2 note 2 0 note 3 0 note 3 0 1 operation enabled count operation sia0 note 2 soa0 note 3 scka0 (output) notes 1. can be set as port function. 2. can be used as p15 when only transmission is performed. clear bit 2 (rxea0) of csima0 to 0. 3. can be used as p16 when only reception is per formed. clear bit 3 (txea0) of csima0 to 0. remark : don?t care csiae0: bit 7 of serial operation mo de specification register 0 (csima0) ate0: bit 6 of csima0 master0: bit 4 of csima0 pm1 : port mode register p1 : port output latch chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 491 (2) 1-byte transmission/recep tion communication operation (a) 1-byte transmission/reception when bit 7 (csiae0) and bit 6 (ate0) of serial operatio n mode specification regist er 0 (csima0) = 1, 0, respectively, if communication data is written to serial i/o shift register 0 (sioa0), the data is output via the soa0 pin in synchronization with the scka0 fal ling edge, and stored in the sioa0 register in synchronization with the rising edge 1 clock later. data transmission and data reception can be performed simultaneously. if only reception is to be performed, communication can only be started by writing a dummy value to the sioa0 register. when communication of 1 byte is complete, an inte rrupt request signal (intacsi) is generated. in 1-byte transmission/reception, the setting of bit 5 (atm0) of csima0 is invalid. be sure to read data after confirming that bit 0 (t sf0) of serial status register 0 (csis0) = 0. figure 17-11. 3-wire serial i/o mode timing 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 end of transfer transfer starts at falling edge of scka0 scka0 sia0 soa0 acsiif tsf0 sioa0 write caution the soa0 pin becomes lo w level by an sioa0 write. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 492 (b) data format in the data format, data is changed in synchroniza tion with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the dat a communication direction can be switched by the specification of bit 1 (dir0) of serial oper ation mode specification register 0 (csima0). figure 17-12. format of transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7 chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 493 (c) switching msb/lsb as start bit figure 17-13 shows the configuration of serial i/o shi ft register 0 (sioa0) and the internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. switching msb/lsb as the start bi t can be specified using bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-13. transfer bit order switching circuit 7 6 internal bus 1 0 lsb-first msb-first read/write gate sia0 shift register 0 (sioa0) read/write gate soa0 scka0 dq soa0 latch start bit switching is realized by switching the bit or der for data written to sioa0. the sioa0 shift order remains unchanged. thus, switching between msb-first and lsb-first mu st be performed before wr iting data to the shift register. (d) communication start serial communication is st arted by setting communication data to se rial i/o shift register 0 (sioa0) when the following two conditions are satisfied. ? serial interface csia0 operation control bit (csiae0) = 1 ? serial communication is not in progress caution if csiae0 is set to 1 after data is writte n to sioa0, communication does not start. upon termination of 8-bit communication, serial comm unication automatically stops and the interrupt request flag (acsiif) is set. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 494 17.4.3 3-wire serial i/o mode with au tomatic transmit/receive function up to 32 bytes of data can be transmi tted/received without using software in the mode in which bit 6 (ate0) of serial operation mode specification register 0 (csima0) is set to 1. after comm unication is started, only data of the set number of bytes stored in ram in advance can be trans mitted, and only data of the se t number of bytes can be received and stored in ram. (1) registers used ? serial operation mode specif ication register 0 (csima0) ? serial status register 0 (csis0) ? serial trigger register 0 (csit0) ? divisor selection register 0 (brgca0) ? automatic data transfer address point specification register 0 (adtp0) ? automatic data transfer interval specification register 0 (adti0) ? port mode register 1 (pm1) ? port register 1 (p1) the relationship between the register settings and pins is shown below. caution a wait state may be generated when data is written to the buffe r ram. for details, see chapter 34 cautions for wait. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 495 the relationship between the register settings and pins is shown below. table 17-4. relationship between register settings and pins pin function csiae0 ate0 master0 pm 15 p15 pm16 p16 pm14 p14 serial i/o shift register 0 operation serial clock counter operation control sia0/p15 soa0/p16 scka0/p14 /intp4 0 note 1 note 1 note 1 note 1 note 1 note 1 operation stopped clear p15 p16 p14/intp4 0 1 scka0 (input) 1 0 1 1 note 2 note 2 0 note 3 0 note 3 0 1 operation enabled count operation sia0 note 2 soa0 note 3 scka0 (output) notes 1. can be set as port function. 2. can be used as p15 when only transmission is performed. clear bit 2 (rxea0) of csima0 to 0. 3. can be used as p16 when only reception is per formed. clear bit 3 (txea0) of csima0 to 0. remark : don?t care csiae0: bit 7 of serial operation mo de specification register 0 (csima0) ate0: bit 6 of csima0 master0: bit 4 of csima0 pm1 : port mode register p1 : port output latch chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 496 (2) automatic transmit/receive data setting here is an example of the procedure for successi vely transmitting/receiving data as the master. <1> enable csia0 to operate by setting bit 7 (csiae0) of serial operation mode specification register 0 (csima0) to 1 (the buffer ram can now be accessed). <2> select a serial clock by using serial status register 0 (csis0). <3> set the division ratio of the serial clock by using division value selection register 0 (brgca0), and specify a communication rate. <4> sequentially write data to be tr ansmitted to the buffer ram, starting from the least significant address fa00h, up to fa1fh. data is transmitted from the lo west address, continuing on to higher addresses. <5> set ?number of data items to be transmitted ? 1? to automatic data transfe r address point specification register 0 (adtp0). <6> set bits 6 (ate0) and 4 (master0) of csima0 to select a master oper ation in the automatic communication mode. <7> set bits 3 (txea0) and 2 (rxea0) of csim a0 to 1 to enable transmission/reception. <8> set the transmission interval of data to the autom atic data transfer interval specification register (adti0). <9> automatic transmit/receive processing is started w hen bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1. caution take the relationship with the other co mmunicating party into consideration when setting the port mode regi ster and port register. operations <1> to <9> exec ute the following operation. ? after the buffer ram data indicated by automatic data transfer address count register 0 (adtc0) is transferred to sioa0, transmission is carried out (start of automatic transmission/reception). ? the received data is written to the buffer ram address indicated by adtc0. ? adtc0 is incremented and the next data tr ansmission/reception is carried out. data transmission/reception continues until the adtc0 incremental output matches the set value of automatic data transfer address point specific ation register 0 (adtp0 ) (end of automatic transmission/reception). however, if bit 5 (atm0) of csima0 is set to 1 (repeat mode), adtc0 is cleared after a match between adtp0 and adtc 0, and then repeated transmission/reception is started. ? when automatic transmission/recept ion is terminated, an interrupt request (intacsi) is generated and bit 0 (tsf0) of csis0 is cleared. ? to continue transmitting the next data, set the new data to the buffer ram, and set ?number of data to be transmitted ? 1? to adtp0. after setting the number of data, set atsta0 to 1. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 497 (3) automatic transmission/re ception communication operation (a) automatic transmi ssion/reception mode automatic transmission/reception can be performed using buffer ram. the data stored in the buffer ram is output from the soa0 pin via the sioa0 register in synchronization with the scka0 falling edge by performing (2) automatic transmit/receive data setting . the receive data is stored in the buffer ram via the sioa0 register in synchronization with the scka0 rising edge. data transfer ends if bit 0 (tsf0) of serial status register 0 (csis0) is set to 1 when any of the following conditions is met. ? communication stop: reset by clearing bi t 7 (csiae0) of the csima0 register to 0 ? communication suspension: transfer of 1 byte is complete by setting bit 1 (atstp0) of the csit0 register to 1 ? transfer of the range specified by the adtp0 register is complete at this time, an interrupt request signal (intacsi ) is generated except when the csiae0 bit = 0. if a transfer is terminated in the middle, transfer star ting from the remaining data is not possible. read automatic data transfer address count register 0 (adt c0) to confirm how much of the data has already been transferred and re-execute transfer by performing (2) automatic transmit/receive data setting . figure 17-14 shows the example of the operation timing in automatic transmission/reception mode and figure 17-15 shows the operation flowchart. figures 17-16 and 17-17 show the operation of internal buffer ram when 6 bytes of data are transmitted/received. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 498 figure 17-14. example of automatic transm ission/reception mode operation timings scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval cautions 1. because, in th e automatic transmission/r eception mode, the automatic transmit/receive function writes/reads data to/from the internal buffer ram after 1- byte transmission/reception, an in terval is inserted until the next transmission/reception. as the buffer ram write/read is performed at the same time as cpu processing, the interval is depende nt upon the set value of automatic data transfer interval specificat ion register 0 (adti0). 2. if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the inte rval time specified by automatic data transfer interval specifi cation register 0 (adti0) may be extended. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 499 figure 17-15. automatic transm ission/reception mode flowchart start set csiae0 to 1 set the communication speed write transmit data in internal buffer ram note set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the automatic transmission/reception mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission/reception operation write receive data from sioa0 to internal buffer ram note adtp0 = adtc0 no tsf0 = 0 no end yes yes increment adtc0 software execution hardware execution software execution csiae0: bit 7 of serial operation mode specification register 0 (csima0) adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0) note a wait state may be generated when data is wr itten to the buffer ram. for details, see chapter 34 cautions for wait . chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 500 in 6-byte transmission/reception (atm0 = 0, rxea0 = 1, txea0 = 1, ate0 = 1) in automatic transmission/reception mode, internal buffer ram operates as follows. (i) starting automatic transmi ssion/reception (see figure 17-16) <1> when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1, transmit data 1 (t1) is transferred from the internal buffer ram to sioa0 and transmission/reception is started. <2> when transmission of the first byte is comple ted, the receive data 1 (r 1) is transferred from sioa0 to the buffer ram, and automatic data tr ansfer address count register 0 (adtc0) is incremented. <3> next, transmit data 2 (t2) is transferred from the internal buffer to sioa0. figure 17-16. internal buffer ram operation in automatic transmi ssion/reception mode (starting transmission/reception) (1/2) <1> starting 1st byte transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) 0 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) 0 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h transmit data 1 (t1) data transmission chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 501 figure 17-16. internal buffer ram operation in automatic transmi ssion/reception mode (starting transmission/reception) (2/2) <2> end of 1st byte transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) transmit data 1 (t1) 0 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 1 (r1) data reception +1 <3> starting of 2nd by te transmission/reception transmit data 6 (t6) transmit data 5 (t5) transmit data 4 (t4) transmit data 3 (t3) transmit data 2 (t2) receive data 1 (r1) 1 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 1 (r1) (ii) completion of transmissi on/reception (see figure 17-17) <1> when transmission/reception of the sixth byte is completed, re ceive data 6 (r6) is transferred from sioa0 to the internal buffer ram and adtc0 is incremented. <2> when the value of adpt0 and that of adtc 0 match, the automatic transmission/reception ends, and an interrupt request flag (acsiif) is set (intacsi is generated). adtc0 and bit 0 (tsf0) of serial status regist er 0 (csis0) are cleared to 0. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 502 figure 17-17. internal buffer ram operation in automatic transmi ssion/reception mode (end of transmission/reception) <1> end of 6th byte transmission/reception transmit data 6 (t6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) 4 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 6 (r6) data reception +1 <2> end of automatic transmission/reception 5 0 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) receive data 6 (r6) match 5 1 sioa0 adtc0 5 adtp0 acsiif fa1fh fa05h fa00h receive data 6 (r6) receive data 5 (r5) receive data 4 (r4) receive data 3 (r3) receive data 2 (r2) receive data 1 (r1) receive data 6 (r6) chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 503 (b) automatic transmission mode in this mode, the specified data is transmitted in 8-bit unit. serial communication is started when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), and bit 3 (txea0) of serial operation mode s pecification register 0 (csima0) are set to 1. when the final byte has been transmitted, an interrupt request flag (acsiif) is set. the termination of automatic transmission can also be judged by bit 0 (tsf0) of serial status register 0 (csis0). if a receive operation, busy control and strobe control are not executed, the sia0 /p15 pin can be used as normal i/o port pins. figure 17-18 shows the example of the automatic transmission mode operation timing, and figure 17-19 shows the operation flowchart. figure 17-18. example of automatic transmission mode operation timing scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 acsiif tsf0 interval cautions 1. because, in the automatic transmission mode, th e automatic transmit/receive function reads data from the internal bu ffer ram after 1-byte transmission, an interval is inserted until the next transmissi on. as the buffer ram read is performed at the same time as cpu processi ng, the interval is depende nt upon the set value of automatic data transfer interval specification register 0 (adti0). 2. if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the inte rval time specified by automatic data transfer interval specifi cation register 0 (adti0) may be extended. remark acsiif: interrupt request flag tsf0: bit 0 of serial status register 0 (csis0) chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 504 figure 17-19. automatic tr ansmission mode flowchart start set csiae0 to 1 set the communication rate write transmit data in internal buffer ram note set adtp0 to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the automatic transmission mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no tsf0 = 0 no end yes yes increment adtc0 software execution hardware execution software execution csiae0: bit 7 of serial operation mode specification register 0 (csima0) adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 tsf0: bit 0 of serial status register 0 (csis0) note a wait state may be generated when data is wr itten to the buffer ram. for details, see chapter 34 cautions for wait . chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 505 (c) repeat transmission mode in this mode, data stored in the internal buffer ram is transmitted repeatedly. serial communication is started when bit 0 (atsta0) of serial trigger register 0 (csit0) is set to 1 while bit 7 (csiae0), bit 6 (ate0), bit 5 (atm0), and bit 3 (txea0) of serial operat ion mode specification register 0 (csima0) are set to 1. unlike the automatic transmission mode, after the number of setting bytes has been transmitted, the interrupt request flag (acsiif) is not set, automat ic data transfer address count register 0 (adtc0) is reset to 0, and the internal buffer ram contents are transmitted again. when a reception operation, busy c ontrol and strobe control are not performed, the sia0/p15 pin can be used as ordinary i/o port pins. the example of the repeat transmission mode operation timing is shown in figure 17-20, and the operation flowchart in figure 17-21. figure 17-20. example of repeat transmission mode operation timing d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 scka0 soa0 cautions 1. because, in the re peat transmission mode, a read is performed on the buffer ram after the transmission of one byte, the inte rval is included in the period up to the next transmission. as the buffer ram re ad is performed at the same time as cpu processing, the interval is de pendent upon the set value of automatic data transfer interval specification register 0 (adti0). 2. if an access to the buffer ram by the cpu conflicts with an access to the buffer ram by serial interface csia0 during the inte rval period, the inte rval time specified by automatic data transfer interval specifi cation register 0 (adti0) may be extended. chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 506 figure 17-21. repeat transmission mode flowchart start set csiae0 to 1 set the communication rate write transmit data in internal buffer ram note set adtp0 to the value (point value) obtained by subtracting 1 from the number of transmit data bytes set the repeat transmission mode set atsta0 to 1 write transmit data from internal buffer ram to sioa0 transmission operation adtp0 = adtc0 no yes increment adtc0 software execution hardware execution reset adtc0 to 0 csiae0: bit 7 of serial operation mode specification register 0 (csima0) adtp0: automatic data transfer addre ss point specification register 0 adti0: automatic data transfer inte rval specification register 0 atsta0: bit 0 of serial trigger register 0 (csit0) sioa0: serial i/o shift register 0 adtc0: automatic data transfer address count register 0 note a wait state may be generated when data is wr itten to the buffer ram. for details, see chapter 34 cautions for wait . chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 507 (d) data format data is changed in synchronization with the scka0 falling edge as shown below. the data length is fixed to 8 bits and the data transfer direction can be sw itched by the spec ification of bit 1 (dir0) of serial operation mode specification register 0 (csima0). figure 17-22. format of csia0 transmit/receive data (a) msb-first (dir0 bit = 0) scka0 sia0 do7 do6 do5 do4 do3 do2 do1 do0 soa0 di7 di6 di5 di4 di3 di2 di1 di0 (b) lsb-first (dir0 bit = 1) scka0 sia0 do0 do1 do2 do3 do4 do5 do6 do7 soa0 di0 di1 di2 di3 di4 di5 di6 di7 chapter 17 serial interface csia0 user?s manual u18329ej4v0ud 508 (e) automatic transmission/rece ption suspension and restart automatic transmission/reception can be temporarily suspended by setting bit 1 (atstp0) of serial trigger register 0 (csit0) to 1. during 8-bit data communication, the transmission/re ception is not suspended. it is suspended upon completion of 8-bit data communication. when suspended, bit 0 (tsf0) of serial status register 0 (csis0) is clea red to 0 after transfer of the 8th bit. cautions 1. if the halt inst ruction is executed during auto matic transmission/reception, communication is suspended and the halt mode is set if during 8-bit data communication. when the halt mode is cleared, automatic tr ansmission/reception is restarted from the suspended point. 2. when suspending automa tic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while tsf0 = 1. figure 17-23. automatic transmissi on/reception suspension and restart scka0 soa0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sia0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command (after each register setting, atsta0 = 1) suspend suspend command (atstp0 = 1) atstp0: bit 1 of serial trigger register 0 (csit0) atsta0: bit 0 of csit0 user?s manual u18329ej4v0ud 509 chapter 18 lcd controller/driver 18.1 functions of lcd controller/driver the functions of the lcd controller/driver in the 78k0/lf3 are as follows. (1) the lcd driver voltage generator c an switch external resistance divisi on and internal resistance division. (2) automatic output of segment and common signal s based on automatic display data memory read (3) six different display modes: ? static ? 1/2 duty (1/2 bias) ? 1/3 duty (1/2 bias) ? 1/3 duty (1/3 bias) ? 1/4 duty (1/3 bias) ? 1/8 duty (1/4 bias) (4) six different frame frequencies, selectable in each display mode (5) pd78f047x: segment signal outputs: 40 note (seg0 to seg39), common signal outputs: 8 note (com0 to com7) pd78f048x: segment signal outputs: 40 note (seg0 to seg39), common signal outputs: 8 note (com0 to com7) pd78f049x: segment signal outputs: 32 note (seg0 to seg31), common signal outputs: 8 note (com0 to com7) (6) output of lcd segment signals and time division output of segment key source signals in each display mode (except static mode) segment key source signal outputs: max. 8 (seg24 (ks0) to seg31 (ks7)) note the four segment signal outputs (seg0 to seg3) and four comm on signal outputs (com4 to com7) are alternate-function pins. com4 to com7 can be us ed only when eight-time-slice mode is selected by the setting of the lcd display mode register (lcdm). chapter 18 lcd controller/driver 510 user?s manual u18329ej4v0ud table 18-1 lists the maximum number of pixels that can be displayed in each display mode. table 18-1. maximu m number of pixels (a) pd78f047x, 78f048x lcd driver voltage generator bias mode number of time slices common signals used number of segments maximum number of pixels ? static com0 (com1 to com3) 40 (40 segment signals, 1 common signal) note 2 2 note 1 com0, com1 80 (40 segment signals, 2 common signals) note 3 1/2 3 note 1 com0 to com2 3 note 1 com0 to com2 120 (40 segment signals, 3 common signals) note 4 1/3 4 note 1 com0 to com3 40 160 (40 segment signals, 4 common signals) note 5 ? external resistance division ? internal resistance division 1/4 8 note 1 com0 to com7 36 288 (36 segment signals, 8 common signals) note 6 notes 1. when using the segment key scan function (kson = 1), ?number of time slices + 1? is added for segment key scan signal output. 2. 5-digit lcd panel, each digit having an 8-segment configuration. 3. 10-digit lcd panel, each digit having a 4-segment configuration. 4. 15-digit lcd panel, each digit having a 3-segment configuration. 5. 20-digit lcd panel, each digit having a 2-segment configuration. 6. 36-digit lcd panel, each digit having a 1-segment configuration. (b) pd78f049x lcd driver voltage generator bias mode number of time slices common signals used number of segments maximum number of pixels ? static com0 (com1 to com3) 32 (32 segment signals, 1 common signal) note 2 2 note 1 com0, com1 64 (32 segment signals, 2 common signals) note 3 1/2 3 note 1 com0 to com2 3 note 1 com0 to com2 96 (32 segment signals, 3 common signals) note 4 1/3 4 note 1 com0 to com3 32 128 (32 segment signals, 4 common signals) note 5 ? external resistance division ? internal resistance division 1/4 8 note 1 com0 to com7 28 224 (28 segment signals, 8 common signals) note 6 notes 1. when using the segment key scan function (kson = 1), ?number of time slices + 1? is added for segment key scan signal output. 2. 4-digit lcd panel, each digit having an 8-segment configuration. 3. 8-digit lcd panel, each digit having a 4-segment configuration. 4. 12-digit lcd panel, each digit having a 3-segment configuration. 5. 16-digit lcd panel, each digit having a 2-segment configuration. 6. 28-digit lcd panel, each digit having a 1-segment configuration. chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 511 18.2 configuration of lcd controller/driver the lcd controller/driver consis ts of the following hardware. table 18-2. configuration of lcd controller/driver item configuration display outputs pd78f047x: 40 segment signals note 1 (seg0-seg39), 8 common signals note 1 (com0 to com7) pd78f048x: 40 segment signals note 1 (seg0-seg39), 8 common signals note 1 (com0 to com7) pd78f049x: 32 segment signals note 1 (seg0-seg31), 8 common signals note 1 (com0 to com7) segment key source output segment key source signal: 8 (seg24 (ks0)-seg31 (ks7)) control registers lcd mode register (lcdmd) lcd display mode register (lcdm) lcd clock control register (lcdc0) port function register 2 (pf2) note 2 port function register all (pfall) key return mode register (krm) port mode register 4 (pm4) pull-up resistor option register4 (pu4) port register 14 (p14) port register 15 (p15) notes 1. the four segment signal outputs (seg0 to seg3) and four co mmon signal outputs (com4 to com7) are alternate-function pins. com4 to com7 can be used only when ei ght-time-slice mode is selected by the setting of t he lcd display mode register. 2. pd78f047x and 78f048x only. chapter 18 lcd controller/driver 512 user?s manual u18329ej4v0ud internal bus lcdc4 lcdc2 lcdc1 lcdc0 lcdc6 lcdc5 3 3 selector prescaler lcd clock selector selector lcd clock control register (lcdc) vaon lcdm2 lcd display mode register (lcdm) common driver com0 com1 com2 com3 com4/ seg0 com5/ seg1 com6/ seg2 com7/ seg3 3210 3210 65 74 fa40h display data memory lcdon pk140 p140 3210 65 74 fa57h seg23 seg4 selector 3210 lcdon lcdcl lcdm1 common voltage controller timing controller vaon segment voltage controller lcdm0 lcdon scoc mdset1 lcd mode register (lcdmd) mdset0 gate booster circuit lcd drive voltage controller 2 3 selector 3210 3210 65 74 fa60h lcdon 3210 65 74 fa67h seg39 seg32 selector 3210 7654 7654 7654 7654 lcdon pd78f047x, 78f048x only f lcd 2 6 f lcd 2 7 f lcd 2 4 f lcd 2 5 f lcd 2 8 f lcd 2 9 v lc0 f xt f prs /2 6 f prs /2 7 f prs /2 8 f rl /2 3 f lcd v lc2 v lc3 v lc1 ksf kson kson ksf selector segment driver 3210 3210 65 74 fa58h lcdon segment driver 3210 65 74 fa5fh seg31 (ks7) seg24 (ks0) selector 3210 7654 7654 lcdon ... ... ... ... ... ... ... ... .......... .......... .......... .......... .......... .......... .......... .......... pk153 p153 segment driver segment driver segment driver segment driver figure 18-1. block diagram of lcd controller/driver ... ... ... ... .......... .......... .......... ....... ... .......... .......... .......... .......... .......... chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 513 18.3 registers controlling lcd controller/driver the following ten registers are used to control the lcd controller/driver. ? lcd mode register (lcdmd) ? lcd display mode register (lcdm) ? lcd clock control register (lcdc0) ? port function register 2 (pf2) note ? port function register all (pfall) ? key return mode register (krm) ? port mode register 4 (pm4) ? pull-up resistor option register4 (pu4) ? port register 14 (p14) ? port register 15 (p15) note pd78f047x and 78f048x only. (1) lcd mode register (lcdmd) lcdmd sets the lcd drive voltage generator. lcdmd is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets lcdmd to 00h. figure 18-2. format of lcd mode register address: ffb0h after reset: 00h r/w note 1 symbol 7 6 5 4 3 2 1 0 lcdmd 0 0 mdset1 mdset0 0 0 ksf kson mdset1 mdset0 lcd drive voltage generator selection 0 0 external resistance division method, internal resistor disconnection 0 1 internal resistance division me thod, internal resistor connection (no step-down transforming, used when v lcd = v dd ) 1 1 internal resistance division me thod, internal resistor connection (step-down transforming, used when v lcd = 3/5v dd ) other than above setting prohibited ksf segment key scan status 0 lcd display signal being output 1 segment key scan signal being output kson segment key scan function control 0 segment key scan function is not used 1 segment key scan function is used note 2 notes 1. bit 1 is read-only. 2. use the segment key scan function if v dd is equal to v lc0 . only the kr0 to kr7 pins can be used as input pins for the segment key scan function. caution bits 0 to 2, 3, 6 and 7 must be set to 0. chapter 18 lcd controller/driver 514 user?s manual u18329ej4v0ud (2) lcd display mode register (lcdm) lcdm specifies whether to enable display operation. it also specifies whether to enable segment pin/common pin output, gate booster circ uit control, and the display mode. lcdm is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets lcdm to 00h. figure 18-3. format of l cd display mode register address: ffb1h after reset: 00h r/w symbol <7> <6> 5 <4> 3 2 1 0 lcdm lcdon scoc 0 vaon 0 lcdm2 lcdm1 lcdm0 lcdon lcd display enable/disable 0 display off (all segment outputs are deselected.) 1 display on scoc segment pin/common pin output control note 1 0 output ground level to segment/common pin 1 output deselect level to segment pin and lcd waveform to common pin vaon gate booster circuit control notes 1, 2 0 no gate voltage boosting 1 gate voltage boosting lcd controller/driver display mode selection resistance division method lcdm2 lcdm1 lcdm0 number of time slices bias mode 1 1 1 8 note 3 1/4 note 4 0 0 0 4 note 3 1/3 0 0 1 3 note 3 1/3 0 1 0 2 note 3 1/2 0 1 1 3 note 3 1/2 1 0 0 static other than above setting prohibited (note and caution are listed on the next page.) chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 515 notes 1. when lcd display is not to be performed or not required, power consum ption can be reduced by using the following settings. <1> set both scoc and vaon to 0. <2> when the internal resistance division me thod is used, assume mdset1, mdset0 = (0, 0). (the current flowing to the in ternal resistors can be reduced.) 2. this bit is used to control boosting of the inte rnal gate signal of the lcd controller/driver. if set to "internal gate voltage boosting" , the lcd drive performance can be enhanced. set vaon based on the following conditions. chapter 18 lcd controller/driver 516 user?s manual u18329ej4v0ud (3) lcd clock control register (lcdc0) lcdc0 specifies the lcd source clock and lcd clock. the frame frequency is determined according to t he lcd clock and the number of time slices. lcdc0 is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets lcdc0 to 00h. figure 18-4. format of l cd clock control register address: ffb2h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 lcdc0 0 l cdc6 lcdc5 lcdc4 0 lcdc2 lcdc1 lcdc0 lcdc6 lcdc5 lcdc4 lcd source clock (f lcd ) selection 0 0 0 f xt (32.768 khz) 0 0 1 f prs /2 6 0 1 0 f prs /2 7 0 1 1 f prs /2 8 1 0 0 f rl /2 3 other than above setting prohibited lcdc2 lcdc1 lcdc0 lcd clock (lcdcl) selection 0 0 0 f lcd /2 4 0 0 1 f lcd /2 5 0 1 0 f lcd /2 6 0 1 1 f lcd /2 7 1 0 0 f lcd /2 8 1 0 1 f lcd /2 9 other than above setting prohibited caution bits 3 and 7 must be set to 0. remarks 1. f xt : xt1 clock oscillation frequency 2. f prs : peripheral hardware clock frequency 3. f rl : internal low-speed oscillation clock frequency chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 517 (4) port function register 2 (pf2) ( pd78f047x and 78f048x only) this register sets whether to use pins p20 to p27 as port pins (other than segm ent output pins) or segment output pins. pf2 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pf2 to 00h. figure 18-5. format of port function register 2 address: ffb5h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pf2 pf27 pf26 pf25 pf 24 pf23 pf22 pf21 pf20 pf2n port/segment out put specification 0 used as port (other than segment output) 1 used as segment output remark n = 0 to 7 (5) port function register all (pfall) this register sets whether to use pins p8 to p11 and p13 to p15 as port pins (other than s egment output pins) or segment output pins. pfall is set using a 1-bit or 8-bi t memory manipulation instruction. reset signal generation sets pfall to 00h. figure 18-6. format of port function register all address: ffb6h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pfall 0 pf15all pf14all pf13all pf11all pf10all pf09all pf08all pfnall port/segment output specification 0 used as port (other than segment output) 1 used as segment output remark n = 08 to 11, 13 to 15 chapter 18 lcd controller/driver 518 user?s manual u18329ej4v0ud (6) key return mode register (krm) this register is used to specify that a pin is to be used as a segm ent key scan input pin when using the segment key scan function. see figure 22-2 format of key return mode register (krm) when not using the s egment key scan function. krm is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets 00h. figure 18-7. format of key return mode register (krm) address: ff6eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 krm krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 krmn setting segment key scan input pin (n = 0 to 7) 0 does not use specified pin as segment key scan input pin. 1 uses specified pin as segment key scan input pin. cautions 1. if krm is changed, the interrupt re quest flag may be set. therefore, disable interrupts and then change the krm register. clear the interrupt request flag and enable interrupts. 2. when set not to use th e specified pin as a segment key scan input pin (krmn = 0), the corresponding p4n pin can be used as a normal port. 3. when using the p40/kr0/v lc3 pin for the key interrupt f unction (kr0), set the lcd display mode register (lcdm) to a setting othe r than the 1/4 bias me thod. when set to the 1/4 bias method, the p40/kr0/v lc3 pin functions as v lc3 . chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 519 (7) port mode register 4 (pm4) this register sets port 4 input/output in 1-bit units. when using the segment key scan functi on, set the port mode register of t he port to be used to 1 (pm4n = 1), in order to set the p4n pin as a key scan input pin. pm4 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets ffh. figure 18-8. format of port mode register 4 (pm4) address: ff24h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm4 pm47 pm46 pm45 pm44 pm43 pm42 pm41 pm40 pf4n p4n pin i/o mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) (8) pull-up resistor option register 4 (pu4) this register is used to set whether to use the on-chip pull-up resistors of p40 to p47. when using the segment key scan functi on, set the pull-up resistor option r egister of the port to be used to 0 (pu4n = 0), in order to set the p4n pin as a key scan input pin. an external pull-up resistor cannot be used, because it affects the lcd display output. pu4 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets 00h. figure 18-9. format of pull-up resistor option register 4 address: ff34h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 pu4 pu47 pu46 pu45 pu44 pu43 pu42 pu41 pu40 p4n pin on-chip pull-up resistor selection (n = 0 to 7) pf4n pin using segment key scan function pin not using segment key scan function 0 on-chip pull-up resistor connected only during segment key scan output period on-chip pull-up resistor not connected 1 setting prohibited on-chip pull-up resistor connected chapter 18 lcd controller/driver 520 user?s manual u18329ej4v0ud (9) port register 14 (p14) this register is used to perform the first half of ks0 to ks3 output control by using bits 0 to 3, and the latter half of ks0 to ks3 output control by using bits 4 to 7, when using the s egment key scan function. when using the p14n pin for segment key scan outpu t, the p14n and pk14n bits are used for control. see figure 4-28 format of port register when not using the segm ent key scan function. p14 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets 00h. figure 18-10. format of port register 14 (p14) address: ff0eh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 p14 pk143 pk142 pk141 pk140 p143 p142 p141 p140 p140-p143 first half of ks0 to ks3 output control 0 low-level output 1 high-level output pk140-pk143 latter half of ks0 to ks3 output control 0 low-level output 1 high-level output (10) port register 15 (p15) this register is used to perform the first half of ks4 to ks7 output control by using bits 0 to 3, and the latter half of ks4 to ks7 output control by using bits 4 to 7, when using the s egment key scan function. when using the p15n pin for segment key scan outpu t, the p15n and pk15n bits are used for control. see figure 4-28 format of port register when not using the segm ent key scan function. p15 is set using a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets 00h. figure 18-11. format of port register 15 (p15) address: ff0fh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 p15 pk153 pk152 pk151 pk150 p153 p152 p151 p150 p150-p153 first half of ks4 to ks7 output control 0 low-level output 1 high-level output pk150-pk153 latter half of ks4 to ks7 output control 0 low-level output 1 high-level output chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 521 18.4 setting lcd controller/driver 18.4.1 setting method when not using segment key scan function (kson = 0) when not using the segment key scan f unction (kson = 0), set the lcd contro ller/driver as follows. set the lcd controller/driver using the following procedure. <1> set (vaon = 1) internal gate voltage boosting (b it 4 of the lcd display mode register (lcdm)). note <2> set the resistance division method via mdset0 and mdset1 (bits 4 and 5 of the lcd mode register (lcdmd)) (mdset0 = 0: external resistance divi sion method, mdset0 = 1: internal resistance division method). <3> set the pins to be used as segment outputs to the port function registers (pf2m, pfnall). <4> set an initial value to the ram for lcd display. <5> set the number of time slices via lcdm0 to lcdm 2 (bits 0 to 2 of the lcd display mode register (lcdm)). <6> set the lcd source clock and lcd clock via lcd clock control register 0 (lcdc0). <7> set (scoc = 1) scoc (bit 6 of the lcd display mode register (lcdm)). deselect signals are output from all the segment and common pins , and the non-display status is entered. <8> start output corresponding to each data memory by setting (lcdon = 1) lcdon (bit 7 of lcdm). subsequent to this procedure, set the dat a to be displayed in the data memory. note set vaon based on the following conditions. chapter 18 lcd controller/driver 522 user?s manual u18329ej4v0ud 18.4.2 setting method when using seg ment key scan function (kson = 1) when using the segment key scan functi on (kson = 1), set the lcd controlle r/driver as follows. set the lcd controller/driver using the following procedure. <1> set (vaon = 1) internal gate voltage boosting (b it 4 of the lcd display mode register (lcdm)). note 1 <2> set the resistance division method via mdset0 and mdset1 (bits 4 and 5 of the lcd mode register (lcdmd)) (mdset0 = 0: external resistance divi sion method, mdset0 = 1: internal resistance division method). set (kson = 1) kson (bit 0 of the lcd mode register (lcdmd)). <3> set the pins to be used as segment outputs to the port function registers (pf2m, pfnall). <4> use port mode register 4 (pm4) to set the pin to be used as a key scan input pin note 2 to pm4m = 1 (input mode). <5> use pull-up resistor option register 4 (pu4) to set the pin to be used as a key scan input pin note 2 to pu4m = 0 (connects an on-chip pull-up resistor only during the segment key scan output period). <6> use the key return mode register (krm) to set the pin to be used as a segment key scan input pin to krmm = 1 note 3 . <7> set an initial value to the ram for lcd display. <8> set an initial value of segment key scan output to p14, p15. <9> set the number of time slices via lcdm0 to lcdm 2 (bits 0 to 2 of the lcd display mode register (lcdm)). <10> set the lcd source clock and lcd clock via lcd clock control register 0 (lcdc0). <11> set (scoc = 1) scoc (bit 6 of the lcd display mode register (lcdm)). deselect signals are output from all the segment and common pins , and the non-display status is entered. <12> start output corresponding to each data memory by setting (lcdon = 1) lcdon (bit 7 of lcdm). hereinafter, set data to the data memory according to the contents displayed, and perform segment key scan output settings for the port registers (p14, p15) acco rding to the contents of the segment key scan output. notes 1. set vaon based on the following conditions. chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 523 remarks 1. use the following procedure to set to the displa y-off state and disconnect the internal resistors when using the internal resistance division method. <1> clear lcdon (bit 7 of lcdm) (lcdon = 0). deselect signals are output from all s egment pins and common pins, and a non-display state is entered. <2> clear scoc (bit 6 of the lcd display mode register (lcdm)) (scoc = 0). ground levels are output from a ll segment pins and common pins. <3> assume mdset0, mdset1 (bits 4 and 5 of the lcd mode register (lcdmd)) = (0, 0) and set the resistance division method to t he external resistance division method. 2. m = 0 to 7, n = 08 to 11, 13 to 15 caution when displaying in a mode with a large number of coms, such as 8 com, v lc0 may not be able to obtain sufficient contrast under the low-voltage conditions, depending on the panel characteristics. use the l cd controller/driver after having performed thorough lcd display evaluation and confirmed that there ar e no problems regarding the display quality. chapter 18 lcd controller/driver 524 user?s manual u18329ej4v0ud 18.5 lcd display data memory the lcd display data memory is mapped at addresses fa40h to fa67h ( pd78f047x and 78f048x) or fa40h to fa5fh ( pd78f049x). data in the lcd display data memory can be displayed on the lcd panel using the lcd controller/driver. figure 18-12 shows the relationship between the c ontents of the lcd disp lay data memory and the segment/common outputs. the areas not to be used for display can be used as normal ram. figure 18-12. relationship between lcd display data memory cont ents and segment/common outputs (a) pd78f047x, 78f048x fa67h fa66h fa65h seg39 seg38 seg37 b7 b6 b5 b4 b3 b2 b1 b0 com7 com6 com5 com4 0000 0000 0000 0000 com3 com2 com1 com0 fa45h fa44h fa43h fa42h fa41h fa40h seg5 seg4 seg3 seg2 seg1 seg0 (b) pd78f049x fa5fh fa5eh fa5dh seg31 seg30 seg29 b7 b6 b5 b4 b3 b2 b1 b0 com7 com6 com5 com4 0000 0000 0000 0000 com3 com2 com1 com0 fa45h fa44h fa43h fa42h fa41h fa40h seg5 seg4 seg3 seg2 seg1 seg0 caution no memory is allocated to the higher 4 bits of fa40h to fa43h. be sure to set there bits to 0. chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 525 18.6 common and segment signals each pixel of the lcd panel turns on when the pot ential difference between the corresponding common and segment signals becomes higher than a s pecific voltage (lcd drive voltage, v lcd ). the pixels turn off when the potential difference becomes lower than v lcd . applying dc voltage to the common and s egment signals of an lcd panel causes deterioration. to avoid this problem, this lcd panel is driven by ac voltage. (1) common signals each common signal is selected sequentially according to a specified number of ti me slices at the timing listed in table 18-3. in the st atic display mode, the same signal is output to com0 to com3. when using the segment key scan output function (kson = 1), segm ent key scan output will be performed for a period of one time slice after one lcd output cycl e. the common signal generat ed at that time will not be displayed when output. in the two-time-slice mode, leave t he com2 and com3 pins open. in t he three-time-slice mode, leave the com3 pin open. use the com4 to com7 pins other than in t he eight-time-slice mode as open or segment pins. table 18-3. com signals com0 com1 com2 com3 static display mode two-time-slice mode note 1 open open open three-time-slice mode note 1 four-time-slice mode note 1 com signal number of time slices eight-time-slice mode note 1 com4 com5 com6 com7 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 note 2 notes 1. when using the segment key scan output function (kson = 1), non-display output will be performed for a period of one time slice after one lcd output cycle. 2. use the pins as open or segment pins. (2) segment signals (a) pd78f047x, 78f048x the segment signals correspond to 40 bytes of the l cd display data memory (fa40h to fa67h) during an lcd display period, bits 0, 1, 2, and 3 of each byte are read in syn chronization with com0, com1, com2, and com3, respectively. if a bit is 1, it is converted to t he select voltage, and if it is 0, it is converted to the deselect voltage. the conversion results are output to the segment pins (seg0 to seg39). furthermore, segment signals correspond to the setting values of port register s 14 and 15 during a segment key scan output period. bits 0 to 3 and bits 4 to 7 of each port register will be read in synchronization with the first half and latter half of the segment key scan output period, respectively, and if the content of each bit is 1 or 0, high levels or low levels will be output to the segment pins (seg24 to seg31), respectively. chapter 18 lcd controller/driver 526 user?s manual u18329ej4v0ud (b) pd78f049x the segment signals correspond to 32 bytes of the lcd display data memory (fa40h to fa5fh) during an lcd display period, bits 0, 1, 2, and 3 of each byte are read in syn chronization with com0, com1, com2, and com3, respectively. if a bit is 1, it is converted to t he select voltage, and if it is 0, it is converted to the deselect voltage. the conversion results are output to the segment pins (seg0 to seg31). furthermore, segment signals correspond to the setting values of port register s 14 and 15 during a segment key scan output period. bits 0 to 3 and bits 4 to 7 of each port register will be read in synchronization with the first half and latter half of the segment key scan output period, respectively, and if the content of each bit is 1 or 0, high levels or low levels will be output to the segment pins (seg24 to seg31), respectively. check, with the information given above, what combination of front-surfa ce electrodes (corresponding to the segment signals) and rear-surface electrodes (corres ponding to the common signals) forms display patterns in the lcd display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one basis. lcd display data memory bits 1 to 3, bits 2 and 3, and bi t 3 are not used for lcd displa y in the static display, two-time slot, and three-time slot modes, respectively . so these bits can be used for purposes other than display. the higher 4 bits of fa40h to fa43h are fixed to 0. chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 527 (3) output waveforms of common signals and segme nt signals during lcd display signal output period the voltages shown in table 18-4 are output to the common signals and segment signals during the lcd display signal output period. when both common and segment signals are at t he select voltage, a display on-voltage of v lcd is obtained. the other combinations of the signals correspond to the display off-voltage. table 18-4. lcd drive voltage (a) static display mode (duri ng lcd display signal output period) segment signal select signal level deselect signal level common signal v ss /v lc0 v lc0 /v ss v lc0 /v ss ?v lcd /+v lcd 0 v/0 v (b) 1/2 bias method (during lcd display signal output period) segment signal select signal level deselect signal level common signal v ss /v lc0 v lc0 /v ss select signal level v lc0 /v ss ?v lcd /+v lcd 0 v/0 v deselect signal level v lc1 = v lc2 ? v lcd /+ v lcd + v lcd /? v lcd (c) 1/3 bias method (during lcd display signal output period) segment signal select signal level deselect signal level common signal v ss /v lc0 v lc1 /v lc2 select signal level v lc0 /v ss ?v lcd /+v lcd ? v lcd /+ v lcd deselect signal level v lc2 /v lc1 ? v lcd /+ v lcd + v lcd /? v lcd (d) 1/4 bias method (during lcd display signal output period) segment signal select signal level deselect signal level common signal v lc0 /v ss v lc1 /v lc2 select signal level v ss /v lc0 +v lcd /?v lcd + v lcd /? v lcd deselect signal level v lc1 /v lc3 + v lcd /? v lcd ? v lcd /+ v lcd 1 2 1 2 1 2 1 2 1 3 1 3 1 3 1 3 1 3 1 3 1 4 1 4 1 2 1 2 1 4 1 4 chapter 18 lcd controller/driver 528 user?s manual u18329ej4v0ud figure 18-13 shows the common signal waveforms, and figure 18-14 shows the vo ltages and phases of the common and segment signals. figure 18-13. common signal waveforms (a) static display mode comn (static display) t f = t v lc0 v ss v lcd t: one lcd clock period t f : frame frequency (b) 1/2 bias method comn (two-time slot mode) t f = 2 t v lc0 v ss v lcd v lc2 comn (three-time slot mode) t f = 3 t v lc0 v ss v lcd v lc2 t: one lcd clock period t f : frame frequency (c) 1/3 bias method comn (three-time slot mode) t f = 3 t v lc0 v ss v lcd v lc1 v lc2 t f = 4 t comn (four-time slot mode) v lc0 v lcd v lc1 v lc2 v ss t: one lcd clock period t f : frame frequency chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 529 (d) 1/4 bias method comn v lc1 v lc0 v ss v lcd v lc2 v lc3 t f = 8 t (eight-time slot mode) t: one lcd clock period t f : frame frequency chapter 18 lcd controller/driver 530 user?s manual u18329ej4v0ud figure 18-14 voltages and phases of common and segment signals (a) static display mode select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt t: one lcd clock period (b) 1/2 bias method select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 t: one lcd clock period (c) 1/3 bias method select deselect common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd tt v lc2 v lc2 v lc1 v lc1 t: one lcd clock period chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 531 (d) 1/4 bias method v lc1 v lc0 v ss v lcd v lc0 v lc3 v lcd v lc3 v lc2 v lc2 v lc1 v ss t t t t select deselect common signal segment signal t: one lcd clock period chapter 18 lcd controller/driver 532 user?s manual u18329ej4v0ud (4) output waveforms of common and segment signals during segment key scan output period the voltages shown in table 18-5 are output to the common signals and segment signals during the segment key scan output period. when both common and segment signals are at t he select voltage, a display on-voltage of v lcd is obtained. the other combinations of the signals correspond to the display off-voltage. table 18-5. lcd drive voltage (a) 1/2 bias method (during segment key scan output period) key scan signal p14x = p15x = 1 p14x = p15x = 0 common signal v d0 v ss deselect signal level v lc1 = v lc2 + v lcd ? v lcd (b) 1/3 bias method (during segment key scan output period) key scan signal p14x = p15x = 1 p14x = p15x = 0 common signal v dd v ss deselect signal level v lc2 /v lc1 + v lcd /+ v lcd ? v lcd /? v lcd (c) 1/4 bias method (during segment key scan output period) key scan signal p14x = p15x = 1 p14x = p15x = 0 common signal v dd v ss deselect signal level v lc1 /v lc3 + v lcd /+ v lcd ? v lcd /? v lcd remark the segment key scan output function cannot be used in t he static display mode. 3 4 1 2 1 2 1 3 3 4 1 4 1 4 2 3 2 3 1 3 chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 533 figure 18-15 shows the common signal waveforms, and figure 18-16 shows the vo ltages and phases of the common and segment signals. figure 18-15 common signal waveforms (a) 1/2 bias method comn (two-time slot mode) t f = 3 t v lc0 v ss v lcd v lc2 comn (three-time slot mode) t f = 4 t v lc0 v ss v lcd v lc2 t: one lcd clock period t f : frame frequency shaded sections: segment key scan output period (b) 1/3 bias method comn (three-time slot mode) comn (four-time slot mode) t f = 4 t t f = 5 t v lc0 v ss v lcd v lc1 v lc2 v lc0 v ss v lcd v lc1 v lc2 t: one lcd clock period t f : frame frequency shaded sections: segment key scan output period (c) 1/4 bias method v lc0 v lc3 comn (eight-time slot mode) t f = 9 t v lc1 v ss v lcd v lc2 t: one lcd clock period t f : frame frequency shaded sections: segment key scan output period chapter 18 lcd controller/driver 534 user?s manual u18329ej4v0ud figure 18-16 voltages and phases of common and segment signals (a) 1/2 bias method key input wait key identification common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd v lc2 v lc2 t t key identification signal t: one lcd clock period (b) 1/3 bias method common signal segment signal v lc0 v ss v lcd v lc0 v ss v lcd v lc2 v lc2 v lc1 v lc1 t t key input wait key identification key identification signal t: one lcd clock period (c) 1/4 bias method common signal common signal v lc0 v ss v lcd v lc0 v ss v lcd v lc2 v lc2 v lc1 v lc1 t t key input wait key identification v lc3 v lc3 key identification signal t: one lcd clock period remark segment key scan signals must be set by using port registers 14 and 15 (p14, p15). chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 535 18.7 display modes 18.7.1 static display example figure 18-18 shows how the three-digit lcd panel having t he display pattern shown in figure 18-17 is connected to the segment signals (seg0 to seg 23) and the common signal (com0) of the 78k0/lf3 chip. this example displays data "12.3" in the lcd panel. the contents of the displa y data memory (fa40h to fa57h) correspond to this display. the following description focuses on numeral "2." ( ) disp layed in the second digit. to display "2." in the lcd panel, it is necessary to apply the select or deselect volt age to the seg8 to seg15 pins according to table 18-6 at the timing of the common signal com0; see figure 18-17 for the relationship between the segment signals and lcd segments. table 18-6. select and deselect voltages (com0) segment seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 common com0 select deselect select select deselect select select select according to table 18-6, it is determi ned that the bit-0 pattern of the disp lay data memory locations (fa48h to fa4fh) must be 10110111. figure 18-19 shows the lcd drive waveforms of seg 11 and seg12, and com0. when the select voltage is applied to seg11 at the timing of com0 , an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. com1 to com3 are supplied with the same waveform as for com0. so, com0 to com3 may be connected together to increase t he driving capacity. figure 18-17 static lcd display pa ttern and electrode connections seg 8n+3 seg 8n+2 seg 8n+5 seg 8n+1 seg 8n seg 8n+4 seg 8n+6 seg 8n+7 com0 remark n = 0 to 2 chapter 18 lcd controller/driver 536 user?s manual u18329ej4v0ud figure 18-18. example of connecting static lcd panel 000001101110110110101110 bit 0 bit 2 bit 1 bit 3 timing strobe data memory address lcd panel fa40h 1 2 3 4 5 6 7 8 9 a b c d e f fa50h 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 can be connected together chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 537 figure 18-19. static l cd drive waveform examples t f v lc0 v ss com0 v lc0 v ss seg11 v lc0 v ss seg12 +v lcd 0 com0-seg12 - v lcd +v lcd 0 com0-seg11 - v lcd chapter 18 lcd controller/driver 538 user?s manual u18329ej4v0ud 18.7.2 two-time-s lice display example figure 18-21 shows how the 6-digit lcd panel having the di splay pattern shown in figure 18-20 is connected to the segment signals (seg0 to seg23) and the common signals (com0 and com1 ) of the 78k0/lf3 chip. this example displays data "12345.6" in the lcd panel. the c ontents of the display data memory (fa40h to fa57h) correspond to this display. the following description focuses on numeral "3" ( ) displa yed in the fourth digit. to display "3" in the lcd panel, it is necessary to apply the select or deselect voltage to the seg12 to seg15 pins acco rding to table 18-7 at the timing of the common signals com0 and com1; see figure 18-20 for the relationship between the segment signals and lcd segments. table 18-7. select and desel ect voltages (com0 and com1) segment seg12 seg13 seg14 seg15 common com0 select select deselect deselect com1 deselect select select select according to table 18-7, it is det ermined that the display data memory location (fa4fh) that corresponds to seg15 must contain xx10. figure 18-22 shows examples of lcd drive wavefo rms between the seg15 signal and each common signal. when the select voltage is applied to seg15 at the timing of com1, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 18-20. two-time-slice lcd displ ay pattern and electrode connections seg 4n+2 seg 4n+3 seg 4n+1 seg 4n com0 com1 remark n = 0 to 5 chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 539 figure 18-21. example of connecting two-time-slice lcd panel 001110100011011101011101 000011101110001011111110 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel fa40h 1 2 3 4 5 6 7 8 9 a b c d e f fa5 0h 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 open open : can always be used to store any data bec ause the two-time-slice mode is being used. chapter 18 lcd controller/driver 540 user?s manual u18329ej4v0ud figure 18-22. two-time-slice lcd dri ve waveform examples (1/2 bias method) (a) when segment key scan function is not used (kson = 0) t f v lc0 v ss com0 v lc0 v ss v lc0 v ss seg15 +v lcd 0 com1-seg15 - v lcd +v lcd 0 com0-seg15 - v lcd v lc1,2 v lc1,2 v lc1,2 com1 +1/2v lcd +1/2v lcd - 1/2v lcd - 1/2v lcd chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 541 (b) when segment key scan function is used (kson = 1) chapter 18 lcd controller/driver 542 user?s manual u18329ej4v0ud chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 543 18.7.3 three-time-s lice display example figure 18-24 shows how the 8-digit lcd panel having the di splay pattern shown in figure 18-23 is connected to the segment signals (seg0 to seg23) and the common signals (com0 to com2 ) of the 78k0/lf3 chip. this example displays data "123456.78" in the lcd panel. the contents of the displa y data memory (addresses fa40h to fa57h) correspond to this display. the following description focuses on numeral "6." ( ) disp layed in the third digit. to display "6." in the lcd panel, it is necessary to apply the select or deselect voltage to the seg6 to seg8 pins according to table 18-8 at the timing of the common signals com0 to com2; see figure 18-23 for the relationship between the segment signals and lcd segments. table 18-8. select and desel ect voltages (com0 to com2) segment seg6 seg7 seg8 common com0 deselect select select com1 select select select com2 select select ? according to table 18-8, it is dete rmined that the display data memory loca tion (fa46h) that corresponds to seg6 must contain x110. figures 18-25 and 18-26 show exampl es of lcd drive waveforms bet ween the seg6 signal and each common signal in the 1/2 and 1/3 bias methods, respectively. w hen the select voltage is appli ed to seg6 at the timing of com1 or com2, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 18-23. three-time-slice lcd displ ay pattern and electrode connections seg 3n+2 seg 3n com0 com2 seg 3n+1 com1 remark n = 0 to 7 chapter 18 lcd controller/driver 544 user?s manual u18329ej4v0ud figure 18-24. example of conn ecting three-time-slice lcd panel 001011011101110110111111 bit 0 001110011011011111001111 bit 1 bit 3 timing strobe data memory address lcd panel fa40h 1 2 3 4 5 6 7 8 9 a b c d e f fa50h 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 open 00 10 10 00 10 11 00 10 bit 2 x? x? x? x? x? x? x? x? ?: can be used to store any data because there is no corres ponding segment in the lcd panel. : can always be used to store any data becaus e the three-time-slice mode is being used. chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 545 figure 18-25. three-time-slice lcd dri ve waveform examples (1/2 bias method) (a) when segment key scan function is not used (kson = 0) com0 com2 +v lcd 0 com1-seg6 +v lcd 0 com0-seg6 com1 +1/2v lcd +1/2v lcd seg6 +v lcd 0 com2-seg6 +1/2v lcd t f v lc0 v ss v lc0 v ss v lc0 v ss v lc1,2 v lc1,2 v lc1,2 v lc0 v ss v lc1,2 - v lcd - v lcd - 1/2v lcd - 1/2v lcd - v lcd - 1/2v lcd chapter 18 lcd controller/driver 546 user?s manual u18329ej4v0ud (b) when segment key scan function is used (kson = 1) chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 547 chapter 18 lcd controller/driver 548 user?s manual u18329ej4v0ud figure 18-26. three-time-slice lcd dri ve waveform examples (1/3 bias method) (a) when segment key scan function is not used (kson = 0) v lc0 v lc2 com0 +v lcd 0 com0-seg6 - v lcd v lc1 +1/3v lcd - 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 seg6 v lc1 v ss +v lcd 0 com1-seg6 - v lcd +1/3v lcd - 1/3v lcd +v lcd 0 com2-seg6 - v lcd +1/3v lcd - 1/3v lcd t f chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 549 (b) when segment key scan function is used (kson = 1) chapter 18 lcd controller/driver 550 user?s manual u18329ej4v0ud chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 551 18.7.4 four-time-sli ce display example figure 18-28 shows how the 12-digit lcd panel having the di splay pattern shown in figure 18-27 is connected to the segment signals (seg0 to seg23) and the common signals (com0 to com3 ) of the 78k0/lf3 chip. this example displays data "123456.789012" in the lcd panel. t he contents of the displa y data memory (addresses fa40h to fa57h) correspond to this display. the following description focuses on numeral "6." ( ) disp layed in the seventh digit. to display "6." in the lcd panel, it is necessary to apply the select or deselect vo ltage to the seg12 and seg13 pins according to table 18-9 at the timing of the common signals com0 to com3; see fi gure 18-27 for the relationshi p between the segment signals and lcd segments. table 18-9. select and desel ect voltages (com0 to com3) segment seg12 seg13 common com0 select select com1 deselect select com2 select select com3 select select according to table 18-9, it is det ermined that the display data memory location (fa4ch) that corresponds to seg12 must contain 1101. figure 18-29 shows examples of lcd drive wavefo rms between the seg12 signal and each common signal. when the select voltage is applied to seg12 at the timing of com0, an alternate rectangle waveform, +v lcd / ? v lcd , is generated to turn on the corresponding lcd segment. figure 18-27. four-time-slice lcd displ ay pattern and electrode connections com0 seg 2n com1 seg 2n+1 com2 com3 remark n = 0 to 11 chapter 18 lcd controller/driver 552 user?s manual u18329ej4v0ud figure 18-28. example of connecting four-time-slice lcd panel 000101101111111111110001 011111111010011111010111 011001010111011101110110 001010001011001000100010 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel fa40h 1 2 3 4 5 6 7 8 9 a b c d e f fa50h 1 2 3 4 5 6 7 seg 0 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 seg 15 seg 16 seg 17 seg 18 seg 19 seg 20 seg 21 seg 22 seg 23 com 3 com 2 com 1 com 0 chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 553 figure 18-29. four-time-slice lcd dri ve waveform examples (1/3 bias method) (a) when segment key scan function is not used (kson = 0) v lc0 v lc2 com0 +v lcd 0 com0-seg12 - v lcd v lc1 +1/3v lcd - 1/3v lcd v ss v lc0 v lc2 com1 v lc1 v ss v lc0 v lc2 com2 v lc1 v ss v lc0 v lc2 com3 v lc1 v ss +v lcd 0 com1-seg12 - v lcd +1/3v lcd - 1/3v lcd v lc0 v lc2 seg12 v lc1 v ss t f remark the waveforms for com2 to seg12 and com3 to seg12 are omitted. chapter 18 lcd controller/driver 554 user?s manual u18329ej4v0ud (b) when segment key scan function is used (kson = 1) chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 555 chapter 18 lcd controller/driver 556 user?s manual u18329ej4v0ud 18.7.5 eight-time-s lice display example figure 18-31 shows how the 15 8 dots lcd panel having the display patte rn shown in figure 18-30 is connected to the segment signals (seg4 to seg 18) and the common signals (com0 to co m7) of the 78k0/lf3 chip. this example displays data "123" in the lcd panel. the cont ents of the display data memory (addresses fa44h to fa52h) correspond to this display. the following description focuses on numeral "3." ( ) displa yed in the first digit. to display "3." in the lcd panel, it is necessary to apply the select or deselect voltage to the seg4 and seg8 pi ns according to table 18-10 at the timing of the common signals com0 to com7; see figure 18-30 for the relationship bet ween the segment signals and lcd segments. table 18-10. select and desel ect voltages (com0 to com7) segment seg4 seg5 seg6 seg7 seg8 common com0 select select select select select com1 deselect select deselect deselect deselect com2 deselect deselect select deselect deselect com3 deselect select deselect deselect deselect com4 select deselect deselect deselect deselect com5 select deselect deselect deselect select com6 deselect select select select deselect com7 deselect deselect de select deselect deselect according to table 18-10, it is det ermined that the display data memory location (fa44h) that corresponds to seg4 must contain 00110001. figure 18-32 shows examples of lcd drive waveforms between the seg4 signal and each common signal. when the select voltage is applied to seg4 at the timing of com0, a waveform is generated to turn on the corresponding lcd segment. figure 18-30. eight-time-s lice lcd display pattern a nd electrode connections com0 com1 com2 com3 com4 com5 com6 com7 sssss eeeee ggggg n+4 n+3 n+2 n+1 n chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 557 figure 18-31. example of connect ing eight-time-slice lcd panel 001000111011111 011001000100010 bit 3 bit 2 bit 1 bit 0 timing strobe data memory address lcd panel bit 5 bit 4 bit 7 bit 6 fa44h 5 6 7 8 9 a b c d e f fa50h 1 2 seg 4 seg 5 seg 6 seg 7 seg 8 seg 9 seg 10 seg 11 seg 12 seg 13 seg 14 com 3 com 2 com 1 com 0 com 7 com 6 com 5 com 4 001000010000001 001000100010001 001000000100100 001000001000010 011101111101110 000000000000000 seg 15 seg 16 seg 17 seg 18 chapter 18 lcd controller/driver 558 user?s manual u18329ej4v0ud figure 18-32. eight-time-slice lcd dri ve waveform examples (1/4 bias method) (a) when segment key scan function is not used (kson = 0) v lc0 v lc2 v lc3 com0 +v lcd 0 - v lcd v lc1 +1/2v lcd - 1/2v lcd v ss +v lcd 0 - v lcd +1/4v lcd - 1/4v lcd t f v lc0 v lc2 v lc3 com1 v lc1 v ss v lc0 v lc2 v lc3 com2 v lc1 v ss v lc0 v lc2 v lc3 v lc1 v ss v lc0 v lc2 v lc3 com7 v lc1 v ss . . . . . . . . +1/4v lcd - 1/4v lcd +1/2v lcd - 1/2v lcd com0-seg4 seg4 com1-seg4 remark the waveforms for com3 to com6, com2 to seg4 and com7 to seg4 are omitted. chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 559 (b) when segment key scan function is used (kson = 1) chapter 18 lcd controller/driver 560 user?s manual u18329ej4v0ud chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 561 18.8 operation of segment key scan function the segment key scan function is us ed to reduce the number of pins us ed by outputting lcd display segment output and key scan signals from the same pin. caution this function may affect the l cd panel, depending on how it is used. use the function after thorough evaluation. 18.8.1 circuit configuration example figure 18-33. circuit configuration example kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 ks0 com3 com1 lcd panel com2 com0 ks1 ks2 ks3 ks4 ks5 ks6 ks7 chapter 18 lcd controller/driver 562 user?s manual u18329ej4v0ud 18.8.2 example of procedure fo r using segment key scan function figure 18-34 shows the operation flow of the segment key scan and fi gure 18-35 shows the key connection example. figure 18-34. operation flow of segment key scan no yes clear intkr key input processing initial setting start segment key scan (key identification status) segment key scan (key input wait status) key on? (krif = 1) figure 18-35. key connection example kr0 kr1 kr2 ks0 lcd panel ks1 ks2 a bc chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 563 an example of the segment key scan operation when key b, shown in figure 18-35, has been pressed is shown below. figure 18-36. example of segm ent key scan operation timing (four-time-slice (1/3 bias method)) v lc0 v lc2 +v lcd 0 -v lcd v lc1 +1/3v lcd -1/3v lcd v ss v lc0 v lc2 v lc1 v ss com0 com0-seg24(ks0) seg24(ks0) ksf key input wait key input wait key identification key input wait key a key b key c v lc0 v lc2 v lc1 v ss seg25(ks1) v lc0 v lc2 v lc1 v ss seg26(ks2) kr0 krif kr1 kr2 h h h h h h l l <1> <3> <4> <2> <5> <6> <7> t f = 5 t t: one lcd clock period t f : frame frequency shaded sections: segment key scan output period <1> assume key b has been pressed at this timing. <2> krif becomes ?1? and the key t hat has been pressed can be known. <3> kr0 becomes low level, and whether key a, b, or c has been pressed can be known. input to the kr pin will be enabled after two f lcd clocks from the rise of ksf. consequently, krif becomes ?1? after two f lcd clocks from the rise of ksf. <4> a segment key scan operation is started a fter it has been confirmed that ksf is ?1?. <5> it can be known that key a is not pressed, bec ause kr0 was at high level when the seg24 (ks0) pin outputs a low level. <6> it can be known that key b is pressed, becaus e kr0 was at low level when the seg25 (ks1) pin outputs a low level. perform t he input processing of key b. <7> clear krif. chapter 18 lcd controller/driver 564 user?s manual u18329ej4v0ud the output values of the seg (ks) pin during the segment key scan out put period correspond to the setting values of port registers 14 and 15, and can be cont rolled by using port registers 14 and 15. bits 0 to 3 and bits 4 to 7 of each port register are used to control the first half and latter half of the segment key scan output period, respectively (see (9) port register 14 (p14) and (10) port register 15 (p15) in 18.3 ). figure 18-37 shows the relationship between port register 14 and the segment key scan output. figure 18-37. relationship between port re gister 14 and segment key scan output (for p140/seg24(ks0) pin) lcd display 1frame period t ks output ks first half ks latter half lcd display ks output lcd display ks output lcd display ks output p140/seg24(ks0) chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 565 18.9 cautions when using se gment key scan function (1) conditions for use use the segment key scan function if v dd is equal to v lc0 . (2) segment key scan input pins only the kr0 to kr7 pins can be used as i nput pins for the segment key scan function. other pins cannot be used as input pins for the segment key scan function. (3) allowable input range of kr0 to kr7 pins due to a delay caused by a pull-up resistor, segment key scan input cannot be performed for the kr pin for a period of two f lcd clocks from the start of the segment key scan output period. similarly, due to input end processing, segment key scan input cannot be perfo rmed for the kr pin for the period of the last f lcd clock of the segment key scan output period. (4) key return mode register (krm) setting when the segment key scan function is us ed (kson = 1), set krmn to 1 or 0 to use or not use the krn pin as a segment key scan input pin. (5) circuit configuration when using the segment key scan func tion, at least diode a or diode b s hown in figure 18-38 is required. the following problems will occur when diodes a and b are missing. figure 18-38. key matrix configuration example diode a to lcd panel diode b p140(ks0) p141(ks1) p152(ks6) p153(ks7) to kr p46/kr6 p47/kr7 p41/kr1 p40/kr0 chapter 18 lcd controller/driver 566 user?s manual u18329ej4v0ud (a) when both diodes a and b are missing when both diodes a and b are missing, the segment key scan function cannot be used, because of the following. the following figure shows a circuit exam ple when both diodes a and b are missing. assume, as shown in the figure below, that switc hes sw1 and sw2 are turned on, and a high level and a low level are output from the ks1 pin and ks0 pin, respectively. when diode a is missing at this time, currents i 1 and i 2 , shown as broken lines, will flow. consequently, the high level of ks1 and the low le vel of ks0 will not be output normally due to i 2 , and the key input data of kr1 will become undefined. furthermore, the lcd display will not be turned on or off normally. i 1 i 2 lcd high low sw2 sw1 kr0 kr1 lcd ks0 ks1 (b) when only diode a exists when only diode a exists, whether s witches are pressed simultaneously cannot be identified, due to the following. the following figure shows a circuit example when only diode a exists. assume, as shown in the figure below, that switc hes sw1, sw2, and sw4 are turned on, and a high level and a low level are output from the ks1 pin and ks0 pin, respectively. at this time currents i 1 and i 2 , shown as broken lines, will flow. consequently, even though sw3 is turned o ff, sw3 is identified to be turned on, because a low level is input to kr0 due to i 2 . there is no interference with the lcd display. i 1 i 2 low high sw4 sw3 sw2 sw1 kr0 kr1 ks0 ks1 lcd lcd (c) when only diode b exists identification of at least three switches being pressed simultaneously can be performed. there is no interference with the lcd display. chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 567 18.10 supplying lcd drive voltages v lc0 , v lc1 , v lc2, and v lc3 with the 78k0/lf3, a lcd drive power supply can be generated using either of two types of methods: internal resistance division method or exte rnal resistance division method. 18.10.1 internal resi stance division method the 78k0/lf3 incorporates vo ltage divider resistors for generating lcd dr ive power supplies. using internal voltage divider resistors, a lcd drive power supply t hat meet each bias method listed in table 18-11 can be generated, without using external voltage divider resistors. table 18-11. lcd drive voltages (with on-chip voltage divider resistors) bias method no bias (static) 1/2 bias method 1/3 bias method 1/4 bias method lcd drive voltage pin v lc0 v lcd v lcd v lcd v lcd v lc1 v lcd v lcd note v lcd v lcd v lc2 v lcd v lcd v lcd v lc3 v ss v ss v ss v lcd note for the 1/2 bias method, it is necessary to connect the v lc1 and v lc2 pins externally. figure 18-39 shows examples of gener ating lcd drive voltages interna lly according to table 18-11. figure 18-39. examples of lcd dr ive power connections (internal resistance division method) (1/2) (a) 1/3 bias method and static display mode (mdset1, mdset0 = 0, 1) (example of v dd = 5 v, v lc0 = 5 v) (b) 1/3 bias method and static display mode (mdset1, mdset0 = 1, 1) (example of v dd = 5 v, v lc0 = 3 v) v lc0 v lc0 r v dd p-ch v ss v lc1 v lc2 p40/kr0 p40/kr0 v lc0 = v dd p-ch v lc1 r p-ch v lc2 r p-ch v ss mdset0 v lc0 v lc0 r v dd p-ch v ss v lc1 v lc2 p40/kr0 p40/kr0 p-ch v lc1 r p-ch v lc2 r p-ch v ss mdset0 2r v lc0 = v dd 5 3 remark it is recommended to use the external resistance divi sion method when using the st atic display mode, in order to reduce power consumed by the voltage divider resistor. 2 3 2 3 1 2 1 3 1 3 3 4 2 4 1 4 chapter 18 lcd controller/driver 568 user?s manual u18329ej4v0ud figure 18-39. examples of lcd dr ive power connections (internal resistance division method) (2/2) (c) 1/2 bias method (mdset1, mdset0 = 0, 1) (example of v dd = 5 v, v lc0 = 5 v) (d) 1/4 bias method (mdset1, mdset0 = 1, 1) (example of v dd = 5 v, v lc0 = 3 v) v lc0 v lc0 r v dd p-ch v ss v lc1 v lc2 p40/kr0 p40/kr0 v lc0 = v dd p-ch v lc1 r p-ch v lc2 r p-ch v ss mdset0 v lc0 v lc0 r v dd p-ch v ss v lc1 v lc2 p40/kr0 p40/kr0 p-ch v lc1 r p-ch v lc2 r p-ch v ss mdset0 v lc0 = v dd 5 3 r 3 4 (e) 1/4 bias method (mdset1, mdset0 = 0, 1) (example of v dd = 5 v, v lc0 = 5 v) v lc0 v lc0 r v dd p-ch v ss v lc1 v lc2 v lc3 v lc3 v lc0 = v dd p-ch v lc1 r p-ch v lc2 r p-ch v ss mdset0 r p-ch chapter 18 lcd controller/driver user?s manual u18329ej4v0ud 569 18.10.2 external resi stance division method the 78k0/lf3 can also use external voltage divider resistors for generati ng lcd drive power supplies, without using internal resistors. figure 18- 40 shows examples of lcd drive volt age connection, corresponding to each bias method. figure 18-40. examples of lcd dr ive power connections (external resistance division method) (1/2) (a) static display mode (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 5 v) (b) static display mode (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 3 v) v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 note v lc2 note p40/kr0 p40/kr0 v lc0 = v dd v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 p40/kr0 p40/ kr0 2r 3r v lc0 = v dd 5 3 note connect v lc1 and v lc2 directly to gnd or v lc0 . (c) 1/2 bias method (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 5 v) (d) 1/2 bias method (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 3 v) v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 p40/kr0 p40/ kr0 r r v lc0 = v dd v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 p40/kr0 p40/ kr0 r r 3 4 r v lc0 = v dd 5 3 chapter 18 lcd controller/driver 570 user?s manual u18329ej4v0ud figure 18-40. examples of lcd dr ive power connections (external resistance division method) (2/2) (e) 1/3 bias method (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 5 v) (f) 1/3 bias method (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 3 v) v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 p40/kr0 p40/ kr0 r r v lc0 = v dd r v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 p40/kr0 p40/ kr0 r r r 2r v lc0 = v dd 5 3 (g) 1/4 bias method (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 5 v) (h) 1/4 bias method (mdset1, mdset0 = 0, 0) (example of v dd = 5 v, v lc0 = 3 v) v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 r r v lc0 = v dd r v lc3 v lc3 r v lc0 v lc0 v lc1 v lc2 v ss v dd v ss v lc1 v lc2 r r r v lc3 v lc3 r 3 8 r v lc0 = v dd 5 3 user?s manual u18329ej4v0ud 571 chapter 19 manchester code generator 19.1 functions of manchester code generator the following three types of modes are ava ilable for the manchester code generator. (1) operation stop mode this mode is used when output by the manchester code generator/bit sequential buffer is not performed. this mode reduces the power consumption. for details, refer to 19.4.1 operation stop mode . (2) manchester code generator mode this mode is used to transmit manchester code from the mcgo pin. the transfer bit length can be set and transfers of various bit lengths are enabled. al so, the output level of the data transfer and lsb- or msb-first can be set for 8-bit transfer data. (3) bit sequential buffer mode this mode is used to transmit bit sequential data from the mcgo pin. the transfer bit length can be set and transfers of various bit lengths are enabled. al so, the output level of the data transfer and lsb- or msb-first can be set for 8-bit transfer data. 19.2 configuration of ma nchester code generator the manchester code generator includes the following hardware. table 19-1. configuration of manchester code generator item configuration registers mcg transmit buffer register (mc0tx) mcg transmit bit count specification register (mc0bit) control registers mcg control register 0 (mc0ctl0) mcg control register 1 (mc0ctl1) mcg control register 2 (mc0ctl2) mcg status register (mc0str) port mode register 3 (pm3) port register 3 (p3) chapter 19 manchester code generator user?s manual u18329ej4v0ud 572 figure 19-1. block diagram of manchester code generator intmcg mcgo/p32/toh0 f prs to f prs /2 5 internal bus control 8-bit shift register output control 3-bit counter selector mc0ctl1 mc0ctl2 brg mc0bit mc0tx mc0str mc0ctl0 p32 pm32 remark brg: baud rate generator f prs : peripheral hardware clock frequency mc0bit: mcg transmit bit count specification register mc0ctl2 to mc0ctl0: mcg control registers 2 to 0 mc0str: mcg status register mc0tx: mcg transmit buffer register figure 19-2. block diagra m of baud rate generator selector mc0ctl1: mc0cks2- mc0cks0 mc0ctl2: mc0brs4- mc0brs0 1/2 baud rate 5-bit counter f prs to f prs /2 5 remark f prs : peripheral hardware clock frequency mc0ctl2, mc0ctl 1: mcg control registers 2, 1 mc0cks2 to mc0cks0: bits 2 to 0 of mc0ctl1 register mc0brs4 to mc0brs0: bits 4 to 0 of mc0ctl2 register (1) mcg transmit buffer register (mc0tx) this register is used to set the transmit data. a transmi t operation starts when data is written to mc0tx while bit 7 (mc0pwr) of mcg control register 0 (mc0ctl0) is 1. the data written to mc0tx is converted into serial data by the 8-bit shift register, and output to the mcgo pin. manchester code or bit sequential data can be set as the output code using bit 1 (mc0osl) of mcg control register 0 (mc0ctl0). this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to ffh. chapter 19 manchester code generator user?s manual u18329ej4v0ud 573 (2) mcg transmit bit count sp ecification register (mc0bit) this register is used to set the number of transmit bits. set the transmit bit count to this register before setting the transmit data to mc0tx. in continuous transmission, the number of transmit bi ts to be transmitted next needs to be written after the occurrence of a transmission start interrupt (intmcg). ho wever, if the next transmit count is the same number as the previous transmit count, this r egister does not need to be written. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 07h. figure 19-3. format of mcg transmit bi t count specification register (mc0bit) address: ff4bh after reset: 07h r/w symbol 7 6 5 4 3 <2> <1> <0> mc0bit 0 0 0 0 0 mc0bit2 mc0bit1 mc0bit0 mc0bit2 mc0bit1 mc0bit0 transmit bit count setting 0 0 0 1 bit 0 0 1 2 bits 0 1 0 3 bits 0 1 1 4 bits 1 0 0 5 bits 1 0 1 6 bits 1 1 0 7 bits 1 1 1 8 bits remark when the number of transmit bits is set as 7 bits or smaller, the lower bits are always transmitted regardless of msb/lsb settings as the transmission start bit. ex. when the number of transmit bits is set as 3 bits, and d7 to d0 are written to mcg transmit buffer register (mc0tx) 7 6 5 4 3 2 1 0 mc0tx d7 d6 d5 d4 d3 d2 d1 d0 start bit: lsb d0 d1 d2 transmission order start bit: msb d2 d1 d0 transmission order transmit data chapter 19 manchester code generator user?s manual u18329ej4v0ud 574 19.3 registers controlling manchester code generator the following six types of registers are used to control the manchester code generator. ? mcg control register 0 (mc0ctl0) ? mcg control register 1 (mc0ctl1) ? mcg control register 2 (mc0ctl2) ? mcg status register (mc0str) ? port mode register 3 (pm3) ? port register 3 (p3) (1) mcg control register 0 (mc0ctl0) this register is used to set the operation mode and to enable/disable the operation. this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. figure 19-4. format of mcg c ontrol register 0 (mc0ctl0) address: ff4ch after reset: 10h r/w symbol <7> 6 5 <4> 3 2 <1> <0> mc0ctl0 mc0pwr 0 0 mc0dir 0 0 mc0osl mc0olv mc0pwr operation control 0 operation stopped 1 operation enabled mc0dir first bit specification 0 msb 1 lsb mc0osl data format 0 manchester code 1 bit sequential data mc0olv output level when transmission suspended 0 low level 1 high level caution clear (0) the mc0pwr bit before rewriti ng the mc0dir, mc0osl, and mc0olv bits (it is possible to rewrite these bits by an 8-bit memory manipulat ion instruction at the same time when the mc0pwr bit is set (1)). chapter 19 manchester code generator user?s manual u18329ej4v0ud 575 (2) mcg control register 1 (mc0ctl1) this register is used to set the base clock of the manchester code generator. this register can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. figure 19-5. format of mcg control register 1 (mc0ctl1) address: ff4dh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 mc0ctl1 0 0 0 0 0 mc0cks2 mc0cks1 mc0cks0 mc0cks2 mc0cks1 mc0cks0 base clock (f xclk ) selection note 1 0 0 0 f prs note 2 (10 mhz) 0 0 1 f prs /2 (5 mhz) 0 1 0 f prs /2 2 (2.5 mhz) 0 1 1 f prs /2 3 (1.25 mhz) 1 0 0 f prs /2 4 (625 khz) 1 0 1 f prs /2 5 (312.5 khz) 1 1 0 1 1 1 setting prohibited notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of mc0cks2 = mc0cks1 = mc0cks0 = 0 (base clock: f prs ) is prohibited. caution clear bit 7 (mc0pwr) of the mc0ctl0 re gister to 0 before rewriting the mc0cks2 to mc0cks0 bits. remarks 1. f prs : peripheral hardware clock frequency 2. figures in parentheses are for operation with f prs = 10 mhz. chapter 19 manchester code generator user?s manual u18329ej4v0ud 576 (3) mcg control register 2 (mc0ctl2) this register is used to set the transmit baud rate. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 1fh. figure 19-6. format of mcg control register 2 (mc0ctl2) address: ff4eh after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 mc0ctl2 0 0 0 mc0brs4 mc0brs3 mc0brs2 mc0brs1 mc0brs0 mc0brs4 mc0brs3 mc0brs2 mc0brs1 mc0brs0 k output clock selection of 5-bit counter 0 0 0 4 f xclk /4 0 0 1 0 0 4 f xclk /4 0 0 1 0 1 5 f xclk /5 0 0 1 1 0 6 f xclk /6 0 0 1 1 1 7 f xclk /7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 0 0 28 f xclk /28 1 1 1 0 1 29 f xclk /29 1 1 1 1 0 30 f xclk /30 1 1 1 1 1 31 f xclk /31 cautions 1. clear bit 7 (mc0pwr) of the mc0ctl0 register to 0 before rewriting the mc0brs4 to mc0brs0 bits. 2. the value from further dividing the output clock of the 5-bit counter by 2 is the baud rate value. remarks 1. f xclk : frequency of the base clock selected by the mc0cks2 to mc0cks0 bits of the mc0ctl1 register 2. k: value set by the mc0brs4 to mc0brs0 bits (k = 4, 5, 6, 7, ?., 31) 3. : don?t care (4) mcg status register (mc0str) this register is used to indicate the operat ion status of the manchester code generator. this register can be read by a 1-bit or 8-bit memory ma nipulation instruction. writing to this register is not possible. reset signal generation or setting mc0pwr = 0 clears this register to 00h. chapter 19 manchester code generator user?s manual u18329ej4v0ud 577 figure 19-7. format of mcg status register (mc0str) address: ff47h after reset: 00h r symbol <7> 6 5 4 3 2 1 0 mc0str mc0tsf 0 0 0 0 0 0 0 mc0tsf data transmission status 0 ? reset signal generation ? mc0pwr = 0 ? if the next transfer data is not written to mc0tx when a transmission is completed 1 transmission operation in progress caution this flag always indicates 1 during continuous tr ansmission. do not initialize a transmission operation without confirming that this flag has been cleared. 19.4 operation of manchester code generator the manchester code generator has the three modes described below. ? operation stop mode ? manchester code generator mode ? bit sequential buffer mode 19.4.1 operation stop mode transmissions are not performed in the o peration stop mode. ther efore, the power consumption can be reduced. in addition, the p32/toh0/mcgo pin is used as an ordinary i/o port in this mode. (1) register description mcg control register 0 (mc0ctl0) is used to set the operation stop mode. to set the operation stop mode, clear bit 7 (mc0pwr) of mc0ctl0 to 0. (a) mcg control register 0 (mc0ctl0) this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. address: ff4ch after reset: 10h r/w symbol <7> 6 5 <4> 3 2 <1> <0> mc0ctl0 mc0pwr 0 0 mc0dir 0 0 mc0osl mc0olv mc0pwr operation control 0 operation stopped chapter 19 manchester code generator user?s manual u18329ej4v0ud 578 19.4.2 manchester code generator mode this mode is used to transmit data in manche ster code format using the mcgo pin. (1) register description mcg control register 0 (mc0ctl0), mcg control regist er 1 (mc0ctl1), and mcg control register 2 (mc0ctl2) are used to set the manchester code generator mode. (a) mcg control register 0 (mc0ctl0) this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. address: ff4ch after reset: 10h r/w symbol <7> 6 5 <4> 3 2 <1> <0> mc0ctl0 mc0pwr 0 0 mc0dir 0 0 mc0osl mc0olv mc0pwr operation control 0 operation stopped 1 operation enabled mc0dir first bit specification 0 msb 1 lsb mc0osl data format 0 manchester code 1 bit sequential data mc0olv output level when transmission suspended 0 low level 1 high level caution clear (0) the mc0pwr bit before rewriti ng the mc0dir, mc0osl, and mc0olv bits (it is possible to rewrite these bits by an 8-bit memory manipulation instruction at the same time when the mc0pwr bit is set (1)). chapter 19 manchester code generator user?s manual u18329ej4v0ud 579 (b) mcg control register 1 (mc0ctl1) this register is used to set the base clock of the manchester code generator. this register can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. address: ff4dh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 mc0ctl1 0 0 0 0 0 mc0cks2 mc0cks1 mc0cks0 mc0cks2 mc0cks1 mc0cks0 base clock (f xclk ) selection note 1 0 0 0 f prs note 2 (10 mhz) 0 0 1 f prs /2 (5 mhz) 0 1 0 f prs /2 2 (2.5 mhz) 0 1 1 f prs /2 3 (1.25 mhz) 1 0 0 f prs /2 4 (625 khz) 1 0 1 1 1 0 1 1 1 f prs /2 5 (312.5 khz) notes 1. if the peripheral hardware clock (f prs ) operates on the high-speed system clock (f xh ) (xsel = 1), the f prs operating frequency varies depending on the supply voltage. ? v dd = 2.7 to 5.5 v: f prs 10 mhz ? v dd = 1.8 to 2.7 v: f prs 5 mhz 2. if the peripheral hardware clock (f prs ) operates on the internal high-speed oscillation clock (f rh ) (xsel = 0), when 1.8 v v dd < 2.7 v, the setting of mc0cks2 = mc0cks1 = mc0cks0 = 0 (base clock: f prs ) is prohibited. caution clear bit 7 (mc0pwr) of the mc0ctl0 re gister to 0 before rewriting the mc0cks2 to mc0cks0 bits. remarks 1. f prs : peripheral hardware clock frequency 2. figures in parentheses are for operation with f prs = 10 mhz. chapter 19 manchester code generator user?s manual u18329ej4v0ud 580 (c) mcg control register 2 (mc0ctl2) this register is used to set the transmit baud rate. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 1fh. address: ff4eh after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 mc0ctl2 0 0 0 mc0brs4 mc0brs3 mc0brs2 mc0brs1 mc0brs0 mc0brs4 mc0brs3 mc0brs2 mc0brs1 mc0brs0 k output clock selection of 5-bit counter 0 0 0 4 f xclk /4 0 0 1 0 0 4 f xclk /4 0 0 1 0 1 5 f xclk /5 0 0 1 1 0 6 f xclk /6 0 0 1 1 1 7 f xclk /7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 0 0 28 f xclk /28 1 1 1 0 1 29 f xclk /29 1 1 1 1 0 30 f xclk /30 1 1 1 1 1 31 f xclk /31 cautions 1. clear bit 7 (mc0pwr) of the mc0ctl0 register to 0 before rewriting the mc0brs4 to mc0brs0 bits. 2. the value from further dividing the output clock of the 5-bit counter by 2 is the baud rate value. remarks 1. f xclk : frequency of the base clock selected by the mc0cks2 to mc0cks0 bits of the mc0ctl1 register 2. k: value set by the mc0brs4 to mc0brs0 bits (k = 4, 5, 6, 7, ?., 31) 3. : don?t care <1> baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk : frequency of base clock selected by the mc0cks2 to mc0cks0 bits of the mc0ctl1 register k: value set by the mc0brs4 to mc0brs0 bits of the mc0ctl2 register (k = 4, 5, 6, ..., 31) f xclk 2 k chapter 19 manchester code generator user?s manual u18329ej4v0ud 581 <2> error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] caution keep the baud rate error during transmi ssion to within the permissible error range at the reception destination. example: frequency of base clock = 2.5 mhz = 2,500,000 hz set value of mc0brs4 to mc0brs0 bits of mc0ctl2 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] <3> example of setting baud rate f prs = 10.0 mhz f prs = 8.38 mhz f prs = 8.0 mhz f prs = 6.0 mhz baud rate [bps] mc0cks2 to mc0cks0 k calculated value err [%] mc0cks2 to mc0cks0 k calculated value err [%] mc0cks2 to mc0cks0 k calculated value err [%] mc0cks2 to mc0cks0 k calculated value err [%] 4800 ? ? ? ? 5, 6, or 7 27 4850 1.03 5, 6, or 7 26 4808 0.16 5, 6, or 7 20 4688 ?2.34 9600 5, 6, or 7 16 9766 1.73 4 27 9699 1.03 5, 6, or 7 13 9615 0.16 4 20 9375 ?2.34 19200 5 8 19531 1.73 3 27 19398 1.03 4 13 19231 0.16 4 10 18750 ?2.34 31250 4 10 31250 0 2 17 30809 ?1.41 4 8 31250 0 2 24 31250 0 38400 4 8 39063 1.73 2 27 38796 1.03 3 13 38462 0.16 2 20 37500 ?2.34 56000 3 11 56818 1.46 2 19 55132 ?1.55 3 9 55556 ?0.79 1 27 55556 ?0.79 62500 2 20 62500 0 2 17 61618 ?1.41 3 8 62500 0 2 12 62500 0 76800 2 16 78125 1.73 1 27 77592 1.03 2 13 76923 0.16 2 10 75000 ?2.34 115200 1 22 113636 ?1.36 2 9 116389 1.03 1 17 117647 2.12 1 13 115385 0.16 125000 1 20 125000 0 1 17 123235 ?1.41 1 16 125000 0 1 12 125000 0 153600 1 16 156250 1.73 2 7 149643 ?2.58 1 13 153846 0.16 1 10 150000 ?2.34 1 8 261875 4.75 250000 1 10 250000 0 0 17 246471 ?1.41 1 8 250000 0 1 6 250000 0 remark mc0cks2 to mc0cks0: bits 2 to 0 of mcg contro l register 1 (mc0ctl1) (setting of base clock (f xclk )) k: value set by bits 4 to 0 (mc0brs4 to mc0brs0) of mcg control register 2 (mc0ctl2) (k = 4, 5, 6, ?, 31) f prs : peripheral hardware clock frequency err: baud rate error actual baud rate (baud rate with error) desired baud rate (correct baud rate) chapter 19 manchester code generator user?s manual u18329ej4v0ud 582 (d) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p32/toh0/mcgo pin for manchester code output, clear pm32 to 0 and clear the output latch of p32 to 0. pm3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) (2) format of "0" and "1" of manchester code output the format of "0" and "1" of manchester code output in 78k0/lf3 is as follows. "0" "1" mcgo pin chapter 19 manchester code generator user?s manual u18329ej4v0ud 583 (3) transmit operation in manchester code generator mode, data is transmitted in 1- to 8-bit units. data bits are transmitted in manchester code format. transmission is enabled if bit 7 (mc0pwr) of mcg control register 0 (mc0ctl0) is set to 1. the output value while a transmission is suspended can be set by using bit 0 (mc0olv) of the mc0ctl0 register. a transmission starts by writing a value to the mcg tr ansmit buffer register (mc0tx) after setting the transmit data bit length to the mcg transmit bit c ount specification register (mc0bit). at the transmission start timing, the mc0bit value is transferred to the 3-bi t counter and the data of mc 0tx is transferred to the 8-bit shift register. an interrupt request signal (intmcg) occurs at the timing that the mc0tx value is transferred to the 8-bit shift register. the 8-bit shift register is continuously shift ed by the baud rate clock, and si gnal that is xored with the baud rate clock is output from the mcgo pin. when continuous transmission is exec uted, the next data is set to mc0bit and mc0tx during data transmission after intmcg occurs. to transmit continuously, writing the next transfer data to mc0tx must be complete within the period (3) and (4) in figure 19-8. rewrite the mc 0bit before writing to mc0tx dur ing continuous transmission. figure 19-8. timing of manchester code generator mode (l sb first) (1/4) (1) transmit timing (mc0olv = 1, to tal transmit bit length = 8 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx 3-bit counter mc0tsf intmcg mcgo pin 8-bit shift register baud rate clock ?111? ?10010110? (8-bit data) ?111? ?110? ?101? ?100? ?011? ?010? ?001? ?000? ?10010110? ?x1001011? ?xx100101? ?xxx10010? ?xxxx1001? ?xxxxx100? ?xxxxxx10? ?xxxxxxx1? ?l? chapter 19 manchester code generator user?s manual u18329ej4v0ud 584 figure 19-8. timing of manchester code generator mode (l sb first) (2/4) (2) transmit timing (mc0olv = 0, to tal transmit bit length = 8 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx 3-bit counter mc0tsf intmcg mcgo pin 8-bit shift register baud rate clock ?111? ?10010110? (8-bit data) ?111? ?110? ?101? ?100? ?011? ?010? ?001? ?000? ?10010110? ?x1001011? ?xx100101? ?xxx10010? ?xxxx1001? ?xxxxx100? ?xxxxxx10? ?xxxxxxx1? ?l? ?l? chapter 19 manchester code generator user?s manual u18329ej4v0ud 585 figure 19-8. timing of manchester code generator mode (l sb first) (3/4) (3) transmit timing (mc0olv = 1, to tal transmit bit length = 13 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx mc0tsf intmcg " 010 " " 001 " " 011 " " 100 " " 100 " " 111 " " 000 " " 001 " " 010 " " 011 " " 100 " " 101 " " 110 " " 111 " " 000 " write write write write (b) (a) " 10100101 " (8-bit data) " xxx10100 " ( 5-bit data) "1010 0101" "x101 0010" "xx10 1001" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" mcgo pin baud rate clock 8-bit shift register 3-bit counter " l " (a): ?8-bit transfer period? ? (b) (b): ?1/2 cycle of baud rate? + 1 clock (f xclk ) before the last bit of transmit data f xclk : frequency of the operation base clock select ed by using the mc0cks2 to mc0cks0 bits of the mc0ctl1 register last bit: transfer bit when 3-bit counter = 000 caution writing the next transmit data to mc0tx must be comple te within the period (a) during continuous transmission. if writing the next tr ansmit data to mc0tx is executed in the period (b), the next data tran smission starts 2 clocks (f xclk ) after the last bit h as been transmitted. rewrite the mc0bit before writing to mc0tx during continuous transmission. chapter 19 manchester code generator user?s manual u18329ej4v0ud 586 figure 19-8. timing of manchester code generator mode (l sb first) (4/4) (4) transmit timing (mc0olv = 0, to tal transmit bit length = 13 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx mc0tsf intmcg " 010 " " 001 " " 011 " " 100 " " 100 " " 111 " " 000 " " 001 " " 010 " " 011 " " 100 " " 101 " " 110 " " 111 " " 000 " write write write write (b) (a) " l " " l " "1010 0101" "x101 0010" "xx10 1001" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" " 10100101 " (8-bit data) " xxx10100 " (5-bit data) 3-bit counter 8-bit shift register baud rate clock mcgo pin (a): ?8-bit transfer period? ? (b) (b): ?1/2 cycle of baud rate? + 1 clock (f xclk ) before the last bit of transmit data f xclk : frequency of the operation base clock select ed by using the mc0cks2 to mc0cks0 bits of the mc0ctl1 register last bit: transfer bit when 3-bit counter = 000 caution writing the next transmit data to mc0tx must be comple te within the period (a) during continuous transmission. if writing the next tr ansmit data to mc0tx is executed in the period (b), the next data tran smission starts 2 clocks (f xclk ) after the last bit h as been transmitted. rewrite the mc0bit before writing to mc0tx during continuous transmission. chapter 19 manchester code generator user?s manual u18329ej4v0ud 587 19.4.3 bit sequential buffer mode the bit sequential buffer mode is used to ou tput sequential signals using the mcgo pin. (1) register description the mcg control register 0 (mc0ctl0), mcg control register 1 (mc0ctl1), and mcg control register 2 (mc0ctl2) are used to set the bit sequential buffer mode. (a) mcg control register 0 (mc0ctl0) this register can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets this register to 10h. address: ff4ch after reset: 10h r/w symbol <7> 6 5 <4> 3 2 <1> <0> mc0ctl0 mc0pwr 0 0 mc0dir 0 0 mc0osl mc0olv mc0pwr operation control 0 operation stopped 1 operation enabled mc0dir first bit specification 0 msb 1 lsb mc0osl data format 0 manchester code 1 bit sequential data mc0olv output level when transmission suspended 0 low level 1 high level caution clear (0) the mc0pwr bit before rewriti ng the mc0dir, mc0osl, and mc0olv bits (it is possible to rewrite these bits by an 8-bit memory manipulation instruction at the same time when the mc0pwr bit is set (1)). chapter 19 manchester code generator user?s manual u18329ej4v0ud 588 (b) mcg control register 1 (mc0ctl1) this register is used to set the base clock of the manchester code generator. this register can be set by an 8-bit memory manipulation instruction. reset signal generation clears this register to 00h. address: ff4dh after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 mc0ctl1 0 0 0 0 0 mc0cks2 mc0cks1 mc0cks0 mc0cks2 mc0cks1 mc0cks0 base clock (f xclk ) selection 0 0 0 f prs (10 mhz) 0 0 1 f prs /2 (5 mhz) 0 1 0 f prs /2 2 (2.5 mhz) 0 1 1 f prs /2 3 (1.25 mhz) 1 0 0 f prs /2 4 (625 khz) 1 0 1 1 1 0 1 1 1 f prs /2 5 (312.5 khz) caution clear bit 7 (mc0pwr) of the mc0ctl0 re gister to 0 before rewriting the mc0cks2 to mc0cks0 bits. remarks 1. f prs : peripheral hardware clock frequency 2. figures in parentheses are for operation with f prs = 10 mhz. chapter 19 manchester code generator user?s manual u18329ej4v0ud 589 (c) mcg control register 2 (mc0ctl2) this register is used to set the transmit baud rate. this register can be set by an 8-bit memory manipulation instruction. reset signal generation sets this register to 1fh. address: ff4eh after reset: 1fh r/w symbol 7 6 5 4 3 2 1 0 mc0ctl2 0 0 0 mc0brs4 mc0brs3 mc0brs2 mc0brs1 mc0brs0 mc0brs4 mc0brs3 mc0brs2 mc0brs1 mc0brs0 k output clock selection of 5-bit counter 0 0 0 4 f xclk /4 0 0 1 0 0 4 f xclk /4 0 0 1 0 1 5 f xclk /5 0 0 1 1 0 6 f xclk /6 0 0 1 1 1 7 f xclk /7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 0 0 28 f xclk /28 1 1 1 0 1 29 f xclk /29 1 1 1 1 0 30 f xclk /30 1 1 1 1 1 31 f xclk /31 cautions 1. clear bit 7 (mc0pwr) of the mc0ctl0 register to 0 before rewriting the mc0brs4 to mc0brs0 bits. 2. the value from further dividing the output clock of the 5-bit counter by 2 is the baud rate value. remarks 1. f xclk : frequency of the base clock selected by the mc0cks2 to mc0cks0 bits of the mc0ctl1 register 2. k: value set by the mc0brs4 to mc0brs0 bits (k = 4, 5, 6, 7, ?., 31) 3. : don?t care <1> baud rate the baud rate can be calculated by the following expression. ? baud rate = [bps] f xclk : frequency of base clock selected by the mc0cks2 to mc0cks0 bits of the mc0ctl1 register k: value set by the mc0brs4 to mc0brs0 bits of the mc0ctl2 register (k = 4, 5, 6, ..., 31) f xclk 2 k chapter 19 manchester code generator user?s manual u18329ej4v0ud 590 <2> error of baud rate the baud rate error can be calculated by the following expression. ? error (%) = ? 1 100 [%] caution keep the baud rate error during transmi ssion to within the permissible error range at the reception destination. example: frequency of base clock = 2.5 mhz = 2,500,000 hz set value of mc0brs4 to mc0brs0 bits of mc0ctl2 register = 10000b (k = 16) target baud rate = 76,800 bps baud rate = 2.5 m/(2 16) = 2,500,000/(2 16) = 78125 [bps] error = (78,125/76,800 ? 1) 100 = 1.725 [%] <3> example of setting baud rate f prs = 10.0 mhz f prs = 8.38 mhz f prs = 8.0 mhz f prs = 6.0 mhz baud rate [bps] mc0cks2 to mc0cks0 k calculated value err [%] mc0cks2 to mc0cks0 k calculated value err [%] mc0cks2 to mc0cks0 k calculated value err [%] mc0cks2 to mc0cks0 k calculated value err [%] 4800 ? ? ? ? 5, 6, or 7 27 4850 1.03 5, 6, or 7 26 4808 0.16 5, 6, or 7 20 4688 ?2.34 9600 5, 6, or 7 16 9766 1.73 4 27 9699 1.03 5, 6, or 7 13 9615 0.16 4 20 9375 ?2.34 19200 5 8 19531 1.73 3 27 19398 1.03 4 13 19231 0.16 4 10 18750 ?2.34 31250 4 10 31250 0 2 17 30809 ?1.41 4 8 31250 0 2 24 31250 0 38400 4 8 39063 1.73 2 27 38796 1.03 3 13 38462 0.16 2 20 37500 ?2.34 56000 3 11 56818 1.46 2 19 55132 ?1.55 3 9 55556 ?0.79 1 27 55556 ?0.79 62500 2 20 62500 0 2 17 61618 ?1.41 3 8 62500 0 2 12 62500 0 76800 2 16 78125 1.73 1 27 77592 1.03 2 13 76923 0.16 2 10 75000 ?2.34 115200 1 22 113636 ?1.36 2 9 116389 1.03 1 17 117647 2.12 1 13 115385 0.16 125000 1 20 125000 0 1 17 123235 ?1.41 1 16 125000 0 1 12 125000 0 153600 1 16 156250 1.73 2 7 149643 ?2.58 1 13 153846 0.16 1 10 150000 ?2.34 1 8 261875 4.75 250000 1 10 250000 0 0 17 246471 ?1.41 1 8 250000 0 1 6 250000 0 remark mc0cks2 to mc0cks0: bits 2 to 0 of mcg contro l register 1 (mc0ctl1) (setting of base clock (f xclk )) k: value set by bits 4 to 0 (mc0brs4 to mc0brs0) of mcg control register 2 (mc0ctl2) (k = 4, 5, 6, ?, 31) f prs : peripheral hardware clock frequency err: baud rate error actual baud rate (baud rate with error) desired baud rate (correct baud rate) chapter 19 manchester code generator user?s manual u18329ej4v0ud 591 (d) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p32/toh0/mcgo pin for bit sequential data output, clear pm32 to 0 and clear the output latch of p32 to 0. pm3 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets these registers to ffh. address: ff23h after reset: ffh r/w symbol 7 6 5 4 3 2 1 0 pm3 1 1 1 pm34 pm33 pm32 pm31 pm30 pm3n p3n pin i/o mode selection (n = 0 to 4) 0 output mode (output buffer on) 1 input mode (output buffer off) chapter 19 manchester code generator user?s manual u18329ej4v0ud 592 (2) transmit operation in bit sequential buffer mode, data is transmitted in 1- to 8-bit units. transmission is enabled if bit 7 (mc0pwr) of mcg control register 0 (mc0ctl0) is set to 1. the output value while transmission is suspended can be se t by using bit 0 (mc0olv) of the mc0ctl0 register. a transmission starts by writing a value to the mcg tr ansmit buffer register (mc0tx) after setting the transmit data bit length to the mcg transmit bit c ount specification register (mc0bit). at the transmission start timing, the mc0bit value is transferred to the 3-bit counter and data of mc0tx is transferred to the 8-bit shift register. an interrupt request signal (intmcg) occurs at the timing that the mc0tx value is transferred to the 8-bit shift register. the 8-bit shift register is continuously shi fted by the baud rate clock and is output from the mcgo pin. when continuous transmission is exec uted, the next data is set to mc0bit and mc0tx during data transmission after intmcg occurs. to transmit continuously, writing the next transfer data to mc0tx must be complete within the period (3) and (4) in figure 19-9. rewrite mc0bit before writ ing to mc0tx during continuous transmission. figure 19-9. timing of bit sequentia l buffer mode (lsb first) (1/4) (1) transmit timing (mc0olv = 1, to tal transmit bit length = 8 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx 3-bit counter mc0tsf intmcg mcgo pin 8-bit shift register baud rate clock ?111? ?10010110? (8-bit data) ?111? ?110? ?101? ?100? ?011? ?010? ?001? ?000? ?10010110? ?x1001011? ?xx100101? ?xxx10010? ?xxxx1001? ?xxxxx100? ?xxxxxx10? ?xxxxxxx1? chapter 19 manchester code generator user?s manual u18329ej4v0ud 593 figure 19-9. timing of bit sequentia l buffer mode (lsb first) (2/4) (2) transmit timing (mc0olv = 0, to tal transmit bit length = 8 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx 3-bit counter mc0tsf intmcg mcgo pin 8-bit shift register baud rate clock ?111? ?10010110? (8-bit data) ?111? ?110? ?101? ?100? ?011? ?010? ?001? ?000? ?10010110? ?x1001011? ?xx100101? ?xxx10010? ?xxxx1001? ?xxxxx100? ?xxxxxx10? ?xxxxxxx1? ?l? chapter 19 manchester code generator user?s manual u18329ej4v0ud 594 figure 19-9. timing of bit sequentia l buffer mode (lsb first) (3/4) (3) transmit timing (mc0olv = 1, to tal transmit bit length = 13 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx mc0tsf intmcg " 010 " " 001 " " 011 " " 100 " " 100 " " 111 " " 000 " " 001 " " 010 " " 011 " " 100 " " 101 " " 110 " " 111 " " 000 " write write write write "1010 0101" "x101 0010" "xx10 1001" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" " 10100101 " (8-bit data) " xxx10100 " (5-bit data) 3-bit counter 8-bit shift register baud rate clock mcgo pin (a) (b) (a): ?8-bit transfer period? ? (b) (b): ?1/2 cycle of baud rate? + 1 clock (f xclk ) before the last bit of transmit data f xclk : frequency of operation base clock selected by using the mc0cks2 to mc0cks0 bits of the mc0ctl1 register last bit: transfer bit when 3-bit counter = 000 caution writing the next transmit data to mc0tx must be comple te within the period (a) during continuous transmission. if writing the next tr ansmit data to mc0tx is executed in the period (b), the next data tran smission starts 2 clocks (f xclk ) after the last bit h as been transmitted. rewrite the mc0bit before writing to mc0tx during continuous transmission. chapter 19 manchester code generator user?s manual u18329ej4v0ud 595 figure 19-9. timing of bit sequentia l buffer mode (lsb first) (4/4) (4) transmit timing (mc0olv = 0, to tal transmit bit length = 13 bits) mc0pwr mc0olv mc0osl mc0bit mc0tx mc0tsf intmcg " 010 " " 001 " " 011 " " 100 " " 100 " " 111 " " 000 " " 001 " " 010 " " 011 " " 100 " " 101 " " 110 " " 111 " " 000 " write write write write " l " "1010 0101" "x101 0010" "xx10 1001" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" "xxx1 0100" "xxxx 1010" "xxxx x101" "xxxx xx10" "xxxx xxx1" " 10100101 " (8-bit data) " xxx10100 " ( 5-bit data) 3-bit counter 8-bit shift register baud rate clock mcgo pin (b) (a) (a): ?8-bit transfer period? ? (b) (b): ?1/2 cycle of baud rate? + 1 clock (f xclk ) before the last bit of transmit data f xclk : frequency of operation base clock selected by using the mc0cks2 to mc0cks0 bits of the mc0ctl1 register last bit: transfer bit when 3-bit counter = 000 caution writing the next transmit data to mc0tx must be comple te within the period (a) during continuous transmission. if writing the next tr ansmit data to mc0tx is executed in the period (b), the next data tran smission starts 2 clocks (f xclk ) after the last bit h as been transmitted. rewrite the mc0bit before writing to mc0tx during continuous transmission. user?s manual u18329ej4v0ud 596 chapter 20 remote controller receiver 20.1 remote controller receiver functions the remote controller receiver uses the following remote controller modes. ? type a reception mode ? guide pulse (half clock) provided ? type b reception mode ? guide pulse (1clock) provided ? type c reception mode ? guide pulse not provided 20.2 remote controller receiver configuration the remote controller receiver includes the following hardware. table 20-1. remote contro ller receiver configuration item configuration registers remote controller receive shift register (rmsr) remote controller receive data register (rmdr) remote controller shift register receive counter register (rmscr) remote controller receive gpls compare register (rmgpls) remote controller receive gpll compare register (rmgpll) remote controller receive gphs compare register (rmgphs) remote controller receive gphl compare register (rmgphl) remote controller receive dls compare register (rmdls) remote controller receive dll compare register (rmdll) remote controller receive dh0s compare register (rmdh0s) remote controller receive dh0l compare register (rmdh0l) remote controller receive dh1s compare register (rmdh1s) remote controller receive dh1l compare register (rmdh1l) remote controller receive end width select register (rmer) control register remote controller receive interrupt status register (ints) remote controller receive interrupt status clear register (intc) remote controller receive control register (rmcn) chapter 20 remote controller receiver user?s manual u18329ej4v0ud 597 figure 20-1. block diagram of remote controller receiver rin/p41/kr1 noise canceler clock counter selector remote controller receive control register ( rmcn) internal bus rmcd0 prsen rmck1 rmck0 rmin rmcd1 input control edge detection compare register rmgpls rmgpll rmgphs rmgphl rmdls rmdll rmdh0s rmdh0l ncw rmen register selection comparator data detection selection control signal remote controller shift register receive counter register (rmscr) intdfull remote controller receive shift register (rmsr) remote controller receive data register (rmdr) intrerr intrend intgp intrin rmin rmen ncw rmdh1s rmdh1l end-width select register ( rmer) 6 7 8 selector f prs /2 f prs /2 f prs /2 f sub rmmd1, rmmd0 f remprs f rem 1/2 (1) remote controller receive shift register (rmsr) this is an 8-bit register for reception of remote controller data. data is stored in bit 7 first. each time new data is stor ed, the stored data is shifted to the lower bits. therefore, the latest data is stored in bit 7, and the first data is stored in bit 0. rmsr is read with an 8-bit memory manipulation instruction. reset signal generation sets rmsr to 00h. also, rmsr is cleared to 00h under any of the following conditions. ? remote controller stops operation (rmen = 0). ? error is detected (intrerr is generated). ? intdfull is generated. ? rmsr is read after intrend has been generated. caution reading rmsr is disable d during remote controller recepti on. complete reception, then read rmsr. when the reading operation is complete, rmsr is cleared. therefore, values once read are not guaranteed. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 598 (2) remote controller receive data register (rmdr) this register holds the remote contro ller reception data. when the remote controller receive shift register (rmsr) overflows, the data in rmsr is transferred to rmdr. bit 7 stores the last data, and bit 0 stores the first data. intdfull is generated at the same time as data is transferred from rmsr to rmdr. rmdr is read with an 8-bit memory manipulation instruction. reset signal generation sets rmdr to 00h. when the remote controller operation is disabled (rmen = 0), rmdr is cleared to 00h. caution when intdfull has been generated, read rmdr before the next 8-bit data is received. if the next intdfull is generated be fore the read operation is co mplete, rmdr is overwritten. (3) remote controller shift register receive counter register (rmscr) this is a 3-bit counter register used to indicate the nu mber of valid bits remaining in the remote controller receive shift register (rmsr) when remote controller reception is complete (intrend is generated). reading the values of this register allows c onfirmation of the number of bits, even if the received data is in a format other than an integral multiple of 8 bits. rmscr is read with an 8-bit memory manipulation instruction. reset signal generation sets rmscr to 00h. it is cleared to 00h under any of the following conditions. ? remote controller stops operation (rmen = 0). ? error is detected (intrerr is generated). ? rmsr is read after intrend has been generated. caution when intrend has been generated, imme diately read rmscr before reading rmsr. if reading occurs at another timing, the value is not guaranteed. figure 20-2. operation examples of rmsr, rmscr, and rmdr registers when receiving 1010101011111111b (16 bits) rmsr 7 6 5 4 3 2 1 0 rmscr rmdr after reset 0 0 0 0 0 0 0 0 00h 00000000b receiving 1 bit 1 0 0 0 0 0 0 0 01h 00000000b receiving 2 bits 0 1 0 0 0 0 0 0 02h 00000000b receiving 3 bits 1 0 1 0 0 0 0 0 03h 00000000b ? ? ? ? ? ? ? ? ? ? ? receiving 7 bits 1 0 1 0 1 0 1 0 07h 00000000b receiving 8 bits rmdr transfer 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 00h 00h 00000000b 01010101b receiving 9 bits 1 0 0 0 0 0 0 0 01h 01010101b receiving 10 bits 1 1 0 0 0 0 0 0 02h 01010101b ? ? ? ? ? ? ? ? ? ? ? receiving 16 bits rmdr transfer 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 00h 00h 01010101b 11111111b chapter 20 remote controller receiver user?s manual u18329ej4v0ud 599 (4) remote controller receive gpls compare re gister (rmgpls) (type b reception mode) this register is used to detect the low level of a remote controller guide pulse (short side). rmgpls is set with an 8-bit memory manipulation instruction. reset signal generation sets rmgpls to 00h. (5) remote controller receive gpll compare re gister (rmgpll) (type b reception mode) this register is used to detect the low level of a remote controller guide pulse (long side). rmgpll is set with an 8-bit memory manipulation instruction. reset signal generation sets rmgpll to 00h. rin counter value rmgpls register value rmgpll register value guide pulse allowable range if rmgpls counter value < rmgpll is satisfied, it is assumed that the low level of the guide pulse has been successfully received. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 600 (6) remote controller receive gphs compare register (rmgphs) (type a, type b reception mode only) this register is used to detect the high level of a remote controller guide pulse (short side). rmgphs is set with an 8-bit memory manipulation instruction. reset signal generation sets rmgphs to 00h. (7) remote controller receive gphl compare register (rmgphl) (type a, type b reception mode only) this register is used to detect the high level of a remote controller guide pulse (long side). rmgphl is set with an 8-bit memory manipulation instruction. reset signal generation sets rmgphl to 00h. (a) type a reception mode rin allowable range counter value rmgphs register value rmgphl register value guide pulse if rmgphs counter value < rmgphl is satisfied, it is assumed that the high level of the guide pulse has been successfully received. (b) type b reception mode rin counter value rmgphs register value rmgphl register value guide pulse allowable range if rmgphs counter value < rmgphl is satisfied, it is assumed that the high level of the guide pulse has been successfully received. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 601 (8) remote controller receive dls compare register (rmdls) this register is used to detect the low level of a remote controller data (short side). rmdls is set with an 8-bit memory manipulation instruction. reset signal generation sets rmdls to 00h. (9) remote controller receive d ll compare register (rmdll) this register is used to detect the low level of a remote controller data (long side). rmdll is set with an 8-bit memory manipulation instruction. reset signal generation sets rmdll to 00h. rin counter value rmdls register value rmdll register value data 0 or data 1 allowable range , rin note note if rmdls counter value < rmdll is satisfied, it is assumed that the low level of data 0 or data 1 has been successfully received. note rin is generated in type a reception mode, and rin is generated in type b and type c reception modes. (10) remote controller receive dh0 s compare register (rmdh0s) this register is used to detect the high level of a remote controller data 0 (short side). rmdh0s is set with an 8-bit memory manipulation instruction. reset signal generation sets rmdh0s to 00h. (11) remote controller receive dh0 l compare register (rmdh0l) this register is used to detect the high level of a remote controller data 0 (long side). rmdh0l is set with an 8-bit memory manipulation instruction. reset signal generation sets rmdh0l to 00h. allowable range counter value rmdh0s register value rmdh0l register value data 0 rin , rin note note if rmdh0s counter value < rmdh0l is satisfied, it is assumed that the high level of data 0 has been successfully received, and therefore rmsr receives the data. note rin is generated in type a reception mode, and rin is generated in type b and type c reception modes. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 602 (12) remote controller receive dh1 s compare register (rmdh1s) this register is used to detect the high level of remote controller data 1 (short side). rmdh1s is set with an 8-bit memory manipulation instruction. reset signal generation sets rmdh1s to 00h. (13) remote controller receive dh1 l compare register (rmdh1l) this register is used to detect the high level of remote controller data 1 (long side). rmdh1l is set with an 8-bit memory manipulation instruction. reset signal generation sets rmdh1l to 00h. allowable range counter value rmdh1s register value rmdh1l register value data 1 rin , rin note note if rmdh1s counter value < rmdh1l is satisfied, it is assumed that the high level of data 0 has been successfully received, and therefore rmsr receives the data. note rin is generated in type a reception mode, and rin is generated in type b and type c reception modes. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 603 (14) remote controller receive end-width select register (rmer) this register determines the interval between the timing at which the intrend signal is output. rmer is set with an 8-bit memory manipulation instruction. reset signal generation sets rmer to 00h. (a) type a reception mode rin counter value = rmer data rmdll intrend counter (b) type b, type c reception mode rin counter value = rmer data rmdh0l intrend counter rmdh1l caution for rmer and all the remote controller receive compare registers (rmgpls, rmgpll, rmgphs, rmgphl, rmdls, rmdll, rmdh0s, rmdh0l, rmdh1s, and rmdh1l), disable remote controller reception (bit 7 (rmen) of th e remote controller receive control register (rmcn) = 0) first, and then change the value. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 604 20.3 registers to control remote controller receiver the remote controller receiver is controlled by the following register. ? remote controller receive interrupt status register (ints) ? remote controller re ceive interrupt status clear register (intc) ? remote controller receive control register (rmcn) (1) remote controller receive inte rrupt status register (ints) this register is used to identify which interrupt reques t among the remote control receive interrupts (intrerr, intgp, intrend, intd full) has occurred. ints is set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets ints to 00h. figure 20-3. format of remote controller r eceive interrupt status register (ints) symbol 7 6 5 4 3 2 1 0 address after reset r/w ints 0 0 0 0 ints dfull ints rend ints gp ints rerr fff9h 00h r ints dfull interrupt request by reading of 8-bit shift data 0 interrupt request by reading of 8-bit shift data has not occurred 1 interrupt request by reading of 8-bit shift data has occurred ints rend request by data reception completion interrupt 0 request by data reception completion interrupt has not occurred 1 request by data reception completion interrupt has occurred ints gp guide pulse detection interrupt 0 guide pulse detection interrupt request has not occurred 1 guide pulse detection interrupt request has occurred ints rerr interrupt request by remote control receive error 0 interrupt request by remote control receive error has not occurred 1 interrupt request by remote control receive error has occurred caution the ints register will not be cleared even if it is read. use the intc re gister to clear the ints register. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 605 (2) remote controller receive interrupt status clear register (intc) this register is used to control the remote cont roller receive interrupt status register (ints). intc is set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets intc to 00h. figure 20-4. format of remote controller recei ve interrupt status clear register (intc) symbol 7 6 5 4 3 2 1 0 address after reset r/w intc 0 0 0 0 intc dfull intc rend intc gp intc rerr fffah 00h r/w intc dfull interrupt identification bit contro l by reading of 8-bit shift data 0 intsdfull bit not changed 1 intsdfull bit cleared intc rend data reception completion interrupt identification bit control 0 intsrend bit not changed 1 intsrend bit cleared intc gp guide pulse detection interrupt identification bit control 0 intsgp bit not changed 1 intsgp bit cleared intc rerr interrupt identification bit control by remote control receive error 0 intsrerr bit not changed 1 intsrerr bit cleared chapter 20 remote controller receiver user?s manual u18329ej4v0ud 606 (3) remote controller receive control register (rmcn) this register is used to enable/disable remote controller reception and to set the noise elimination width, clock internal division, input invert signal, and source clock. rmcn is set with a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets rmcn to 00h. figure 20-5. format of remote contro ller receive control register (rmcn) symbol 7 6 5 4 3 2 1 0 address after reset r/w rmcn rmen ncw prsen rmin rmmd1 rmmd0 rmck1 rmck0 ff9ah 00h r/w rmen control of remote controller receive operation 0 disable remote controller reception 1 enable remote controller reception ncw noise elimination width control signal 0 eliminate noise less than 1/f remprs 1 eliminate noise less than 2/f remprs prsen internal clock division control signal 0 clock not divided internally (f remprs = f rem ) 1 clock internally divided into two (f remprs = f rem /2) rmin remote controller input invert signal 0 input positive phase 1 input negative phase rmmd1 rmmd0 remote controller reception mode 0 0 type a reception mode (guide pulse (half clock) provided) 0 1 type b reception mode (guide pulse (1 clock) provided) 1 0 type c reception mode (guide pulse not provided) 1 1 setting prohibited rmck1 rmck0 selecti on of source clock (f rem ) of remote controller counter 0 0 f prs /2 6 (156.25 khz) 0 1 f prs /2 7 (78.125 khz) 1 0 f prs /2 8 (39.063 khz) 1 1 f sub (32.768 khz) caution to change the values of ncw, prsen, rmin, rmmd1, rmmd0, rmck1, and rmck0, disable remote controller reception (rmen = 0) first. remark 1. f rem : source clock of remote controller counter (selected by bits 0 and 1 (rmck0 and rmck1)) chapter 20 remote controller receiver user?s manual u18329ej4v0ud 607 remarks 2. f remprs : operation clock inside remote controller receiver 3. f prs : peripheral hardware clock frequency 4. f sub : oscillation frequency of subsystem clock 5. the parenthesized values apply to operation at f prs = 10 mhz and f sub = 32.768 khz. 20.4 operation of remote controller receiver the following remote controller reception mode is used for this remote controller receiver. ? type a reception mode with guide pulse (half clock) ? type b reception mode with guide pulse (1clock) ? type c reception mode without guide pulse 20.4.1 format of type a reception mode figure 20-6 shows the data format for type a. figure 20-6. example of type a data format rin intdfull guide pulse intgp rmer data ?0? data ?1? 0.6 ms 1.8 ms 1.2 ms 2.4 ms intrin intrend rmdll data ?1? data ?0? data ?0? data ?0? data ?0? data ?0? data ?0? 20.4.2 operation flow of type a reception mode figure 20-7 shows the operation flow. cautions 1. when intrerr is generated, rmsr and rmscr are automatically cleared immediately. 2. when data has been set to all the bits of rmsr, the following processing is automatically performed. ? the value of rmsr is transferred to rmdr. ? intdfull is generated. ? rmsr is cleared. rmdr must then be read before the next data is set to all the bits of rmsr. 3. when intrend has been generated, read rmscr first followed by rmsr. when rmsr has been read, rmscr and rmsr are automatically cleared. if intrend is generated, the next da ta cannot be received until rmsr is read. 4. rmsr, rmscr, and rmdr are cleared si multaneously to operation termination (rmen = 0). chapter 20 remote controller receiver user?s manual u18329ej4v0ud 608 figure 20-7. operation flow of type a reception mode longer than end interval? no yes start yes no generate intgp set data to all bits of rmsr ok? no guide pulse high level width ok? data low level width ok? generate intrend read rmscr process received data receive operation completed yes data high level width ok? set data to rmsr end no no yes yes yes generate intrerr no yes clear rmsr and rmscr clear rmsr, rmscr, and rmdr rmsr rmdr generate intdfull clear rmsr read rmsr clear rmsr and rmscr : software processing (user executes via program) : hardware processing (macro automatically performs) read rmdr note set compare registers operation enabled ( rmen = 1) terminate operation ( rmen = 0) note read rmdr before data has been set to all the bits of rmsr. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 609 20.4.3 format of type b reception mode figure 20-8 shows the data format for type b. figure 20-8. example of type b data format rin rin guide pulse data "1" data "0" 9 ms 4.5 ms data "1" data "0" data "0" data "0" data "0" data "0" 2.25 ms 1.125 ms 0.56 ms intdfull intgp intrin intrend rmer rmdh1l data "0" remark rin is the internally inverted signal of rin. 20.4.4 operation flow of type b reception mode figure 20-9 shows the operation flow. cautions 1. when intrerr is generated, rmsr and rmscr are automatically cleared immediately. 2. when data has been set to all the bits of rmsr, the following processing is automatically performed. ? the value of rmsr is transferred to rmdr. ? intdfull is generated. ? rmsr is cleared. rmdr must then be read before the next data is set to all the bits of rmsr. 3. when intrend has been generated, read rmscr first followed by rmsr. when rmsr has been read, rmscr and rmsr are automatically cleared. if intrend is generated, the next da ta cannot be received until rmsr is read. 4. rmsr, rmscr, and rmdr are cleared si multaneously to operation termination (rmen = 0). chapter 20 remote controller receiver user?s manual u18329ej4v0ud 610 figure 20-9. operation flow of type b reception mode longer than end interval? no yes start yes no generate intgp set data to all bits of rmsr ok? no guide pulse low level width ok? data low level width ok? generate intrend read rmscr process received data receive operation completed yes data high level width ok? set data to rmsr end no no yes yes yes generate intrerr no yes guide pulse high level width ok? no yes clear rmsr and rmscr clear rmsr, rmscr, and rmdr rmsr rmdr generate intdfull clear rmsr read rmsr clear rmsr and rmscr : software processing (user executes via program) : hardware processing (macro automatically performs) read rmdr note set compare registers operation enabled ( rmen = 1) terminate operation ( rmen = 0) note read rmdr before data has been set to all the bits of rmsr. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 611 20.4.5 format of type c reception mode figure 20-10 shows the data format for type c. figure 20-10. example of type c data format rmdh1l rmer 1.0 ms 2.0 ms rin rin intdfull intgp intrin intrend 0.263 ms data "1" data "0" data "1" data "0" data "0" data "0" data "0" data "0" data "0" remark rin is the internally inverted signal of rin. 20.4.6 operation flow of type c reception mode figure 20-11 shows the operation flow. cautions 1. when intrerr is generated, rmsr and rmscr are automatically cleared immediately. 2. when data has been set to all the bits of rmsr, the following processing is automatically performed. ? the value of rmsr is transferred to rmdr. ? intdfull is generated. ? rmsr is cleared. rmdr must then be read before the next data is set to all the bits of rmsr. 3. when intrend has been generated, read rmscr first followed by rmsr. when rmsr has been read, rmscr and rmsr are automatically cleared. if intrend is generated, the next da ta cannot be received until rmsr is read. 4. rmsr, rmscr, and rmdr are cleared si multaneously to operation termination (rmen = 0). 5. in type c reception mode, if the conditions for receiving a data low-/high-level width are not met before the first intdfull interrupt is generated, in trerr and intrend will not be generated. however, rmsr and rmscr will be cleared. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 612 figure 20-11. operation flow of type c reception mode operation enabled ( rmen = 1) longer than end interval? no start yes no set data to all bits of rmsr ok? no set compare registers data low level width ok? generate intrend read rmscr data high level width ok? set data to rmsr no no yes yes yes generate intrerr clear rmsr and rmscr read rmsr : software processing (user executes via program) : hardware processing (macro automatically performs) read rmdr note set data to all bits of rmsr ok? no data low level width ok? data high level width ok? set data to rmsr yes yes yes rmsr rmdr generate intdfull clear rmsr no no process received data receive operation completed yes terminate operation ( rmen = 0) end clear rmsr, rmscr, and rmdr clear rmsr and rmscr clear rmsr and rmscr note read rmdr before data has been set to all the bits of rmsr. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 613 20.4.7 timing operation varies depending on the positi ons of the rin input waveform below. (1) guide pulse high level width determinati on (type a, type b reception modes only) rin rmgphs rmgphl allowable range <1> <2> <3> rin rin , rin note note , rin note note , rin note note note rin is generated in type a reception mode, and rin is generated in type b reception mode. relationship between rmgphs/rmgphl/counter po sition of waveform corresponding operation counter < rmgphs <1>: short measuring guide pulse high-level width is started from the next rising edge. rmgphs counter < rmgphl <2>: within the range intgp is generated. data measurement is started. rmgphl counter <3>: long measuring guide pulse high-level width is started from the next rising edge. (2) guide pulse low level width determi nation (type b reception mode only) rin rmgpls rmgpll allowable range <1> <2> <3> rin rin relationship between rmgpls/rmgpll/counter po sition of waveform corresponding operation counter < rmgpls <1>: short measuring guide pulse high-level width is started from the next rising edge. rmgpls counter < rmgpll <2>: within the range intgp is generated. data measurement is started. rmgpll counter <3>: long measuring guide pulse high-level width is started from the next rising edge. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 614 (3) data low level width determination rin rmdls rmdll allowable range <1> <2> <3> rin rin , rin note note , rin note note , rin note note note rin is generated in type a reception mode, and ri n is generated in type b and type c reception modes. relationship between rmdls/rmdll/counter po sition of waveform corresponding operation counter < rmdls <1>: short error interrupt intrerr is generated note . measuring guide pulse high-level width is started. rmdls counter < rmdll <2>: within the range measuring data high-level width is started. rmdll counter <3>: long (type a reception mode) measuring the end width is started from the point. (type b, type c reception modes) error interrupt intrerr is generated at the point. note . note in type c reception mode, before the first intdfull interrupt is generated, intrerr will not be generated. however, rmsr and rmscr will be cleared. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 615 (4) data high level width determination rin rmdh0s rmdh0l allowable range <1> <2> <3> rin rin rmdh1s rmdh1l rin rin <5> <4> allowable range , rin note note , rin note note , rin note note , rin note note , rin note note note rin is generated in type a reception mode, and ri n is generated in type b and type c reception modes. relationship between rmdh0s/rmdh0l/rmdh1s/rmdh1l/counter position of waveform corresponding operation counter < rmdh0s <1>: short error interrupt intrerr is generated. measuring the guide pulse high-level width is started at the next rising edge. rmdh0s counter < rmdh0l <2>: within the range data 0 is received. measuring data low-level width is started. rmdh0l counter < rmdh1s <3>: outside of the range error interrupt intrerr is generated. measuring the guide pulse high-level width is started at the next rising edge. rmdh1s counter < rmdh1l <4>: within the range data 1 is received. measuring the data low-level width is started. rmdh1l counter <5>: long (type a reception mode) error interrupt intrerr is generated at the point. (type b, type c reception modes) measuring the end width is started from the point. measuring the guide pulse high-level width is started at the next rising edge. note in type c reception mode, before the first intdfull interrupt is generated, intrerr will not be generated. however, rmsr and rmscr will be cleared. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 616 (5) end width determination (a) type a reception mode rin rmdls rmdll <1> <2> rin rmer (b) type b, type c reception modes rin rmdh0l rmdh1l <1> <2> rin rmer relationship between rmer/counter positi on of waveform corresponding operation counter < rmer <1>: short error interrupt intrerr is generated note . measuring the guide pulse high-level width is started. rmer counter <2>: long intrend is generated at the point note . reception via circuit stops until rmsr is read. note in type c reception mode, before the first intd full interrupt is generated, intrerr and intrend will not be generated. however, rmsr and rmscr will be cleared. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 617 20.4.8 compare register setting this remote controller receiver has the following 11 types of compare registers. ? remote controller receive gpls compare register (rmgpls) ? remote controller receive gpll compare register (rmgpll) ? remote controller receive gphs compare register (rmgphs) ? remote controller receive gphl compare register (rmgphl) ? remote controller receive dls compare register (rmdls) ? remote controller receive dll compare register (rmdll) ? remote controller receive dh0s compare register (rmdh0s) ? remote controller receive dh0l compare register (rmdh0l) ? remote controller receive dh1s compare register (rmdh1s) ? remote controller receive dh1l compare register (rmdh1l) ? remote controller receive end width select register (rmer) use formulas (1) to (3) below to set the value of each compare register. making allowances for tolerance enables a normal reception operation, even if the rin i nput waveform is rin_1 or rin_2 shown in figure 20-12 due to the effect of noise. cautions 1. always set each compare register wh ile remote controller rece ption is disabled (rmen = 0). 2. set the set values so that they sat isfy all the following four conditions. ? rmgpls < rmgpll ? rmgphs < rmgphl ? rmdls < rmdll ? rmdh0s < rmdh0l rmdh1s < rmdh1l chapter 20 remote controller receiver user?s manual u18329ej4v0ud 618 figure 20-12. setting example (where n1 = 1, n2 = 2) rin rin_2 t w rin_1 clock rmgpls/rmgphs/rmdh0s/rmdh1s n1 n2 rmgpll/rmgphl/rmdh0l/rmdh1l rmdls rmdll t we rmer (1) formula for rmgpls, rmgphs, rmdls, rmdh0s, and rmdh1s ? 2 ? n1 (2) formula for rmgpll, rmgphl, rmdll, rmdh0l, and rmdh1l + 1 + n2 (3) formula for rmer ? 1 t w : width of rin input waveform 1/f remprs : width of internal oper ation clock cycle after division control by prsen a: tolerance (%) [ ] int : round down the fractional portion of the value produced by the formula in the brackets. n1, n2: variables of waveform change caused by noise note1 t we : end width of rin input note2 notes 1. set the values of n1 and n2 as required to meet the user s system specification. 2. this end width is counted after rmdll. the low-level width actually required after the last data has been received is as follows: (rmdll + 1 + rmer + 1) (width of internal operation cloc k cycle after division control by prsen) t w (1 ? a/100) 1/f remprs int t w (1 + a/100) 1/f remprs int t we (1 ? a/100) 1/f remprs int chapter 20 remote controller receiver user?s manual u18329ej4v0ud 619 20.4.9 error interrupt generation timing (1) type a reception mode after the guide pulse has been detected normally, the intrerr signal is generated under any of the following conditions. ? counter < rmdls at the rising edge of rin ? rmdll counter and counter after rmdll < rmer at the rising edge of rin ? counter < rmdh0s at the falling edge of rin ? rmdh0l counter < rmdh1s at the falling edge of rin ? register changes so that rmdh1l counter while rin is at high level the intrerr signal is not generated until the guide pulse is detected. once the intrerr signal has been generated, it will not be generated again until the next guide pulse is detected. the generation timing of the intrerr signal is shown in figure 20-13. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 620 figure 20-13. generation timing of in trerr signal (type a reception mode) rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr rin intrerr intrend rin intrerr rin intrerr example 1 counter < rmgphs intrerr is not generated. basic waveform example 2 rmgphl counter intrerr is not generated. example 3 counter < rmdls intrerr is generated. example 4 rmdll counter and counter < rmer intrerr is generated. example 5 rmdll counter and rmer counter intrerr is not generated. intrend is generated. example 6 counter < rmdh0s intrerr is generated. example 7 rmdh0l counter rmdh1s intrerr is generated. example 8 rmdh1l counter intrerr is generated. rmgphs rmgphl rmdls rmdll rmer rmdh1l rmdh0s rmdh1s rmdh0l chapter 20 remote controller receiver user?s manual u18329ej4v0ud 621 (2) type b reception mode after the guide pulse has been detected normally, the intrerr signal is generated under any of the following conditions. ? counter < rmdls at the rising edge of rin ? register changes so that rmdll counter while rin is at low level ? counter < rmdh0s at the falling edge of rin ? rmdh0l counter < rmdh1s at the falling edge of rin ? rmdh1l counter and counter after rmdh1l < rmer at the falling edge of rin the intrerr signal is not generated until the guide pulse is detected. once the intrerr signal has been generated, it will not be generated again until the next guide pulse is detected. the generation timing of the intrerr signal is shown in figure 20-14. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 622 figure 20-14. generation timing of in trerr signal (type b reception mode) intrerr rin intrerr intrerr intrerr intrerr rin intrerr rin intrerr intrerr example 3 counter < rmgphs intrerr is not generated. example 4 rmgphl counter intrerr is not generated. example 5 counter < rmdls intrerr is generated. example 6 rmdll counter intrerr is generated. rin intrerr intrend example 10 rmdll counter and rmer counter intrerr is not generated. intrend is generated. example 7 counter < rmdh0s intrerr is generated. example 8 rmdh0l counter < rmdh1s intrerr is generated. example 9 rmdh1l counter and counter < rmer intrerr is generated. intrerr intrerr example 1 counter < rmgpls intrerr is not generated. example 2 rmgpll counter intrerr is not generated. basic waveform rmgphs rmgpls rmgphl rmgpll rmdls rmdll rmer rmdh1l rmdh0s rmdh1s rmdh0l rin rin rin rin rin rin rin chapter 20 remote controller receiver user?s manual u18329ej4v0ud 623 (3) type c reception mode the intrerr signal is generated under any of the following conditions. ? counter < rmdls at the rising edge of rin ? register changes so that rmdll counter while rin is at low level ? counter < rmdh0s at the falling edge of rin ? rmdh0l counter < rmdh1s at the falling edge of rin ? rmdh1l counter and counter after rmdh1l < rmer at the falling edge of rin however, before the first intdfull interrupt is generated, intrerr signal will not be generated. the generation timing of the intrerr signal is shown in figure 20-15. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 624 figure 20-15. generation timing of in trerr signal (type c reception mode) intrerr intrerr rin intrerr rin intrerr intrerr example 1 counter < rmdls intrerr is not generated. example 2 rmdll counter intrerr is not generated. rin intrerr intrend example 6 rmdll counter and rmer counter intrerr is not generated. intrend is generated. example 3 counter < rmdh0s intrerr is generated. example 4 rmdh0l counter < rmdh1s intrerr is generated. example 5 rmdh1l counter and counter < rmer intrerr is generated. intrerr basic waveform rmdls rmdll rmer rmdh1l rmdh0s rmdh1s rmdh0l rin rin rin rin chapter 20 remote controller receiver user?s manual u18329ej4v0ud 625 20.4.10 noise elimination this remote controller receiver provides a function that supplies the signals input from the outside to the rin pin after eliminating noise. noise width can be eliminated by setting bit 5 (prsen) and bit 6 (ncw) of the remote controller receive control register (rmcn) as shown in figure 20-2. table 20-2. noise elimination width prsen division control signal ncw noise elimination width control signal internal operation clock cycle after division control by prsen (1/f remprs ) eliminatable noise width 0 0 1/f rem less than 1/f rem 0 1 1/f rem less than 2/f rem 1 0 2/f rem less than 2/f rem 1 1 2/f rem less than 4/f rem remark f rem : source clock of remote controller counter a noise elimination operation is performed by using the in ternal operation clock after division control by prsen. then, after the external input signal from rin pin has been synchronized with the clock, if ncw = 0, the signal after sampling is performed twice is processed as a rin input in the circuit. if ncw = 1, the signal after sampling is performed thr ee times is processed as a rin input in the circuit. the following shows the flow of a noise elimination operation. <1> select whether or not the internal operation clock is divided by prsen. prsen = 0: not divided (f remprs = f rem ) prsen = 1: divided (f remprs = f rem /2) <2> synchronize the external input signal from the rin pin with the internal operation clock. <3> generate a signal (samp1) sampling the synchronized signal for the first time. (the signal is later than the synchronized signal by one clock.) <4> generate a signal (samp2) sampling the synch ronized signal and samp1 for the second time. (when synchronized signal = samp1 = h, samp1 is latched.) <5> generate a signal (samp3) sampling the synch ronized signal and samp2 for the third time. (when synchronized signal = samp2 = h, samp2 is latched.) <6> select a signal to be the rin input in the circuit using ncw. ncw = 0: samp2 is processed as the rin input in the circuit. ncw = 1: samp3 is processed as the rin input in the circuit. figure 20-16 shows an example of a noise elimination operation. chapter 20 remote controller receiver user?s manual u18329ej4v0ud 626 figure 20-16. noise elimination operation example (1/2) (a) 1-clock noise elimination (prsen = 0, ncw = 0) remark internal rin is a signal after synchronization and sampling are performed twice, and is therefore later than the actual signal input from the outside to the rin pin by two to three clocks. (b) 2-clock noise elimination (prsen = 0, ncw = 1) remark internal rin is a signal after synchronization and sampling are performed three times, and is therefore later than the actual signal input from t he outside to the rin pin by 3 to 4 clocks. clock clock rin (ideal) rin synchronization samp2 samp3 internal rin noise delayed by 3 to 4 clocks samp1 h h l h l l l since synchronized signal = samp1 = h, samp1 is latched from this point and later. since synchronized signal = samp2 = h is not satisfied, samp2 is not latched. clock rin (ideal) rin synchronization samp1 samp2 internal rin noise delayed by 2 to 3 clocks l h l l since synchronized signal = samp1 = h is not satisfied, samp1 is not latched. l chapter 20 remote controller receiver user?s manual u18329ej4v0ud 627 figure 20-16. noise elimination operation example (2/2) (c) 2-clock noise elimination (prsen = 1, ncw = 0) remark internal rin is a signal after synchronization and sampling are performed twice, and is therefore later than the actual signal input from the out side to the rin pin by 4 to 6 clocks. (d) 4-clock noise elimination (prsen = 1, ncw = 1) remark internal rin is a signal after synchronization and sampling are performed three times, and is therefore later than the actual signal input from t he outside to the rin pin by 6 to 8 clocks. clock divider rin (ideal) rin synchronization samp2 samp3 internal rin noise delayed by 6 to 8 clocks samp1 clock h h l h l l since synchronized signal = samp2 = h is not satisfied, samp2 is not latched. since synchronized signal = samp1 = h, samp1 is latched. l clock divider rin (ideal) rin synchronization samp2 internal rin noise delayed by 4 to 6 clocks samp1 clock l h l l since synchronized signal = samp1 = h is not satisfied, samp1 is not latched. l user?s manual u18329ej4v0ud 628 chapter 21 interrupt functions 21.1 interrupt function types the following two types of inte rrupt functions are used. (1) maskable interrupts these interrupts undergo mask control. maskable interrup ts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (pr0l, pr0h, pr1l, pr1h). multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. if two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored in terrupt servicing. for the priority order, see table 21-1 . a standby release signal is generated a nd stop and halt modes are released. external interrupt requests and internal interrupt requests are provided as maskable interrupts. ? pd78f047x external: 7, internal: 20 ? pd78f048x external: 7, internal: 21 ? pd78f049x external: 7, internal: 22 (2) software interrupt this is a vectored interrupt generated by executing the brk instruction. it is acknowledged even when interrupts are disabled. the software interrupt does not undergo interrupt priority control. 21.2 interrupt sources and configuration the pd78f047x has a total of 28 interrupt sources, the pd78f048x has a total of 29 interrupt sources, and the pd78f049x has a total of 30 interrupt sources, including maskable interrupts and software interrupts. in addition, they also have up to four reset sources (see table 21-1 ). chapter 21 interrupt functions user?s manual u18329ej4v0ud 629 table 21-1. interrupt source list (1/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 0 intlvi low-voltage detection note 3 internal 0004h (a) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 pin input edge detection external 0010h (b) 7 intsre6 uart6 reception error generation 0012h 8 intsr6 end of uart6 reception 0014h 9 intst6 end of uart6 transmission 0016h 10 intcsi10/ intst0 end of csi10 communication/end of uart0 transmission 0018h 11 inttmh1 match between tmh1 and cmp01 (when compare register is specified) 001ah 12 inttmh0 match between tmh0 and cmp00 (when compare register is specified) 001ch 13 inttm50 match between tm50 and cr50 (when compare register is specified) 001eh 14 inttm000 match between tm00 and cr000 (when compare register is specified), ti010 pin valid edge detection (when capture register is specified) 0020h 15 inttm010 match between tm00 and cr010 (when compare register is specified), ti000 pin valid edge detection (when capture register is specified) 0022h 16 intad note 5 end of 10-bit successive approximation type a/d conversion 0024h 17 intsr0 end of uart0 reception or reception error generation 0026h 18 intrtc fixed-cycle sign al of real-time counter/alarm match detection 0028h 19 inttm51 note 4 match between tm51 and cr51 (when compare register is specified) internal 002ah (a) 20 intkr key interrupt detection external 002ch (c) maskable 21 intrtci interval signal detection of real-time counter internal 002eh (a) notes 1. the default priority determines t he sequence of processing vectored in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the hi ghest priority and 28 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 21-1. 3. when bit 1 (lvimd) of the low-voltage det ection register (lvim) is cleared to 0. 4. when 8-bit timer/event counter 51 and 8-bit timer h1 are used in the carrier generator mode, an interrupt is generated upon the timing wh en the inttm5h1 signal is generated (see figure 8-15 transfer timing ). 5. pd78f048x and 78f049x only. chapter 21 interrupt functions user?s manual u18329ej4v0ud 630 table 21-1. interrupt source list (2/2) interrupt source interrupt type default priority note 1 name trigger internal/ external vector table address basic configuration type note 2 22 intdsad note 4 end of 16-bit ? type a/d conversion 0030h 23 inttm52 match between tm52 and cr52 (when compare register is specified) 0032h 24 inttmh2 match between tmh2 and crh2 (when compare register is specified) 0034h 25 intmcg end of manchester code reception 0036h 26 intrin remote controller reception edge detection 0038h 27 intrerr/ intgp/ intrend/ intdfull remote controller reception error occurrence remote controller guide pulse detection remote controller data reception completion read request for remote controller 8-bit shift data 003ah maskable 28 intacsi end of csia0 communication internal 003ch (a) software ? brk brk instruction execution ? 003eh (d) reset reset input poc power-on clear lvi low-voltage detection note 3 reset ? wdt wdt overflow ? 0000h ? notes 1. the default priority determines t he sequence of processing vectored in terrupts if two or more maskable interrupts occur simultaneously. zero indicates the hi ghest priority and 28 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 21-1. 3. when bit 1 (lvimd) of the low-voltage detection register (lvim) is set to 1. 4. pd78f049x only. chapter 21 interrupt functions user?s manual u18329ej4v0ud 631 figure 21-1. basic configurati on of interrupt function (1/2) (a) internal maskable interrupt internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal (b) external maskable inte rrupt (intp0 to intp5) internal bus interrupt request if mk ie pr isp priority controller vector table address generator standby release signal external interrupt edge enable register (egp, egn) edge detector if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag chapter 21 interrupt functions user?s manual u18329ej4v0ud 632 figure 21-1. basic configurati on of interrupt function (2/2) (c) external maskable interrupt (intkr) if mk ie pr isp internal bus interrupt request priority controller vector table address generator standby release signal key interrupt detector 1 when krmn = 1 (n = 0 to 7) (d) software interrupt internal bus interrupt request priority controller vector table address generator if: interrupt request flag ie: interrupt enable flag isp: in-service priority flag mk: interrupt mask flag pr: priority specification flag krm: key return mode register chapter 21 interrupt functions user?s manual u18329ej4v0ud 633 21.3 registers controlling interrupt functions the following 6 types of registers are used to control the interrupt functions. ? interrupt request flag regist er (if0l, if0h, if1l, if1h) ? interrupt mask flag register (mk0l, mk0h, mk1l, mk1h) ? priority specification flag register (pr0l, pr0h, pr1l, pr1h) ? external interrupt rising edge enable register (egp) ? external interrupt falling edge enable register (egn) ? program status word (psw) table 21-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. table 21-2. flags corresponding to interrupt request sources (1/2) interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intlvi lviif if0l lvimk mk0l lvipr pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intsre6 sreif6 sremk6 srepr6 intsr6 srif6 if0h srmk6 mk0h srpr6 pr0h intst6 stif6 stmk6 stpr6 intcsi10 intst0 csiif10 note 1 stif0 note 1 csimk10 note 2 stmk0 note 2 csipr10 note 3 stpr0 note 3 inttmh1 tmifh1 tmmkh1 tmprh1 inttmh0 tmifh0 tmmkh0 tmprh0 inttm50 tmif50 tmmk50 tmpr50 inttm000 tmif000 tmmk000 tmpr000 inttm010 tmif010 tmmk010 tmpr010 notes 1. if either interrupt source intcsi10 or ints t0 is generated, bit 2 of if0h is set (1). 2. bit 2 of mk0h supports both interrupt sources intcsi10 and intst0. 3. bit 2 of pr0h supports both interrupt sources intcsi10 and intst0. chapter 21 interrupt functions user?s manual u18329ej4v0ud 634 table 21-2. flags corresponding to interrupt request sources (2/2) interrupt request flag interrupt mask flag priority specification flag interrupt source register register register intad note 1 adif note 1 if1l admk note 1 mk1l adpr note 1 pr1l intsr0 srif0 srmk0 srpr0 intrtc rtcif rtcmk rtcpr inttm51 note 2 tmif51 tmmk51 tmpr51 intkr krif krmk krpr intrtci rtciif rtcimk rtcipr intdsad note 3 dsadif note 3 dsadmk note 3 dasdpr note 3 inttm52 tmif52 tmmk52 tmpr52 inttmh2 tmhif2 tmhmk2 tmhpr2 intmcg mcgif if1h mcgmk mk1h mcgpr pr1h intrin rinif rinmk rinpr intrerr intgp intrend intdfull rerrif note 4 gpif note 4 rendif note 4 dfullif note 4 rerrmk note 5 gpmk note 5 rendmk note 5 dfullmk note 5 rerrpr note 6 gppr note 6 rendpr note 6 dfullpr note 6 intacsi acsiif acsimk acsipr notes 1. pd78f048x and 78f049x only. 2. when 8-bit timer/event counter 51 and 8-bit timer h1 are used in the carrier gen erator mode, an interrupt is generated upon the timing when the inttm5h1 signal is generated (see figure 8-15 transfer timing ). 3. pd78f049x only. 4. if either interrupt source intrerr, intgp, intrend, or intdfull is generated, bit 3 of if1h is set (1). 5. bit 3 of mk1h supports all of interrupt s ources intrerr, intgp, intrend, and intdfull. 6. bit 3 of pr1h supports all of interrupt s ources intrerr, intgp, intrend, and intdfull. chapter 21 interrupt functions user?s manual u18329ej4v0ud 635 (1) interrupt request flag regist ers (if0l, if0h, if1l, if1h) the interrupt request flags are set to 1 when the correspo nding interrupt request is g enerated or an instruction is executed. they are cleared to 0 when an instruction is executed upon acknow ledgment of an interrupt request or upon reset signal generation. when an interrupt is acknowledged, the interrupt req uest flag is automatically cleared and then the interrupt routine is entered. if0l, if0h, if1l, and if1h are set by a 1-bit or 8-bit memory manipulation instruct ion. when if0l and if0h, and if1l and if1h are combined to form 16-bit registers if0 and if1, they are set by a 16-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 21-2. format of interrupt request fl ag registers (if0l, if0h, if1l, if1h) address: ffe0h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0l sreif6 pif5 pif4 pif3 pif2 pif1 pif0 lviif address: ffe1h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if0h tmif010 tmif000 tmif50 tmifh0 tmifh1 csiif10 stif0 stif6 srif6 address: ffe2h after reset: 00h r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> if1l tmif52 dsadif note 2 rtciif krif tmif51 rtcif srif0 adif note 1 address: ffe3h after reset: 00h r/w symbol 7 6 5 <4> <3> <2> <1> <0> if1h 0 0 0 acsiif rerrif gpif renif dfullif rinif mcgif tmhif2 xxifx interrupt request flag 0 no interrupt request signal is generated 1 interrupt request is generated, interrupt request status notes 1. pd78f048x and 78f049x only. 2. pd78f049x only. cautions 1. be sure to clear bits 5 to 7 of if1h to 0. 2. when operating a timer, se rial interface, or a/d converter after standby release, operate it once after clearing the interrupt request flag. an interrupt request flag may be set by noise. chapter 21 interrupt functions user?s manual u18329ej4v0ud 636 cautions 3. when manipulating a flag of the in terrupt request flag regi ster, use a 1-bit memory manipulation instruction (clr1). when descr ibing in c language, use a bit manipulation instruction such as ?if0l.0 = 0;? or ?_asm(?clr1 if0l, 0?);? because the co mpiled assembler must be a 1-bit memory manipulation instruction (clr1). if a program is described in c language usi ng an 8-bit memory manipulation instruction such as ?if0l &= 0xfe;? and compiled, it becom es the assembler of three instructions. mov a, if0l and a, #0feh mov if0l, a in this case, even if the request flag of another bit of the same interrupt request flag register (if0l) is set to 1 at the timing between ?mov a, if0l? and ?mov if 0l, a?, the flag is cleared to 0 at ?mov if0l, a?. therefore, care must be exercised when us ing an 8-bit memory manipulation instruction in c language. chapter 21 interrupt functions user?s manual u18329ej4v0ud 637 (2) interrupt mask flag regist ers (mk0l, mk0h, mk1l, mk1h) the interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. mk0l, mk0h, mk1l, and mk1h are set by a 1-bit or 8- bit memory manipulation instruction. when mk0l and mk0h, and mk1l and mk1h are combined to form 16-bit registers mk0 and mk1, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 21-3. format of interrupt mask fl ag registers (mk0l, mk0h, mk1l, mk1h) address: ffe4h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0l sremk6 pmk5 pmk4 pmk3 pmk2 pmk1 pmk0 lvimk address: ffe5h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk0h tmmk010 tmmk000 tmmk50 tmmkh0 tmmkh1 csimk10 stmk0 stmk6 srmk6 address: ffe6h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> mk1l tmmk52 dasdmk note 2 rtcimk krmk tmmk51 rtcmk srmk0 admk note 1 address: ffe7h after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> mk1h 1 1 1 acsimk rerrmk gpmk rendmk dfullmk rinmk mcgmk tmhmk2 xxmkx interrupt servicing control 0 interrupt servicing enabled 1 interrupt servicing disabled notes 1. pd78f048x and 78f049x only. 2. pd78f049x only. caution be sure to set bits 5 to 7 of mk1h to 1. chapter 21 interrupt functions user?s manual u18329ej4v0ud 638 (3) priority specification flag re gisters (pr0l, pr0h, pr1l, pr1h) the priority specification flag regist ers are used to set the corresponding maskable interrupt priority order. pr0l, pr0h, pr1l, and pr1h are set by a 1-bit or 8-bi t memory manipulation instruction. if pr0l and pr0h, and pr1l and pr1h are combined to form 16-bit registers pr0 and pr1, they are set by a 16-bit memory manipulation instruction. reset signal generation sets these registers to ffh. figure 21-4. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) address: ffe8h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0l srepr6 ppr5 ppr4 ppr3 ppr2 ppr1 ppr0 lvipr address: ffe9h after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr0h tmpr010 tmpr000 tmpr50 tmprh0 tmprh1 csipr10 stpr0 stpr6 srpr6 address: ffeah after reset: ffh r/w symbol <7> <6> <5> <4> <3> <2> <1> <0> pr1l tmpr52 dsadpr note 2 rtcipr krpr tmpr51 rtcpr srpr0 adpr note 1 address: ffebh after reset: ffh r/w symbol 7 6 5 <4> <3> <2> <1> <0> pr1h 1 1 1 acsipr rerrpr gppr rendpr dfullpr rinpr mcgpr tmhpr2 xxprx priority level selection 0 high priority level 1 low priority level notes 1. pd78f048x and 78f049x only. 2. pd78f049x only. caution be sure to set bits 5 to 7 of pr1h to 1. chapter 21 interrupt functions user?s manual u18329ej4v0ud 639 (4) external interrupt rising edge en able register (egp), external interrupt falling edge enable register (egn) these registers specify the valid edge for intp0 to intp5. egp and egn are set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears these registers to 00h. figure 21-5. format of external interrupt rising edge enable register (egp) and external interrupt falling edge enable register (egn) address: ff48h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egp 0 0 egp5 egp4 egp3 egp2 egp1 egp0 address: ff49h after reset: 00h r/w symbol 7 6 5 4 3 2 1 0 egn 0 0 egn5 egn4 egn3 egn2 egn1 egn0 egpn egnn intpn pin valid edge selection (n = 0 to 5) 0 0 edge detection disabled 0 1 falling edge 1 0 rising edge 1 1 both rising and falling edges table 21-3 shows the ports corresponding to egpn and egnn. table 21-3. ports correspo nding to egpn and egnn detection enable register edge detection port interrupt request signal egp0 egn0 p120/exlvi intp0 egp1 egn1 p34/ti52/ti010/to00/rtc1hz intp1 egp2 egn2 p33/ti000/rtcdiv/rtccl/buz intp2 egp3 egn3 p31/toh1 intp3 egp4 egn4 p14/scka0 intp4 egp5 egn5 p30 intp5 caution select the port mode by clearing eg pn and egnn to 0 because an edge may be detected when the external interrupt func tion is switched to the port function. remark n = 0 to 5 chapter 21 interrupt functions user?s manual u18329ej4v0ud 640 (5) program status word (psw) the program status word is a register used to hold the instruction exec ution result and the current status for an interrupt request. the ie flag that sets maskable interr upt enable/disable and the isp fl ag that controls multiple interrupt servicing are mapped to the psw. besides 8-bit read/write, this register can carry out op erations using bit manipulation instructions and dedicated instructions (ei and di). when a vect ored interrupt request is acknowledged, if the brk instruction is executed, the contents of the psw are aut omatically saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged, the contents of the priority specification flag of t he acknowledged interrupt are transferred to the isp flag. the psw contents are also saved into the stack with t he push psw instruction. they are restored from the stack with the reti, retb, and pop psw instructions. reset signal generation sets psw to 02h. figure 21-6. format of program status word <7> ie <6> z <5> rbs1 <4> ac <3> rbs0 2 0 <1> isp 0 cy psw after reset 02h isp high-priority interrupt servicing (low-priority interrupt disabled) ie 0 1 disabled priority of interrupt currently being serviced interrupt request acknowledgment enable/disable used when normal instruction is executed enabled interrupt request not acknowledged, or low- priority interrupt servicing (all maskable interrupts enabled) 0 1 chapter 21 interrupt functions user?s manual u18329ej4v0ud 641 21.4 interrupt servicing operations 21.4.1 maskable interrupt acknowledgment a maskable interrupt becomes acknowledgeable when the in terrupt request flag is set to 1 and the mask (mk) flag corresponding to that interrupt request is cleared to 0. a vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the ie flag is set to 1). however, a low-priority interrupt request is not acknowledged during servicing of a higher priority in terrupt request (when the isp flag is reset to 0). the times from generation of a maskable interrupt request until vectored interr upt servicing is performed are listed in table 21-4 below. for the interrupt request acknowledgment timing, see figures 21-8 and 21-9 . table 21-4. time from generation of maskable inte rrupt until servicing minimum time maximum time note when pr = 0 7 clocks 32 clocks when pr = 1 8 clocks 33 clocks note if an interrupt request is generated just before a di vide instruction, the wait time becomes longer. remark 1 clock: 1/f cpu (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledge d first. if two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. an interrupt request that is held pending is a cknowledged when it becomes acknowledgeable. figure 21-7 shows the interrupt request acknowledgment algorithm. if a maskable interrupt request is acknowledged, the content s are saved into the stacks in the order of psw, then pc, the ie flag is reset (0), and the contents of the pr iority specification flag corresponding to the acknowledged interrupt are transferred to the isp flag. the vector table data deter mined for each interrupt request is the loaded into the pc and branched. restoring from an interrupt is possible by using the reti instruction. chapter 21 interrupt functions user?s manual u18329ej4v0ud 642 figure 21-7. interrupt request acknowledgment processing algorithm start if = 1? mk = 0? pr = 0? ie = 1? isp = 1? interrupt request held pending yes yes no no yes (interrupt request generation) yes no (low priority) no no yes yes no ie = 1? no any high-priority interrupt request among those simultaneously generated with pr = 0? yes (high priority) no yes yes no vectored interrupt servicing interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending interrupt request held pending vectored interrupt servicing any high-priority interrupt request among those simultaneously generated? any high-priority interrupt request among those simultaneously generated with pr = 0? if: interrupt request flag mk: interrupt mask flag pr: priority specification flag ie: flag that controls acknowledgment of mask able interrupt request (1 = enable, 0 = disable) isp: flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt servicing, 1 = no interrupt request acknowledg ed, or low-priority interrupt servicing) chapter 21 interrupt functions user?s manual u18329ej4v0ud 643 figure 21-8. interrupt request ac knowledgment timing (minimum time) 8 clocks 7 clocks instruction instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) figure 21-9. interrupt request ac knowledgment timing (maximum time) 33 clocks 32 clocks instruction divide instruction psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if ( pr = 1) if ( pr = 0) 6 clocks 25 clocks remark 1 clock: 1/f cpu (f cpu : cpu clock) 21.4.2 software interrupt request acknowledgment a software interrupt acknowledge is acknowledged by brk instruction execution. so ftware interrupts cannot be disabled. if a software interrupt request is ackno wledged, the cont ents are saved into the stacks in the order of the program status word (psw), then program counter (pc), the ie flag is reset (0), and t he contents of the ve ctor table (003eh, 003fh) are loaded into the pc and branched. restoring from a software interrupt is possi ble by using the retb instruction. caution do not use the reti instruction fo r restoring from the software interrupt. chapter 21 interrupt functions user?s manual u18329ej4v0ud 644 21.4.3 multiple interrupt servicing multiple interrupt servicing occurs when another interrupt re quest is acknowledged during execution of an interrupt. multiple interrupt servicing does not occur unless the inte rrupt request acknowledgment enabled state is selected (ie = 1). when an interrupt request is acknowledged, inte rrupt request acknowledgment becomes disabled (ie = 0). therefore, to enable multiple interrupt servicing, it is necessary to set (1) the ie flag with the ei instruction during interrupt servicing to enable interrupt acknowledgment. moreover, even if interrupts are enabled, multiple interr upt servicing may not be enabled, this being subject to interrupt priority control. two types of priority control are available: default priority control and programmable priority control. programmable priority control is used for multiple interrupt servicing. in the interrupt enabled state, if an in terrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for mu ltiple interrupt servicing. if an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. inte rrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower prio rity are held pending. when servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. table 21-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and figure 21-10 shows multiple interrupt servicing examples. table 21-5. relationship between interrupt requests enabled for multiple interrupt servicing during interrupt servicing maskable interrupt request pr = 0 pr = 1 multiple interrupt request interrupt being serviced ie = 1 ie = 0 ie = 1 ie = 0 software interrupt request isp = 0 { { maskable interrupt isp = 1 { { { software interrupt { { { remarks 1. : multiple interrupt servicing enabled 2. : multiple interrupt servicing disabled 3. isp and ie are flags contained in the psw. isp = 0: an interrupt with higher priority is being serviced. isp = 1: no interrupt request has been acknowledged, or an interrupt with a lower priority is being serviced. ie = 0: interrupt request acknowledgment is disabled. ie = 1: interrupt request acknowledgment is enabled. 4. pr is a flag contained in pr0l, pr0h, pr1l, and pr1h. pr = 0: higher priority level pr = 1: lower priority level chapter 21 interrupt functions user?s manual u18329ej4v0ud 645 figure 21-10. examples of multip le interrupt se rvicing (1/2) example 1. multiple inte rrupt servicing occurs twice main processing intxx servicing intyy servicing intzz servicing ei ei ei reti reti reti intxx (pr = 1) intyy (pr = 0) intzz (pr = 0) ie = 0 ie = 0 ie = 0 ie = 1 ie = 1 ie = 1 during servicing of interrupt intxx, two interrupt re quests, intyy and intzz, are acknowledged, and multiple interrupt servicing takes place. before each interrupt re quest is acknowledged, the ei instruction must always be issued to enable interrupt request acknowledgment. example 2. multiple interrupt servicing does not occur due to priority control main processing intxx servicing intyy servicing intxx (pr = 0) intyy (pr = 1) ei reti ie = 0 ie = 0 ei 1 instruction execution reti ie = 1 ie = 1 interrupt request intyy issued during servicing of interrupt intxx is not acknowledged because its priority is lower than that of intxx, and mu ltiple interrupt servicing does not take place. the intyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. pr = 0: higher priority level pr = 1: lower priority level ie = 0: interrupt request acknowledgment disabled chapter 21 interrupt functions user?s manual u18329ej4v0ud 646 figure 21-10. examples of multip le interrupt se rvicing (2/2) example 3. multiple interrupt servicing do es not occur because inte rrupts are not enabled main processing intxx servicing intyy servicing ei 1 instruction execution reti reti intxx (pr = 0) intyy (pr = 0) ie = 0 ie = 0 ie = 1 ie = 1 interrupts are not enabled during servicing of interrupt int xx (ei instruction is not issued), therefore, interrupt request intyy is not acknowledged and multiple interrupt serv icing does not take place. the intyy interrupt request is held pending, and is acknowledged following ex ecution of one main processing instruction. pr = 0: higher priority level ie = 0: interrupt request acknowledgment disabled chapter 21 interrupt functions user?s manual u18329ej4v0ud 647 21.4.4 interrupt request hold there are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the ne xt instruction. these instructions (interrupt request hol d instructions) are listed below. ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw. bit, cy ? mov1 cy, psw. bit ? and1 cy, psw. bit ? or1 cy, psw. bit ? xor1 cy, psw. bit ? set1 psw. bit ? clr1 psw. bit ? retb ? reti ? push psw ? pop psw ? bt psw. bit, $addr16 ? bf psw. bit, $addr16 ? btclr psw. bit, $addr16 ? ei ? di ? manipulation instructions for the if0l, if0h, if1l, if1h, mk0l, mk0h, mk1l, mk1h, pr0l, pr0h, pr1l, and pr1h registers. caution the brk instruction is not one of the above-listed interrupt re quest hold instructions. however, the software interrupt activated by executing the brk instruction causes the ie flag to be cleared. therefore, even if a maskable interrupt re quest is generated during execution of the brk instruction, the interrupt re quest is not acknowledged. figure 21-11 shows the timing at which interrupt requests are held pending. figure 21-11. interrupt request hold instruction n instruction m psw and pc saved, jump to interrupt servicing interrupt servicing program cpu processing if remarks 1. instruction n: interrupt request hold instruction 2. instruction m: instruction other t han interrupt request hold instruction 3. the pr (priority level) values do not affect the operation of if (interrupt request). user?s manual u18329ej4v0ud 648 chapter 22 key interrupt function 22.1 functions of key interrupt a key interrupt (intkr) can be generated by setting t he key return mode register (krm) and inputting a falling edge to the key interrupt input pins (kr0 to kr7). table 22-1. assignment of k ey interrupt detection pins flag description krm0 controls kr0 signal in 1-bit units. krm1 controls kr1 signal in 1-bit units. krm2 controls kr2 signal in 1-bit units. krm3 controls kr3 signal in 1-bit units. krm4 controls kr4 signal in 1-bit units. krm5 controls kr5 signal in 1-bit units. krm6 controls kr6 signal in 1-bit units. krm7 controls kr7 signal in 1-bit units. 22.2 configuration of key interrupt the key interrupt includes the following hardware. table 22-2. configuration of key interrupt item configuration control register key return mode register (krm) figure 22-1. block diag ram of key interrupt intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0 chapter 22 key interrupt function user?s manual u18329ej4v0ud 649 22.3 register controlling key interrupt (1) key return mode register (krm) this register is used to set whether to detect a key inte rrupt (intkr) when a falling edge of the key interrupt input pins (kr0 to kr7) is generated. krm is set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation clears krm to 00h. figure 22-2. format of key return mode register (krm) krm7 does not detect key interrupt signal detects key interrupt signal krmn 0 1 key interrupt mode control (n = 0-7) krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 address: ff6eh after reset: 00h r/w symbol 765432 0 cautions 1. when setting the krmn bit to 1 in order to u se the key interrupt function, set the pu4n bit of the corresponding pull-up resistor option register 4 (pu4) to 1. 2. if krm is changed, the interrupt request flag may be set. therefore, disable interrupts and then change the krm register. clear the in terrupt request flag and enable interrupts. 3. if detection of key interrupt signals is disabled (krmn = 0), the corresponding p4n pin can be used as a normal port. 4. to use the p40/kr0/v lc3 pin for the key interrupt function (kr0), use the lcd display mode register (lcdm) to set it other than to the 1/4 bias method. if the p40/kr0/v lc3 pin is set to the 1/4 bias method, it will function as v lc3 . 5. when using the krn pin as a segment key scan input pin wh ile using the segment key scan function (kson = 1), set krmn to 1. when not using the krn pi n as a segment key scan input pin, set krmn to 0 (see figure 18-7). user?s manual u18329ej4v0ud 650 chapter 23 standby function 23.1 standby function and configuration 23.1.1 standby function the standby function is designed to reduce the operating current of the system. the following two modes are available. (1) halt mode halt instruction execution se ts the halt mode. in the halt mode, the cpu operation clock is stopped. if the high-speed system clock oscillator, in ternal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the halt mode is set, oscillation of each clock continues. in this mode, the operating current is not decreased as much as in the st op mode, but the halt mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the high-speed system clock oscillator and internal high-speed oscillator stop, stopping the whole system, thereby considerably reducing the cpu operating current. because this mode can be cleared by an interrupt reques t, it enables intermittent operations to be carried out. however, because a wait time is required to secure th e oscillation stabilization time after the stop mode is released when the x1 clock is selected, select the halt mode if it is necessary to start processing immediately upon interrupt request generation. in either of these two modes, all the contents of registers, flags and data me mory just before the standby mode is set are held. the i/o port output latches an d output buffer statuses are also held. cautions 1. the stop mode can be used only when the cpu is operating on the main system clock. the subsystem clock oscillation cannot be stopped. the halt mode can be used when the cpu is operating on either the main syst em clock or the subsystem clock. 2. when shifting to the stop mode, be su re to stop the peripher al hardware operation operating with main system clock be fore executing stop instruction. 3. the following sequence is recommended for operating current reduction of the 10-bit successive approximation type a/d converter when the standby function is used: first clear bit 7 (adcs) and bit 0 (adce) of the a/d converte r mode register (adm) to 0 to stop the a/d conversion operation, and then execute the stop instruction. the following sequence is recommended fo r operating current reduction of the 16-bit ? type a/d converter when the standby function is used: first clear bit 7 (addpon) and bit 6 (addce) of the 16-bit ? type a/d converter mode register (addctl0) to 0 to stop the a/d conversion operation, and then execute the stop instruction. chapter 23 standby function user?s manual u18329ej4v0ud 651 23.1.2 registers controlling standby function the standby function is controlled by the following two registers. ? oscillation stabilization time c ounter status register (ostc) ? oscillation stabilization time select register (osts) remark for the registers that start, st op, or select the clock, see chapter 5 clock generator . (1) oscillation stabilization time counter status register (ostc) this is the register that indicates t he count status of the x1 clock oscillati on stabilization time counter. when x1 clock oscillation starts with the intern al high-speed oscillation clock or su bsystem clock used as the cpu clock, the x1 clock oscillation stabilization time can be checked. ostc can be read by a 1-bit or 8-bit memory manipulation instruction. when reset is released (reset by reset input, poc, lvi, and wdt), the stop instruction and mstop (bit 7 of moc register) = 1 clear ostc to 00h. figure 23-1. format of oscillation stabilizati on time counter status register (ostc) address: ffa3h after reset: 00h r symbol 7 6 5 4 3 2 1 0 ostc 0 0 0 most11 most 13 most14 most15 most16 most11 most13 most14 most15 most16 oscillation stabilization time status f x = 10 mhz 1 0 0 0 0 2 11 /f x min. 204.8 s min. 1 1 0 0 0 2 13 /f x min. 819.2 s min. 1 1 1 0 0 2 14 /f x min. 1.64 ms min. 1 1 1 1 0 2 15 /f x min. 3.27 ms min. 1 1 1 1 1 2 16 /f x min. 6.55 ms min. cautions 1. after the above time has elapsed, the bits are set to 1 in order from most11 and remain 1. 2. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 3. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 23 standby function user?s manual u18329ej4v0ud 652 (2) oscillation stabilization time select register (osts) this register is used to select the x1 clock oscillation stabilization wait time when the stop mode is released. when the x1 clock is selected as the cpu clock, the operation waits for the time set using osts after the stop mode is released. when the internal high-speed oscillation clock is selected as the cpu clock, confirm with ostc that the desired oscillation stabilization time has elaps ed after the stop mode is released. the oscillation stabilization time can be checked up to the time set using ostc. osts can be set by an 8-bit memory manipulation instruction. reset signal generation sets osts to 05h. figure 23-2. format of oscillation stabiliz ation time select register (osts) address: ffa4h after reset: 05h r/w symbol 7 6 5 4 3 2 1 0 osts 0 0 0 0 0 osts2 osts1 osts0 osts2 osts1 osts0 oscillation stabilization time selection f x = 10 mhz 0 0 1 2 11 /f x 204.8 s 0 1 0 2 13 /f x 819.2 s 0 1 1 2 14 /f x 1.64 ms 1 0 0 2 15 /f x 3.27 ms 1 0 1 2 16 /f x 6.55 ms other than above setting prohibited cautions 1. to set the stop mode when the x1 clock is used as the cpu clock, set osts before executing the stop instruction. 2. do not change the value of the osts register during the x1 clock oscillation stabilization time. 3. the oscillation stabilization time counter counts up to the oscillation stabilization time set by osts. if the st op mode is entered and then released while the internal high-speed oscillation clock is being used as the cpu clock, set the oscillation stabilization time as follows. ? desired ostc oscillation stabilization time oscillation stabilization time set by osts note, therefore, that only the status up to the oscillation stabilization time set by osts is set to ostc afte r stop mode is released. 4. the x1 clock oscillation stabilization wa it time does not include the time until clock oscillation starts (?a? below). stop mode release x1 pin voltage waveform a remark f x : x1 clock oscillation frequency chapter 23 standby function user?s manual u18329ej4v0ud 653 23.2 standby function operation 23.2.1 halt mode (1) halt mode the halt mode is set by executing t he halt instruction. halt mode can be set regardless of whether the cpu clock before the setting was the high-spe ed system clock, internal high-spee d oscillation clock, or subsystem clock. the operating statuses in t he halt mode are shown below. chapter 23 standby function user?s manual u18329ej4v0ud 654 table 23-1. operating statuses in halt mode (1/2) when halt instruction is executed while cpu is operating on main system clock halt mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh operation continues (cannot be stopped) status before halt mode was set is retained f x status before halt mode was set is retained operation continues (cannot be stopped) status before halt mode was set is retained main system clock f exclk operates or stops by external cl ock input operation continues (cannot be stopped) subsystem clock f xt status before halt mode was set is retained f rl status before halt mode was set is retained cpu operation stopped flash memory operation stopped ram status before halt mode was set is retained port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 50 51 8-bit timer/event counter 52 h0 h1 8-bit timer h2 real-time counter operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output buzzer output 10-bit successive approximation type a/d converter 16-bit ? type a/d converter uart0 uart6 csi10 serial interface csia0 lcd controller/driver manchester code generator remote controller receiver power-on-clear function low-voltage detection function external interrupt operable remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f rl : internal low-speed oscillation clock chapter 23 standby function user?s manual u18329ej4v0ud 655 table 23-1. operating statuses in halt mode (2/2) when halt instruction is executed while cpu is operating on subsystem clock halt mode setting item when cpu is operating on xt1 clock (f xt ) system clock clock supply to the cpu is stopped f rh f x status before halt mode was set is retained main system clock f exclk operates or stops by external clock input subsystem clock f xt operation continues (cannot be stopped) f rl status before halt mode was set is retained cpu operation stopped flash memory operation stopped ram status before halt mode was set is retained port (latch) status before halt mode was set is retained 16-bit timer/event counter 00 note 50 note 51 note 8-bit timer/event counter 52 note h0 h1 8-bit timer h2 real-time counter operable watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable buzzer output 10-bit successive approximation type a/d converter operable. however, operation dis abled when peripheral hardware clock (f prs ) is stopped. 16-bit ? type a/d converter uart0 uart6 csi10 note serial interface csia0 note lcd controller/driver manchester code generator remote controller receiver power-on-clear function low-voltage detection function external interrupt operable note when the cpu is operating on the s ubsystem clock and the internal high-speed oscillation clock has been stopped, do not start operation of thes e functions on the external clock input from peripheral hardware pins. remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f rl : internal low-speed oscillation clock chapter 23 standby function user?s manual u18329ej4v0ud 656 (2) halt mode release the halt mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the halt mode is released. if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 23-3. halt mode release by interrupt request generation halt instruction wait note normal operation halt mode normal operation oscillation high-speed system clock, internal high-speed oscillation clock, or subsystem clock status of cpu standby release signal interrupt request note the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. chapter 23 standby function user?s manual u18329ej4v0ud 657 (b) release by reset signal generation when the reset signal is generated, halt mode is re leased, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 23-4. halt mode release by reset (1) when high-speed system clock is used as cpu clock halt instruction reset signal high-speed system clock (x1 oscillation) halt mode reset period oscillates oscillation stopped oscillates status of cpu normal operation (high-speed system clock) oscillation stabilization time (2 11 /f x to 2 16 /f x ) normal operation (internal high-speed oscillation clock) oscillation stopped starting x1 oscillation is specified by software. reset processing (19 to 80 s) (2) when internal high-speed osc illation clock is used as cpu clock halt instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) halt mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu wait for oscillation accuracy stabilization (86 to 361 s) reset processing (19 to 80 s) (3) when subsystem clo ck is used as cpu clock halt instruction reset signal subsystem clock (xt1 oscillation) normal operation (subsystem clock) halt mode reset period normal operation mode (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stopped starting xt1 oscillation is specified by software. reset processing (19 to 80 s) remark f x : x1 clock oscillation frequency chapter 23 standby function user?s manual u18329ej4v0ud 658 table 23-2. operation in response to interrupt request in halt mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 halt mode held reset ? ? reset processing : don?t care 23.2.2 stop mode (1) stop mode setting and operating statuses the stop mode is set by executing t he stop instruction, and it can be se t only when the cpu clock before the setting was the main system clock. caution because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilizat ion time select register (osts) has elapsed. the operating statuses in t he stop mode are shown below. chapter 23 standby function user?s manual u18329ej4v0ud 659 table 23-3. operating statuses in stop mode when stop instruction is executed while cpu is operating on main system clock stop mode setting item when cpu is operating on internal high-speed oscillation clock (f rh ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f exclk ) system clock clock supply to the cpu is stopped f rh f x stopped main system clock f exclk input invalid subsystem clock f xt status before stop mode was set is retained f rl status before stop mode was set is retained cpu operation stopped flash memory operation stopped ram status before stop mode was set is retained port (latch) status before stop mode was set is retained 16-bit timer/event counter 00 note 1 operable only when tm52 output or ti 000 is selected as the count clock 50 note 1 operable only when ti50 is se lected as the count clock 51 note 1 operable only when ti51 is se lected as the count clock 8-bit timer/event counter 52 note 1 operable only when ti52 is se lected as the count clock h0 operable only when tm50 output is selected as the count clock during 8-bit timer/event counter 50 operation h1 operable only when f rl , f rl /2 7 , f rl /2 9 is selected as the count clock 8-bit timer h2 operation stopped real-time counter operable only when subsystem clock is selected as the count clock watchdog timer operable. clock supply to watchdog ti mer stops when ?internal low-speed oscillator can be stopped by software? is set by option byte. clock output operable only w hen subsystem clock is selected as the count clock buzzer output 10-bit successive approximation type a/d converter operation stopped 16-bit ? type a/d converter note 2 operable uart0 uart6 operable only when tm50 output is selected as the serial clock duri ng 8-bit timer/event counter 50 operation csi10 note 1 operable only when external clock is selected as the serial clock serial interface csia0 note 1 operation stopped lcd controller/driver operable only when subsyst em clock is selected as the count clock manchester code generator operation stopped remote controller receiver operable only when su bsystem clock is selected as the count clock power-on-clear function low-voltage detection function external interrupt operable notes 1. do not start operation of these func tions on the external clock input from peripheral hardware pins in the stop mode. 2. be sure to turn off the power (addpon = 0) of the 16-bit ? type a/d converter, when executing a stop instruction upon selecting f prs /4, f prs /8, or f prs /16 for the sampling clock. remark f rh : internal high-speed oscillation clock f x : x1 clock f exclk : external main system clock f xt : xt1 clock f rl : internal low-speed oscillation clock chapter 23 standby function user?s manual u18329ej4v0ud 660 cautions 1. to use the peripheral ha rdware that stops operation in the stop mode, and the peripheral hardware for which the clock that stops oscillati ng in the stop mode after the stop mode is released, restart the peripheral hardware. 2. even if ?internal low-speed oscillator can be stopped by software? is selected by the option byte, the internal low-speed osc illation clock continues in the stop mode in the status before the stop mode is set. to stop the internal low- speed oscillator?s oscillation in the stop mode, stop it by software and then execute the stop instruction. 3. to shorten oscillation stabiliz ation time after the stop mode is released when the cpu operates with the high-speed system clock (x1 oscillation), switch the cpu clock to the internal high- speed oscillation clock before the execution of the stop instruction using the following procedure. <1> set rstop to 0 (starting oscillati on of the internal high-speed oscillator) <2> set mcm0 to 0 (switching the cpu from x1 oscilla tion to internal high-speed oscillation) <3> check that mcs is 0 (checking the cpu clock) <4> check that rsts is 1 (c hecking internal high-speed oscillation operation) <5> execute the stop instruction before changing the cpu clock from the internal high-speed o scillation clock to the high-speed system clock (x1 oscillation) after the stop mode is released, check the oscillation stabilization time with the oscillation stabilization ti me counter status register (ostc). 4. execute the stop instruction after having conf irmed that the internal high-speed oscillator is operating stably (rsts = 1). (2) stop mode release figure 23-5. operation timing when stop mode is released (when unmasked interrupt request is generated) stop mode stop mode release high-speed system clock (x1 oscillation) high-speed system clock (external clock input) internal high-speed oscillation clock high-speed system clock (x1 oscillation) is selected as cpu clock when stop instruction is executed high-speed system clock (external clock input) is selected as cpu clock when stop instruction is executed internal high-speed oscillation clock is selected as cpu clock when stop instruction is executed wait for oscillation accuracy stabilization (86 to 361 s) halt status (oscillation stabilization time set by osts) automatic selection clock switched by software high-speed system clock high-speed system clock wait note wait note high-speed system clock internal high-speed oscillation clock note the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks chapter 23 standby function user?s manual u18329ej4v0ud 661 the stop mode can be released by the following two sources. (a) release by unmasked interrupt request when an unmasked interrupt request is generated, the stop mode is released. after the oscillation stabilization time has elapsed, if interrupt acknowledg ment is enabled, vectored interrupt servicing is carried out. if interrupt acknowledgment is disabled, the next address instruction is executed. figure 23-6. stop mode release by interrupt request generation (1/2) (1) when high-speed system clock (x 1 oscillation) is used as cpu clock normal operation (high-speed system clock) normal operation (high-speed system clock) oscillates oscillates stop instruction stop mode wait (set by osts) standby release signal oscillation stabilization wait (halt mode status) oscillation stopped high-speed system clock (x1 oscillation) status of cpu oscillation stabilization time (set by osts) interrupt request (2) when high-speed system clock (external clock in put) is used as cpu clock interrupt request stop instruction standby release signal status of cpu high-speed system clock (external clock input) normal operation (high-speed system clock) oscillates stop mode oscillation stopped wait note normal operation (high-speed system clock) oscillates note the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 23 standby function user?s manual u18329ej4v0ud 662 figure 23-6. stop mode release by interrupt request generation (2/2) (3) when internal high-speed osc illation clock is used as cpu clock wait note wait for oscillation accuracy stabilization (86 to 361 s) oscillates normal operation (internal high-speed oscillation clock) stop mode oscillation stopped oscillates normal operation (internal high-speed oscillation clock) internal high-speed oscillation clock status of cpu standby release signal stop instruction interrupt request note the wait time is as follows: ? when vectored interrupt servicing is carried out: 8 or 9 clocks ? when vectored interrupt servicing is not carried out: 2 or 3 clocks remark the broken lines indicate the case when the inte rrupt request that has re leased the standby mode is acknowledged. chapter 23 standby function user?s manual u18329ej4v0ud 663 (b) release by reset signal generation when the reset signal is generated, stop mode is released, and then, as in the case with a normal reset operation, the program is executed after br anching to the reset vector address. figure 23-7. stop mode release by reset (1) when high-speed system clock is used as cpu clock stop instruction reset signal high-speed system clock (x1 oscillation) normal operation (high-speed system clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped oscillates status of cpu oscillation stabilization time (2 11 /f x to 2 16 /f x ) oscillation stopped starting x1 oscillation is specified by software. oscillation stopped reset processing (19 to 80 s) (2) when internal high-speed osc illation clock is used as cpu clock stop instruction reset signal internal high-speed oscillation clock normal operation (internal high-speed oscillation clock) stop mode reset period normal operation (internal high-speed oscillation clock) oscillates oscillation stopped status of cpu oscillates oscillation stopped wait for oscillation accuracy stabilization (86 to 361 s) reset processing (19 to 80 s) remark f x : x1 clock oscillation frequency table 23-4. operation in response to interrupt request in stop mode release source mk pr ie isp operation 0 0 0 next address instruction execution 0 0 1 interrupt servicing execution 0 1 0 1 0 1 0 next address instruction execution 0 1 1 1 interrupt servicing execution maskable interrupt request 1 stop mode held reset ? ? reset processing : don?t care user?s manual u18329ej4v0ud 664 chapter 24 reset function the following four operations are av ailable to generate a reset signal. (1) external reset input via reset pin (2) internal reset by watchdog timer program loop detection (3) internal reset by comparison of supply voltage and detection voltage of power-on-clear (poc) circuit (4) internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (lvi) external and internal resets have no functional differences . in both cases, program ex ecution starts at the address at 0000h and 0001h when the reset signal is generated. a reset is applied when a low level is input to the reset pin, the watchdog timer overflows, or by poc and lvi circuit voltage detection, and each item of hardware is set to the status shown in tables 24-1 and 24-2. each pin is high impedance during reset signal generation or during the osc illation stabilization time just after a reset release. when a low level is input to the reset pin, the device is reset. it is released from the reset status when a high level is input to the reset pin and program execution is started with the internal high- speed oscillation clock after reset processing. a reset by the watchdog timer is autom atically released, and program execution starts using the internal high-speed oscillation clock (see figures 24-2 to 24-4 ) after reset processing. reset by poc and lvi circuit power supply detection is automatically released when v dd v poc or v dd v lvi after the reset, and program execution starts using the internal high-speed oscillation clock (see chapter 25 power-on-clear circuit and chapter 26 low-voltage detector ) after reset processing. cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. during reset input, the x1 clo ck, xt1 clock, internal high-speed oscillati on clock, and internal low-speed oscillation clock stop oscillating. external main system clock input becomes invalid. 3. when the stop mode is released by a reset , the stop mode contents are held during reset input. however, the port pins become high-impedance. chapter 24 reset function user?s manual u18329ej4v0ud 665 figure 24-1. block di agram of reset function lvirf wdtrf reset control flag register (resf) internal bus watchdog timer reset signal reset power-on-clear circuit reset signal low-voltage detector reset signal reset signal reset signal to lvim/lvis register clear set clear set caution an lvi circuit internal r eset does not reset the lvi circuit. remarks 1. lvim: low-voltage detection register 2. lvis: low-voltage detection level selection register chapter 24 reset function user?s manual u18329ej4v0ud 666 figure 24-2. timing of reset by reset input delay delay (5 s (typ.)) hi-z normal operation cpu clock reset period (oscillation stop) normal operation (internal high-speed oscillation clock) reset internal reset signal port pin high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. reset processing (19 to 80 s) wait for oscillation accuracy stabilization (86 to 361 s) figure 24-3. timing of reset du e to watchdog timer overflow normal operation reset period (oscillation stop) cpu clock watchdog timer overflow internal reset signal hi-z port pin high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (19 to 80 s) wait for oscillation accuracy stabilization (86 to 361 s) caution a watchdog timer internal reset resets the watchdog timer. chapter 24 reset function user?s manual u18329ej4v0ud 667 figure 24-4. timing of reset in stop mode by reset input delay normal operation cpu clock reset period (oscillation stop) reset internal reset signal stop instruction execution stop status (oscillation stop) high-speed system clock (when x1 oscillation is selected) internal high-speed oscillation clock hi-z port pin starting x1 oscillation is specified by software. normal operation (internal high-speed oscillation clock) reset processing (19 to 80 s) delay (5 s (typ.)) wait for oscillation accuracy stabilization (86 to 361 s) remark for the reset timing of the power-on-cl ear circuit and low-voltage detector, see chapter 25 power- on-clear circuit and chapter 26 low-voltage detector . chapter 24 reset function user?s manual u18329ej4v0ud 668 table 24-1. operation st atuses during reset period item during reset period system clock clock supply to the cpu is stopped. f rh operation stopped f x operation stopped (pin is i/o port mode) main system clock f exclk clock input invalid (pin is i/o port mode) subsystem clock f xt operation stopped (pin is i/o port mode) f rl cpu flash memory ram port (latch) 16-bit timer/event counter 00 50 51 8-bit timer/event counter 52 h0 h1 8-bit timer h2 real-time counter watchdog timer clock output buzzer output 10-bit successive approximation type a/d converter 16-bit ? type a/d converter uart0 uart6 csi10 serial interface csia0 lcd controller/driver manchester code generator remote controller receiver operation stopped power-on-clear f unction operable low-voltage detection function external interrupt operation stopped remark f rh : internal high-speed oscillation clock f x : x1 oscillation clock f exclk : external main system clock f xt : xt1 oscillation clock f rl : internal low-speed oscillation clock chapter 24 reset function user?s manual u18329ej4v0ud 669 table 24-2. hardware statuses after reset acknowledgment (1/4) hardware after reset acknowledgment note 1 program counter (pc) the contents of the reset vector table (0000h, 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose registers undefined note 2 port registers (p1 to p4, p8 to p15) (output latches) 00h port mode registers (pm1 to pm4, pm8 to pm15) ffh pull-up resistor option registers (pu1, pu3, pu4, pu8 to pu15) 00h port function register 1 (pf1) 00h port function register 2 (pf2) 00h port function register all (pfall) 00h internal expansion ram size switching register (ixs) 0ch note 3 internal memory size switching register (ims) cfh note 3 clock operation mode select register (oscctl) 00h processor clock control register (pcc) 01h internal oscillation mode register (rcm) 80h main osc control register (moc) 80h main clock mode register (mcm) 00h oscillation stabilization time counter status register (ostc) 00h oscillation stabilization time select register (osts) 05h internal high-speed oscillation tr imming register (hiotrm) 10h timer counters 00 (tm00) 0000h capture/compare registers 000, 010 (cr000, cr010) 0000h mode control registers 00 (tmc00) 00h prescaler mode registers 00 (prm00) 00h capture/compare control registers 00 (crc00) 00h 16-bit timer/event counters 00 timer output control registers 00 (toc00) 00h timer counters 50, 51, 52 (tm50, tm51, tm52) 00h compare registers 50, 51, 52 (cr50, cr51, cr52) 00h timer clock selection registers 50, 51, 52 (tcl50, tcl51, tcl52) 00h 8-bit timer/event counters 50, 51, 52 mode control registers 50, 51, 52 (tmc50, tmc51, tmc52) 00h notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. when a reset is executed in the standby mode, the pre-reset status is held even after reset. 3. the initial values of the internal memory size s witching register (ims) and internal expansion ram size switching register (ixs) after a reset release are c onstant (ims = cfh, ixs = 0ch) in all the 78k0/lf3 products, regardless of the internal memory capacity. therefore, after a reset is released, be sure to set the following values for each product. flash memory version (78k0/lf3) ims ixs pd78f0471, 78f0481, 78f0491 04h pd78f0472, 78f0482, 78f0492 c6h pd78f0473, 78f0483, 78f0493 c8h 0ch pd78f0474, 78f0484, 78f0494 cch pd78f0475, 78f0485, 78f0495 cfh 0ah chapter 24 reset function user?s manual u18329ej4v0ud 670 table 24-2. hardware statuses after reset acknowledgment (2/4) hardware status after reset acknowledgment note 1 compare registers 00, 10, 01, 11, 02, 12 (cmp00, cmp10, cmp01, cmp11, cmp02, cmp12) 00h mode registers (tmhmd0, tmhmd1, tmhmd2) 00h 8-bit timers h0, h1, h2 carrier control register 1 (tmcyc1) note 2 00h clock selection register (rtccl) 00h sub-count register (rsubc) 0000h second count register (sec) 00h minute count register (min) 00h hour count register (hour) 12h week count register (week) 00h day count register (day) 01h month count register (month) 01h year count register (year) 00h watch error correction register (subcud) 00h alarm minute register (alarmwm) 00h alarm hour register (alarmwh) 12h alarm week register (alarmww) 00h control register 0 (rtcc0) 00h control register 1 (rtcc1) 00h real-time counter control register 2 (rtcc2) 00h clock output/buzzer output controller clock output selection register (cks) 00h watchdog timer enable register (wdte) 1ah/9ah note 3 10-bit a/d conversion result register (adcr) 0000h 8-bit a/d conversion result register (adcrh) 00h a/d converter mode register (adm) 00h analog input channel specification register (ads) 00h 10-bit successive approximation type a/d converter a/d port configuration register 0 (adpc0) 08h ? a/d converter control register 0 (addctl0) 00h ? a/d converter control register 1 (addctl1) 00h 16-bit ? a/d conversion status register (addstr) 00h 16-bit ? a/d conversion result register (addcr) 0000h 16-bit ? type a/d converter 8-bit ? a/d conversion result register (addcrh) 00h receive buffer register 0 (rxb0) ffh transmit shift register 0 (txs0) ffh asynchronous serial interface oper ation mode register 0 (asim0) 01h asynchronous serial interface reception error status register 0 (asis0) 00h serial interface uart0 baud rate generator control register 0 (brgc0) 1fh notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. 8-bit timer h1 only. 3. the reset value of wdte is dete rmined by the option byte setting. chapter 24 reset function user?s manual u18329ej4v0ud 671 table 24-2. hardware statuses after reset acknowledgment (3/4) hardware status after reset acknowledgment note 1 receive buffer register 6 (rxb6) ffh transmit buffer register 6 (txb6) ffh asynchronous serial interface oper ation mode register 6 (asim6) 01h asynchronous serial interface reception error status register 6 (asis6) 00h asynchronous serial interface transmis sion status register 6 (asif6) 00h clock selection register 6 (cksr6) 00h baud rate generator control register 6 (brgc6) ffh asynchronous serial interface control register 6 (asicl6) 16h serial interface uart6 input switch control register (isc) 00h transmit buffer registers 10 (sotb10) 00h serial i/o shift regi sters 10 (sio10) 00h serial operation mode registers 10 (csim10) 00h serial interfaces csi10 serial clock selection r egisters 10 (csic10) 00h serial operation mode specification register 0 (csima0) 00h serial status register 0 (csis0) 00h serial trigger register 0 (csit0) 00h divisor value selection r egister 0 (brgca0) 03h automatic data transfer address point specification register 0 (adtp0) 00h automatic data transfer interval specification register 0 (adti0) 00h serial i/o shift register 0 (sioa0) 00h serial interface csia0 automatic data transfer address count register 0 (adtc0) 00h lcd mode register (lcdmd) 00h lcd display mode register (lcdm) 00h lcd controller/driver lcd clock control register 0 (lcdc0) 00h transmit buffer register (mc0tx) ffh transmit bit count specification register (mc0bit) 07h control register 0 (mc0ctl0) 10h control register 1 (mc0ctl1) 00h control register 2 (mc0ctl2) 1fh manchester code generator status register (mc0str) 00h key interrupt key return mode register (krm) 00h reset function reset control flag register (resf) 00h note 2 low-voltage detection register (lvim) 00h note 2 low-voltage detector low-voltage detection level selection register (lvis) 00h note 2 notes 1. during reset signal generation or oscillation st abilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remain unchanged after reset. 2. these values vary depending on the reset source. reset source register reset input reset by poc reset by wdt reset by lvi wdtrf bit set (1) held resf lvirf bit cleared (0) cleared (0) held set (1) lvim lvis cleared (00h) cleared (00h) cleared (00h) held chapter 24 reset function user?s manual u18329ej4v0ud 672 table 24-2. hardware statuses after reset acknowledgment (4/4) hardware status after reset acknowledgment note remote controller receive shift register (rmsr) 00h remote controller receive data register (rmdr) 00h remote controller shift register receive counter register (rmscr) 00h remote controller receive gphs compare register (rmgphs) 00h remote controller receive gphl compare register (rmgphl) 00h remote controller receive dls compare register (rmdls) 00h remote controller receive dll compare register (rmdll) 00h remote controller receive dh0s compare register (rmdh0s) 00h remote controller receive dh0l compare register (rmdh0l) 00h remote controller receive dh1s compare register (rmdh1s) 00h remote controller receive dh1l compare register (rmdh1l) 00h remote controller receive end width select register (rmer) 00h remote controller receive interrupt status register (ints) 00h remote controller receive interrupt status clear register (intc) 00h remote controller receiver remote controller receive control register (rmcn) 00h request flag registers 0l, 0h, 1l, 1h (if0l, if0h, if1l, if1h) 00h mask flag registers 0l, 0h, 1l, 1h (mk0l, mk0h, mk1l, mk1h) ffh priority specification fl ag registers 0l, 0h, 1l, 1h (pr0l, pr0h, pr1l, pr1h) ffh external interrupt rising edge enable register (egp) 00h interrupt external interrupt falling edge enable register (egn) 00h note during reset signal generation or oscillation stabiliz ation time wait, only the pc contents among the hardware statuses become undefined. all other hardwar e statuses remain unchanged after reset. chapter 24 reset function user?s manual u18329ej4v0ud 673 24.1 register for confirming reset source many internal reset generation sources exist in the 78k0 /lf3. the reset control flag register (resf) is used to store which source has generated the reset request. resf can be read by an 8-bit memory manipulation instruction. reset input, reset by power-on-clear (poc) circuit, and reading resf set resf to 00h. figure 24-5. format of reset control flag register (resf) address: ffach after reset: 00h note r symbol 7 6 5 4 3 2 1 0 resf 0 0 0 wdtrf 0 0 0 lvirf wdtrf internal reset request by watchdog timer (wdt) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. lvirf internal reset request by low-voltage detector (lvi) 0 internal reset request is not generated, or resf is cleared. 1 internal reset request is generated. note the value after reset varies depending on the reset source. caution do not read data by a 1-bi t memory manipulation instruction. the status of resf when a reset request is generated is shown in table 24-3. table 24-3. resf status when reset request is generated reset source flag reset input reset by poc reset by wdt reset by lvi wdtrf set (1) held lvirf cleared (0) cleared (0) held set (1) user?s manual u18329ej4v0ud 674 chapter 25 power-on-clear circuit 25.1 functions of power-on-clear circuit the power-on-clear circuit (poc) has the following functions. ? generates internal reset signal at power on. in the 1.59 v poc mode (option byte: pocmode = 0), the reset signal is released when the supply voltage (v dd ) exceeds 1.59 v 0.15 v. in the 2.7 v/1.59 v poc m ode (option byte: pocmode = 1), the re set signal is released when the supply voltage (v dd ) exceeds 2.7 v 0.2 v. ? compares supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v), generates internal reset signal when v dd < v poc . caution if an internal reset signal is generated in the poc circuit, th e reset control flag register (resf) is cleared to 00h. remark 78k0/lf3 incorporates multiple har dware functions that generate an inte rnal reset signal. a flag that indicates the reset source is located in the rese t control flag register (resf) for when an internal reset signal is generated by the watchdog timer (w dt) or low-voltage-detector (lvi). resf is not cleared to 00h and the flag is set to 1 when an in ternal reset signal is generated by wdt or lvi. for details of resf, see chapter 24 reset function . chapter 25 power-on-clear circuit user?s manual u18329ej4v0ud 675 25.2 configuration of power-on-clear circuit the block diagram of the power-on-clear circuit is shown in figure 25-1. figure 25-1. block diagram of power-on-clear circuit ? + reference voltage source internal reset signal v dd v dd 25.3 operation of power-on-clear circuit (1) in 1.59 v poc mode (option byte: pocmode = 0) ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v poc = 1.59 v 0.15 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v poc . (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) ? an internal reset signal is generated on power application. when the supply voltage (v dd ) exceeds the detection voltage (v ddpoc = 2.7 v 0.2 v), the reset status is released. ? the supply voltage (v dd ) and detection voltage (v poc = 1.59 v 0.15 v) are compared. when v dd < v poc , the internal reset signal is generated. it is released when v dd v ddpoc . the timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown below. chapter 25 power-on-clear circuit user?s manual u18329ej4v0ud 676 figure 25-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) note 3 note 3 internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. operation stops wait for voltage stabilization (1.93 to 5.39 ms) normal operation (internal high-speed oscillation clock) note 4 operation stops reset period (oscillation stop) reset period (oscillation stop) wait for oscillation accuracy stabilization (86 to 361 s) normal operation (internal high-speed oscillation clock) note 4 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 wait for voltage stabilization (1.93 to 5.39 ms) normal operation (internal high-speed oscillation clock ) note 4 0.5 v/ms (min.) note 2 set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt internal reset signal reset processing (19 to 80 s) reset processing (11 to 47 s) reset processing (19 to 80 s) v poc = 1.59 v (typ.) v lvi notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. if the voltage rises to 1.8 v at a rate slower than 0.5 v/ms (min.) on power applic ation, input a low level to the reset pin after power application and before the voltage reaches 1.8 v, or set the 2.7 v/1.59 v poc mode by using an option byte (pocmode = 1). 3. the internal voltage stabilization time includes the o scillation accuracy stabilization time of the internal high-speed oscillation clock. 4. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. caution set the low-voltage detector by software after the reset status is released (see chapter 26 low-voltage detector). remark v lvi : lvi detection voltage v poc : poc detection voltage chapter 25 power-on-clear circuit user?s manual u18329ej4v0ud 677 figure 25-2. timing of generation of intern al reset signal by power-on-clear circuit and low-voltage detector (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) internal high-speed oscillation clock (f rh ) high-speed system clock (f xh ) (when x1 oscillation is selected) starting oscillation is specified by software. internal reset signal operation stops normal operation (internal high-speed oscillation clock) note 2 normal operation (internal high-speed oscillation clock) note 2 operation stops reset period (oscillation stop) reset period (oscillation stop) normal operation (internal high-speed oscillation clock) note 2 starting oscillation is specified by software. starting oscillation is specified by software. cpu 0 v supply voltage (v dd ) 1.8 v note 1 reset processing (11 to 47 s) reset processing (11 to 47 s) reset processing (11 to 47 s) set lvi to be used for reset set lvi to be used for reset set lvi to be used for interrupt wait for oscillation accuracy stabilization (86 to 361 s) wait for oscillation accuracy stabilization (86 to 361 s) wait for oscillation accuracy stabilization (86 to 361 s) v ddpoc = 2.7 v (typ.) v poc = 1.59 v (typ.) v lvi notes 1. the operation guaranteed range is 1.8 v v dd 5.5 v. to make the state at lower than 1.8 v reset state when the supply voltage falls, us e the reset function of the low-vo ltage detector, or input the low level to the reset pin. 2. the internal high-speed oscillation clock and a hi gh-speed system clock or subsystem clock can be selected as the cpu clock. to us e the x1 clock, use the ostc regi ster to confirm the lapse of the oscillation stabilization time. to use the xt1 clock, use the timer function for confirmation of the lapse of the stabilization time. cautions 1. set the low-voltage det ector by software after the reset st atus is released (see chapter 26 low-voltage detector). 2. a voltage oscillation stabilization time of 1. 93 to 5.39 ms is required after the supply voltage reaches 1.59 v (typ.). if the ti me the supply voltage rises from 1.59 v (typ.) to 2.7 v (typ.) is within 1.93 to 5.39 ms, a power supply stabiliz ation wait time of 0 to 5.39 ms occurs automatically before reset processing and th e reset processing time becomes 19 to 80 s. remark v lvi : lvi detection voltage v poc : poc detection voltage chapter 25 power-on-clear circuit user?s manual u18329ej4v0ud 678 25.4 cautions for power-on-clear circuit in a system where the supply voltage (v dd ) fluctuates for a certain period in the vicinity of the poc detection voltage (v poc ), the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the oper ation of the microcontroller can be arbitrarily set by taking the following action. chapter 25 power-on-clear circuit user?s manual u18329ej4v0ud 679 figure 25-3. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector no wdtrf of resf register = 1? lvirf of resf register = 1? yes user?s manual u18329ej4v0ud 680 chapter 26 low-voltage detector 26.1 functions of low-voltage detector the low-voltage detector (lvi ) has the following functions. ? the lvi circuit compares the supply voltage (v dd ) with the detection voltage (v lvi ) or the input voltage from an external input pin (exlvi) with the detection voltage (v exlvi = 1.21 v (typ.): fixed), and generates an internal reset or internal interrupt signal. ? the supply voltage (v dd ) or input voltage from an external input pin (exlvi) can be selected by software. ? reset or interrupt function can be selected by software. ? detection levels (16 levels) of suppl y voltage can be changed by software. ? operable in stop mode. the reset and interrupt signals are generated as follows depending on selection by software. selection of level detection of supply voltage (v dd ) (lvisel = 0) selection level detection of input voltage from external input pin (exlvi) (lvisel = 1) selects reset (lvimd = 1). selects interrupt (lvimd = 0). selects reset (lvimd = 1). selects interrupt (lvimd = 0). generates an internal reset signal when v dd < v lvi and releases the reset signal when v dd v lvi . generates an internal interrupt signal when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). generates an internal reset signal when exlvi < v exlvi and releases the reset signal when exlvi v exlvi . generates an internal interrupt signal when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). remark lvisel: bit 2 of low-voltage detection register (lvim) lvimd: bit 1 of lvim while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). when the low-voltage detector is used to reset, bit 0 (lvirf) of the reset control flag regi ster (resf) is set to 1 if reset occurs. for details of resf, see chapter 24 reset function . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 681 26.2 configuration of low-voltage detector the block diagram of the low-voltage detector is shown in figure 26-1. figure 26-1. block diagram of low-voltage detector lvis1 lvis0 lvion ? + reference voltage source v dd internal bus n-ch low-voltage detection level selection register (lvis) low-voltage detection register (lvim) lvis2 lvis3 lvif intlvi internal reset signal 4 lvisel exlvi/p120/ intp0 lvimd v dd low-voltage detection level selector selector selector 26.3 registers controlling low-voltage detector the low-voltage detector is contro lled by the following registers. ? low-voltage detection register (lvim) ? low-voltage detection level selection register (lvis) ? port mode register 12 (pm12) (1) low-voltage detection register (lvim) this register sets low-voltag e detection and the operation mode. this register can be set by a 1-bit or 8-bit memory manipulation instruction. the generation of a reset signal other than an lvi reset clears th is register to 00h. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 682 figure 26-2. format of low-volta ge detection register (lvim) <0> lvif <1> lvimd <2> lvisel 3 0 4 0 5 0 6 0 <7> lvion symbol lvim address: ffbeh after reset: 00h note 1 r/w note 2 lvion notes 3, 4 enables low-voltage detection operation 0 disables operation 1 enables operation lvisel note 3 voltage detection selection 0 detects level of supply voltage (v dd ) 1 detects level of input voltage from external input pin (exlvi) lvimd note 3 low-voltage detection operation m ode (interrupt/reset) selection 0 ? lvisel = 0: generates an internal interrupt signal when the supply voltage (v dd ) drops lower than the detection voltage (v lvi ) (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ). ? lvisel = 1: generates an interrupt signal when the input voltage from an external input pin (exlvi) drops lower than the detection voltage (v exlvi ) (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ). 1 ? lvisel = 0: generates an internal reset signal when the supply voltage (v dd ) < detection voltage (v lvi ) and releases the reset signal when v dd v lvi . ? lvisel = 1: generates an internal reset signal when the input voltage from an external input pin (exlvi) < detection voltage (v exlvi ) and releases the reset signal when exlvi v exlvi . lvif low-voltage detection flag 0 ? lvisel = 0: supply voltage (v dd ) detection voltage (v lvi ), or when operation is disabled ? lvisel = 1: input voltage from external input pin (exlvi) detection voltage (v exlvi ), or when operation is disabled 1 ? lvisel = 0: supply voltage (v dd ) < detection voltage (v lvi ) ? lvisel = 1: input voltage from external input pin (exlvi) < detection voltage (v exlvi ) notes 1. this bit is cleared to 00h upon a reset other than an lvi reset. 2. bit 0 is read-only. 3. lvion, lvimd, and lvisel are cleared to 0 in the case of a reset other than an lvi reset. these are not cleared to 0 in the case of an lvi reset. 4. when lvion is set to 1, operation of the com parator in the lvi circuit is started. use software to wait for an operation stabilization time (10 s (max.)) from when lvion is set to 1 until operation is stabilized. after operation has stabilized, 200 s (min.) are required from when a state below lvi detection voltage has been entered, until lvif is set (1). cautions 1. to stop lvi, follow either of the procedures below. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. 2. input voltage from external input pin (exlvi) must be exlvi < v dd . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 683 caution 3. when using lvi as an interrupt, if lvion is cleared (0) in a state below the lvi detection voltage, an intlvi signal is generate d and lviif becomes 1. (2) low-voltage detection l evel selection register (lvis) this register selects the low-voltage detection level. this register can be set by a 1-bit or 8-bit memory manipulation instruction. the generation of a reset signal other than an lvi reset clears th is register to 00h. figure 26-3. format of low-voltage dete ction level selection register (lvis) 0 lvis0 1 lvis1 2 lvis2 3 lvis3 4 0 5 0 6 0 7 0 symbol lvis address: ffbfh after reset: 00h note r/w lvis3 lvis2 lvis1 lvis0 detection level 0 0 0 0 v lvi0 (4.24 v 0.1 v) 0 0 0 1 v lvi1 (4.09 v 0.1 v) 0 0 1 0 v lvi2 (3.93 v 0.1 v) 0 0 1 1 v lvi3 (3.78 v 0.1 v) 0 1 0 0 v lvi4 (3.62 v 0.1 v) 0 1 0 1 v lvi5 (3.47 v 0.1 v) 0 1 1 0 v lvi6 (3.32 v 0.1 v) 0 1 1 1 v lvi7 (3.16 v 0.1 v) 1 0 0 0 v lvi8 (3.01 v 0.1 v) 1 0 0 1 v lvi9 (2.85 v 0.1 v) 1 0 1 0 v lvi10 (2.70 v 0.1 v) 1 0 1 1 v lvi11 (2.55 v 0.1 v) 1 1 0 0 v lvi12 (2.39 v 0.1 v) 1 1 0 1 v lvi13 (2.24 v 0.1 v) 1 1 1 0 v lvi14 (2.08 v 0.1 v) 1 1 1 1 v lvi15 (1.93 v 0.1 v) note the value of lvis is not reset but retained as is, upon a reset by lvi. it is cleared to 00h upon other resets. cautions 1. be sure to cl ear bits 4 to 7 to ?0?. 2. do not change the value of lvis during lvi operation. 3. when an input voltage from the externa l input pin (exlvi) is detected, the detection voltage (v exlvi = 1.21 v (typ.)) is fixed. therefor e, setting of lvis is not necessary. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 684 (3) port mode register 12 (pm12) when using the p120/exlvi/intp0 pin for external low-volt age detection potential input, set pm120 to 1. at this time, the output latch of p120 may be 0 or 1. pm12 can be set by a 1-bit or 8-bit memory manipulation instruction. reset signal generation sets pm12 to ffh. figure 26-4. format of port mode register 12 (pm12) 0 pm120 1 1 2 1 3 1 4 1 5 1 6 1 7 1 symbol pm12 address: ff2ch after reset: ffh r/w pm120 p120 pin i/o mode selection 0 output mode (output buffer on) 1 input mode (output buffer off) 26.4 operation of low-voltage detector the low-voltage detector can be us ed in the following two modes. (1) used as reset (lvimd = 1) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ), generates an internal reset signal when v dd < v lvi , and releases internal reset when v dd v lvi . ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)), generates an internal reset signal when exlvi < v exlvi , and releases internal reset when exlvi v exlvi . (2) used as interrupt (lvimd = 0) ? if lvisel = 0, compares the supply voltage (v dd ) and detection voltage (v lvi ). when v dd drops lower than v lvi (v dd < v lvi ) or when v dd becomes v lvi or higher (v dd v lvi ), generates an interrupt signal (intlvi). ? if lvisel = 1, compares the input voltage from external input pin (exlvi) and detection voltage (v exlvi = 1.21 v (typ.)). when exlvi drops lower than v exlvi (exlvi < v exlvi ) or when exlvi becomes v exlvi or higher (exlvi v exlvi ), generates an interrupt signal (intlvi). while the low-voltage detector is operat ing, whether the supply voltage or t he input voltage from an external input pin is more than or less than the detection level can be che cked by reading the low-voltage detection flag (lvif: bit 0 of lvim). remark lvimd: bit 1 of low-voltage detection register (lvim) lvisel: bit 2 of lvim chapter 26 low-voltage detector user?s manual u18329ej4v0ud 685 26.4.1 when used as reset (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection r egister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (max.)). <6> wait until it is checked that (supply voltage (v dd ) detection voltage (v lvi )) by bit 0 (lvif) of lvim. <7> set bit 1 (lvimd) of lvim to 1 (generates reset when the level is detected). figure 26-5 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <7> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <4>. 2. if supply voltage (v dd ) detection voltage (v lvi ) when lvimd is set to 1, an internal reset signal is not generated. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 686 figure 26-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) supply voltage (v dd ) <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> v lvi v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 24 reset function . remark <1> to <7> in figure 26-5 above correspond to <1> to <7> in the description of ?when starting operation? in 26.4.1 (1) when detecting level of supply voltage (v dd ) . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 687 figure 26-5. timing of low-voltage dete ctor internal reset signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) supply voltage (v dd ) v lvi <3> <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal poc reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <4> <7> clear clear clear <5> wait time lvion flag (set by software) lvimd flag (set by software) h note 1 l lvisel flag (set by software) <6> <2> 2.7 v (typ.) v poc = 1.59 v (typ.) notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 24 reset function . remark <1> to <7> in figure 26-5 above correspond to <1> to <7> in the description of ?when starting operation? in 26.4.1 (1) when detecting level of supply voltage (v dd ) . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 688 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time (10 s (max.)). <5> wait until it is checked that (input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.))) by bit 0 (lvif) of lvim. <6> set bit 1 (lvimd) of lvim to 1 (generates reset signal when the level is detected). figure 26-6 shows the timing of the internal reset signal generated by the low-volt age detector. the numbers in this timing chart correspond to <1> to <6> above. cautions 1. <1> must always be executed. when lvimk = 0, an interrupt may occur immediately after the processing in <3>. 2. if input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)) when lvimd is set to 1, an intern al reset signal is not generated. 3. input voltage from external input pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvimd to 0 and then lvion to 0. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 689 figure 26-6. timing of low-voltage dete ctor internal reset signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) lvi detection voltage (v exlvi ) <1> time lvimk flag (set by software) lvif flag lvirf flag note 3 note 2 lvi reset signal internal reset signal cleared by software not cleared not cleared not cleared not cleared cleared by software <3> <6> lvion flag (set by software) lvimd flag (set by software) h note 1 lvisel flag (set by software) <5> <2> not cleared not cleared <4> wait time not cleared not cleared not cleared notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the lvif flag may be set (1). 3. lvirf is bit 0 of the reset control flag re gister (resf). for details of resf, see chapter 24 reset function . remark <1> to <6> in figure 26-6 above correspond to <1> to <6> in the description of ? when starting operation? in 26.4.1 (2) when detecting level of input voltage from external input pin (exlvi) . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 690 26.4.2 when used as interrupt (1) when detecting level of supply voltage (v dd ) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> clear bit 2 (lvisel) of the low-voltage detection r egister (lvim) to 0 (detects level of supply voltage (v dd )) (default value). <3> set the detection voltage using bits 3 to 0 (lvis3 to lvis0) of the low-voltage detection level selection register (lvis). <4> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <5> use software to wait for an operation stabilization time (10 s (max.)). <6> confirm that ?supply voltage (v dd ) detection voltage (v lvi )? when detecting the falling edge of v dd , or ?supply voltage (v dd ) < detection voltage (v lvi )? when detecting the rising edge of v dd , at bit 0 (lvif) of lvim. <7> clear the interrupt request flag of lvi (lviif) to 0. <8> release the interrupt mask flag of lvi (lvimk). <9> clear bit 1 (lvimd) of lvim to 0 (generates interr upt signal when the level is detected) (default value). <10> execute the ei instruction (w hen vector interrupts are used). figure 26-7 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <9> above. ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 691 figure 26-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (1/2) (1) in 1.59 v poc mode (option byte: pocmode = 0) supply voltage (v dd ) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <9> v lvi v poc = 1.59 v (typ.) note 2 note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lvi detection voltage, an intlvi signal is generated and lviif becomes 1. remark <1> to <9> in figure 26-7 above correspond to <1> to <9> in the description of ?when starting operation? in 26.4.2 (1) when detecting level of supply voltage (v dd ) . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 692 figure 26-7. timing of low-voltage de tector interrupt signal generation (detects level of supply voltage (v dd )) (2/2) (2) in 2.7 v/1.59 v poc mode (option byte: pocmode = 1) supply voltage (v dd ) time <1> note 1 <8> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag internal reset signal <4> <6> <7> cleared by software <5> wait time lvion flag (set by software) note 2 note 2 <3> l lvisel flag (set by software) <2> lvimd flag (set by software) l <9> v lvi 2.7 v(typ.) v poc = 1.59 v (typ.) note 2 note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lvi detection voltage, an intlvi signal is generated and lviif becomes 1. remark <1> to <9> in figure 26-7 above correspond to <1> to <9> in the description of ?when starting operation? in 26.4.2 (1) when detecting level of supply voltage (v dd ) . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 693 (2) when detecting level of input vo ltage from external input pin (exlvi) ? when starting operation <1> mask the lvi interrupt (lvimk = 1). <2> set bit 2 (lvisel) of the low-voltage detection regist er (lvim) to 1 (detects level of input voltage from external input pin (exlvi)). <3> set bit 7 (lvion) of lvim to 1 (enables lvi operation). <4> use software to wait for an operation stabilization time (10 s (max.)). <5> confirm that ?input voltage from external input pin (exlvi) detection voltage (v exlvi = 1.21 v (typ.)? when detecting the falling edge of exlvi, or ?input vo ltage from external input pin (exlvi) < detection voltage (v exlvi = 1.21 v (typ.)? when detecting the rising e dge of exlvi, at bit 0 (lvif) of lvim. <6> clear the interrupt request flag of lvi (lviif) to 0. <7> release the interrupt mask flag of lvi (lvimk). <8> clear bit 1 (lvimd) of lvim to 0 (generates interr upt signal when the level is detected) (default value). <9> execute the ei instruction (w hen vector interrupts are used). figure 26-8 shows the timing of the interrupt signal ge nerated by the low-voltage detector. the numbers in this timing chart correspond to <1> to <8> above. caution input voltage from external i nput pin (exlvi) must be exlvi < v dd . ? when stopping operation either of the following pr ocedures must be executed. ? when using 8-bit memory manipulation instruction: write 00h to lvim. ? when using 1-bit memory manipulation instruction: clear lvion to 0. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 694 figure 26-8. timing of low-voltage detector interrupt signal generation (detects level of input voltage fr om external input pin (exlvi)) input voltage from external input pin (exlvi) v exlvi time <1> note 1 <7> cleared by software lvimk flag (set by software) lvif flag intlvi lviif flag <3> <5> <6> cleared by software <4> wait time lvion flag (set by software) note 2 note 2 lvisel flag (set by software) <2> lvimd flag (set by software) l <8> note 2 note 3 note 3 notes 1. the lvimk flag is set to ?1? by reset signal generation. 2. the interrupt request signal (intlvi) is generat ed and the lvif and lviif flags may be set (1). 3. if lvion is cleared (0) in a state below the lvi detection voltage, an intlvi signal is generated and lviif becomes 1. remark <1> to <8> in figure 26-8 above correspond to <1> to <8> in the description of ?when starting operation? in 26.4.2 (2) when detecting level of in put voltage from external input pin (exlvi) . chapter 26 low-voltage detector user?s manual u18329ej4v0ud 695 26.5 cautions for low-voltage detector in a system where the supply voltage (v dd ) fluctuates for a certain period in t he vicinity of the lvi detection voltage (v lvi ), the operation is as follows depending on how the low-voltage detector is used. (1) when used as reset the system may be repeatedly reset and released from the reset status. in this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking action (1) below. (2) when used as interrupt interrupt requests may be frequently generated. take (b) of action (2) below. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 696 figure 26-9. example of software processing after reset release (1/2) ? if supply voltage fluctuation is 50 ms or less in vicinity of lvi detection voltage ; check the reset source note initialize the port. reset initialization processing <1> 50 ms have passed? (tmifh1 = 1?) initialization processing <2> setting 8-bit timer h1 (to measure 50 ms) ; setting of division ratio of system clock, such as setting of timer or a/d converter yes no clearing wdt detection voltage or higher (lvif = 0?) yes restarting timer h1 (tmhe1 = 0 tmhe1 = 1) no ; the timer counter is cleared and the timer is started. lvi reset ;f prs = internal high-speed oscillation clock (8.4 mhz (max.)) (default) source: f prs (8.4 mhz (max.))/2 12 , where comparison value = 102: ? 50 ms timer starts (tmhe1 = 1). note a flowchart is shown on the next page. chapter 26 low-voltage detector user?s manual u18329ej4v0ud 697 figure 26-9. example of software processing after reset release (2/2) ? checking reset source yes no check reset source power-on-clear/external reset generated reset processing by watchdog timer reset processing by low-voltage detector yes wdtrf of resf register = 1? lvirf of resf register = 1? no user?s manual u18329ej4v0ud 698 chapter 27 option byte 27.1 functions of option bytes the flash memory at 0080h to 0084h of the 78k0/lf3 is an option byte area. when power is turned on or when the device is restarted from the reset status, the device automatically referenc es the option bytes and sets specified functions. when using the product, be sure to set t he following functions by using the option bytes. when the boot swap operation is used du ring self-programming, 0080h to 0084h are switched to 1080h to 1084h. therefore, set values that are the same as thos e of 0080h to 0084h to 1080h to 1084h in advance. caution be sure to set 00h to 0082h and 0083h (0082h/1082h and 0083h/1 083h when the boot swap function is used). (1) 0080h/1080h { internal low-speed oscillator operation ? can be stopped by software ? cannot be stopped { watchdog timer interval time setting { watchdog timer counter operation ? enabled counter operation ? disabled counter operation { watchdog timer window open period setting caution set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. (2) 0081h/1081h { selecting poc mode ? during 2.7 v/1.59 v poc mode operation (pocmode = 1) the device is in the reset state upon power application and until the supply voltage reaches 2.7 v (typ.). it is released from the reset state when the voltage exceeds 2.7 v (typ.). after that , poc is not detected at 2.7 v but is detect ed at 1.59 v (typ.). if the supply voltage rises to 1.8 v after power applicati on at a pace slower than 0.5 v/ms (min.), use of the 2.7 v/1.59 v poc mode is recommended. ? during 1.59 v poc mode operation (pocmode = 0) the device is in the reset state upon power application and until the suppl y voltage reaches 1.59 v (typ.). it is released from the reset state when the voltage exceeds 1.59 v (typ.). after that, poc is detected at 1.59 v (typ.), in the same mann er as on power application. caution pocmode can only be writte n by using a dedicated flash memo ry programmer. it cannot be set during self-programming or boot swap operat ion during self-progra mming (at this time, 1.59 v poc mode (default) is set). however, be cause the value of 1081h is copied to 0081h during the boot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h when the boot swap function is used. chapter 27 option byte user?s manual u18329ej4v0ud 699 (3) 0084h/1084h { on-chip debug operation control ? disabling on-chip debug operation ? enabling on-chip debug operation and erasing data of th e flash memory in case authentication of the on- chip debug security id fails ? enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security id fails caution to use the on-chip debug function, set 02h or 03h to 0084h. set a value that is the same as that of 0084h to 1084h because 0084h and 1084h ar e switched during th e boot operation. chapter 27 option byte user?s manual u18329ej4v0ud 700 27.2 format of option byte the format of the option byte is shown below. figure 27-1. format of option byte (1/2) address: 0080h/1080h note 7 6 5 4 3 2 1 0 0 window1 window0 wdton wdcs2 wdcs1 wdcs0 lsrosc window1 window0 watchdog timer window open period 0 0 25% 0 1 50% 1 0 75% 1 1 100% wdton operation control of watchdog ti mer counter/illegal access detection 0 counter operation disabled (counting stopped afte r reset), illegal access detection operation disabled 1 counter operation enabled (counting started after reset), illegal access detection operation enabled wdcs2 wdcs1 wdcs0 watc hdog timer overflow time 0 0 0 2 10 /f rl (3.88 ms) 0 0 1 2 11 /f rl (7.76 ms) 0 1 0 2 12 /f rl (15.52 ms) 0 1 1 2 13 /f rl (31.03 ms) 1 0 0 2 14 /f rl (62.06 ms) 1 0 1 2 15 /f rl (124.12 ms) 1 1 0 2 16 /f rl (248.24 ms) 1 1 1 2 17 /f rl (496.48 ms) lsrosc internal low-speed oscillator operation 0 can be stopped by software (stopped when 1 is written to bit 1 (lsrstop) of rcm register) 1 cannot be stopped (not stopped even if 1 is written to lsrstop bit) note set a value that is the same as that of 0080h to 1080h because 0080h and 1080h are switched during the boot swap operation. cautions 1. the combination of wdcs2 = wdcs1 = wdcs0 = 0 and window1 = window0 = 0 is prohibited. 2. the watchdog timer continues its operation during self-programming and eeprom emulation of the flash memory. during pr ocessing, the interrupt acknowledge time is delayed. set the overflow ti me and window size taking this delay into consideration. 3. if lsrosc = 0 (oscillation can be stopped by software), the count clock is not supplied to the watchdog timer in the halt and stop modes, rega rdless of the setting of bit 1 (lsrstop) of the internal oscillation mode register (rcm). when 8-bit timer h1 operates with the internal low-speed oscillation clo ck, the count clock is supplied to 8-bit timer h1 even in the halt/stop mode. 4. be sure to clear bit 7 to 0. remarks 1. f rl : internal low-speed oscillation clock frequency 2. ( ): f rl = 264 khz (max.) chapter 27 option byte user?s manual u18329ej4v0ud 701 figure 27-1. format of option byte (2/2) address: 0081h/1081h notes 1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 pocmode pocmode poc mode selection 0 1.59 v poc mode (default) 1 2.7 v/1.59 v poc mode notes 1. pocmode can only be written by using a dedicat ed flash memory programmer. it cannot be set during self-programming or boot swap operation during self-programming (at this time, 1.59 v poc mode (default) is set). however, because the val ue of 1081h is copied to 0081h during the boot swap operation, it is recommended to set a value that is the same as that of 0081h to 1081h when the boot swap function is used. 2. to change the setting for the poc mode, set the va lue to 0081h again after batch erasure (chip erasure) of the flash memory. the setting cannot be changed after t he memory of the specified block is erased. caution be sure to clea r bits 7 to 1 to ?0?. address: 0082h/1082h, 0083h/1083h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 note be sure to set 00h to 0082h and 0083h, as these addresses are reserved areas. also set 00h to 1082h and 1083h because 0082h and 0083h are switched with 1082h and 1083h when the boot swap operation is used. address: 0084h/1084h note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ocden1 ocden0 ocden1 ocden0 on-chip debug operation control 0 0 operation disabled 0 1 setting prohibited 1 0 operation enabled. does not erase data of the flash memory in case authentication of the on-chip debug security id fails. 1 1 operation enabled. erases data of the flash memory in case authentication of the on-chip debug security id fails. note to use the on-chip debug function, set 02h or 03h to 00 84h. set a value that is the same as that of 0084h to 1084h because 0084h and 1084h are switched during the boot swap operation. remark for the on-chip debug security id, see chapter 29 on-chip debug function . chapter 27 option byte user?s manual u18329ej4v0ud 702 here is an example of description of t he software for setting the option bytes. opt cseg at 0080h option: db 30h ; enables watchdog timer operation (illegal access detection operation), ; window open period of watchdog timer: 50%, ; overflow time of watchdog timer: 2 10 /f rl , ; internal low-speed oscillator can be stopped by software. db 00h ; 1.59 v poc mode db 00h ; reserved area db 00h ; reserved area db 00h ; on-chip debug operation disabled remark referencing of the option byte is performed during reset processing. for the reset processing timing, see chapter 24 reset function . user?s manual u18329ej4v0ud 703 chapter 28 flash memory the 78k0/lf3 incorporates t he flash memory to which a program can be written, erased, and overwritten while mounted on the board. 28.1 internal memory size switching register the internal memory capacity can be selected using t he internal memory size s witching register (ims). ims is set by an 8-bit memory manipulation instruction. reset signal generation sets ims to cfh. caution be sure to set each produc t to the values shown in table 28-1 after a reset release. figure 28-1. format of internal memo ry size switching register (ims) address: fff0h after reset: cfh r/w symbol 7 6 5 4 3 2 1 0 ims ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ram2 ram1 ram0 internal hi gh-speed ram capacity selection 0 0 0 768 bytes 1 1 0 1024 bytes other than above setting prohibited rom3 rom2 rom1 rom0 internal rom capacity selection 0 1 0 0 16 kb 0 1 1 0 24 kb 1 0 0 0 32 kb 1 1 0 0 48 kb 1 1 1 1 60 kb other than above setting prohibited table 28-1. internal memory si ze switching register settings flash memory versions (78k0/lf3) ims setting pd78f0471, 78f0481, 78f0491 04h pd78f0472, 78f0482, 78f0492 c6h pd78f0473, 78f0483, 78f0493 c8h pd78f0474, 78f0484, 78f0494 cch pd78f0475, 78f0485, 78f0495 cfh chapter 28 flash memory user?s manual u18329ej4v0ud 704 28.2 internal expansion ram size switching register the internal expansion ram capacity can be selected using the internal expansion ram size switching register (ixs). ixs is set by an 8-bit memory manipulation instruction. reset signal generation sets ixs to 0ch. caution be sure to set each produc t to the values shown in table 28-2 after a reset release. figure 28-2. format of internal expans ion ram size switching register (ixs) address: fff4h after reset: 0ch r/w symbol 7 6 5 4 3 2 1 0 ixs 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 ixram4 ixram3 ixram2 ixram1 ixram0 internal expansion ram capacity selection 0 1 1 0 0 0 byte 0 1 0 1 0 1024 bytes other than above setting prohibited table 28-2. internal expansion ram size switching register settings flash memory versions (78k0/lf3) ixs setting pd78f0471, 78f0481, 78f0491 pd78f0472, 78f0482, 78f0492 pd78f0473, 78f0483, 78f0493 0ch pd78f0474, 78f0484, 78f0494 pd78f0475, 78f0485, 78f0495 0ah chapter 28 flash memory user?s manual u18329ej4v0ud 705 28.3 writing with flash memory programmer data can be written to the flash memory on-board or o ff-board, by using a dedicated flash memory programmer. (1) on-board programming the contents of the flash memory can be rewritten after the 78k0/lf3 has been mounted on the target system. the connectors that connect the dedicated flash memo ry programmer must be mounted on the target system. (2) off-board programming data can be written to the flash memory with a dedica ted program adapter (fa series) before the 78k0/lf3 is mounted on the target system. remark the fa series is a product of na ito densei machida mfg. co., ltd. table 28-3. wiring between 78k0/lf3 a nd dedicated flash memory programmer pin configuration of dedicated flash memory programmer with csi10 with uart6 signal name i/o pin function pin name pin no. pin name pin no. si/rxd input receive signal so10/txd0/p13 78 txd6/seg18/p112 36 so/txd output transmit signal si10/rxd0/p12 79 rxd6/seg19/p113 35 sck output transfer clock sck10/p11 80 ? ? clk output clock to 78k0/lf3 ? note 1 ? note 2 note 2 /reset output reset signal reset 14 reset 14 flmd0 output mode signal flmd0 17 flmd0 17 v dd 22 v dd 22 v dd note 3 v dd note 3 v dd i/o v dd voltage generation/ power monitoring av ref note 4 59 av ref note 4 59 v ss 21 v ss 21 v ss note 3 v ss note 3 gnd ? ground av ss note 4 60 av ss note 4 60 notes 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. only the x1 clock (f x ), external main system clock (f exclk ), or internal high-speed oscillation clock (f rh ) can be used when uart6 is used. when using the clo ck output of the dedicated fl ash memory programmer, connect clk of the pg-fp5 or fl-pr5 to exclk/x2/p122 (pin number 18). 3. pd78f047x only. 4. pd78f048x and 78f049x only. caution only the bottom side pins (pin numbers 35 and 36) correspond to the uart6 pins (rxd6 and txd6) when writing by a flash memory programmer. wr iting cannot be performed by the top side pins (pin numbers 76 and 75). chapter 28 flash memory user?s manual u18329ej4v0ud 706 examples of the recommended connection when using the adapter for flash memory writing are shown below. figure 28-3. example of wiring ad apter for flash memory writing in 3-wire serial i/o (csi10) mode gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gnd vdd vdd2 writer interface si so sck clk /reset flmd0 v dd (2.7 to 5.5 v) chapter 28 flash memory user?s manual u18329ej4v0ud 707 figure 28-4. example of wiri ng adapter for flash memory wr iting in uart (uart6) mode gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gnd vdd vdd2 v dd (2.7 to 5.5 v) writer interface si so sck clk note /reset flmd0 note note the above figure illustrates an example of wiring when using the clock output from the pg-fp5 or fl-pr5. chapter 28 flash memory user?s manual u18329ej4v0ud 708 28.4 programming environment the environment required for writing a program to the fl ash memory of the 78k0/lf 3 is illustrated below. figure 28-5. environment for wr iting program to flash memory rs-232c usb 78k0/lf3 flmd0 v dd v ss reset csi10/uart6 host machine dedicated flash memory programmer pg-fp5 start power pass busy ng a host machine that controls the dedicated flash memory programmer is necessary. to interface between the dedicated flash memory pr ogrammer and the 78k0/lf3, cs i10 or uart6 is used for manipulation such as writing and erasi ng. to write the flash memory off- board, a dedicated program adapter (fa series) is necessary. 28.5 communication mode communication between the dedicated flash memory progr ammer and the 78k0/lf3 is established by serial communication via csi10 or uart6 of the 78k0/lf3. (1) csi10 transfer rate: 2.4 khz to 2.5 mhz figure 28-6. communication with dedica ted flash memory programmer (csi10) v dd /av ref v ss /av ss reset so10 si10 sck10 flmd0 flmd0 v dd gnd /reset si/rxd so/txd sck dedicated flash memory programmer 78k0/lf3 pg-fp5 start power pass busy ng chapter 28 flash memory user?s manual u18329ej4v0ud 709 (2) uart6 transfer rate: 115200 bps figure 28-7. communication with dedica ted flash memory programmer (uart6) v dd /av ref v ss /av ss reset txd6 rxd6 v dd gnd /reset si/rxd so/txd exclk note clk note dedicated flash memory programmer flmd0 flmd0 78k0/lf3 pg-fp5 start power pass busy ng note the above figure illustrates an example of wiring when using the clock output from the pg-fp5 or fl-pr5. caution only the bottom side pins (pin numbers 35 and 36) correspond to the uart6 pins (rxd6 and txd6) when writing by a flash memory programmer. writing cannot be performed by the top side pins (pin numbers 76 and 75). the dedicated flash memory programmer generates the following signals for the 78k0/lf3. for details, refer to the user?s manual for the pg-fp5 or fl-pr5. table 28-4. pin connection dedicated flash memory programmer 78k0/lf3 connection signal name i/o pin function pin name csi10 uart6 flmd0 output mode signal flmd0 v dd i/o v dd voltage generation/power monitoring v dd , av ref note 3 gnd ? ground v ss , av ss note 3 clk output clock output to 78k0/lf3 note 1 note 2 { note 1 /reset output reset signal reset si/rxd input receive signal so10 or txd6 so/txd output transmit signal si10 or rxd6 sck output transfer clock sck10 notes 1. only the x1 clock (f x ), external main system clock (f exclk ), or internal high-speed oscillation clock (f rh ) can be used when uart6 is used. when using the clo ck output of the dedicated fl ash memory programmer, connect clk of the pg-fp5 or fl-pr5 to exclk/x2/p122. 2. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 3. pd78f048x and 78f049x only. remark : be sure to connect the pin. { : the pin does not have to be connected if the signal is generated on the target board. : the pin does not have to be connected. chapter 28 flash memory user?s manual u18329ej4v0ud 710 28.6 connection of pins on board to write the flash memory on-board, connectors that connect the dedicat ed flash memory programmer must be provided on the target system. first provide a function that selects the no rmal operation mode or flash memory programming mode on the board. when the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after re set. therefore, if the external device does not recognize t he state immediately after reset, the pins must be handled as described below. 28.6.1 flmd0 pin in the normal operation mode, 0 v is input to the flmd 0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. an flmd0 pin connection example is shown below. figure 28-8. flmd0 pin connection example 78k0/lf3 flmd0 10 k (recommended) dedicated flash memory programmer connection pin 28.6.2 serial interface pins the pins used by each serial interface are listed below. table 28-5. pins used by each serial interface serial interface pins used csi10 so10, si10, sck10 uart6 txd6, rxd6 to connect the dedicated flash memory programmer to the pins of a serial interface that is connected to another device on the board, care must be exer cised so that signals do not collide or that the other device does not malfunction. chapter 28 flash memory user?s manual u18329ej4v0ud 711 (1) signal collision if the dedicated flash memory programmer (output) is connec ted to a pin (input) of a serial interface connected to another device (output), signal collision ta kes place. to avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. figure 28-9. signal collision (i nput pin of serial interface) input pin signal collision dedicated flash memory programmer connection pin other device output pin in the flash memory programming mode, the signal output by the device collides with the signal sent from the dedicated flash programmer. therefore, isolate the signal of the other device. 78k0/lf3 (2) malfunction of other device if the dedicated flash memory programmer (output or input) is connected to a pin (input or output) of a serial interface connected to another device (input), a signal ma y be output to the other devic e, causing the device to malfunction. to avoid this malfunction, is olate the connection with the other device. figure 28-10. malfunction of other device pin dedicated flash memory programmer connection pin other device input pin if the signal output by the 78k0/lf3 in the flash memory programming mode affects the other device, isolate the signal of the other device. pin dedicated flash memory programmer connection pin other device input pin if the signal output by the dedicated flash memory programmer in the flash memory programming mode affects the other device, isolate the signal of the other device. 78k0/lf3 78k0/lf3 chapter 28 flash memory user?s manual u18329ej4v0ud 712 28.6.3 reset pin if the reset signal of the dedicated flash memory programm er is connected to the reset pin that is connected to the reset signal generator on the board, signal collision takes pl ace. to prevent this col lision, isolate the connection with the reset signal generator. if the reset signal is input from the user system whil e the flash memory programming mode is set, the flash memory will not be correctly programmed. do not input any signal other than the reset signal of the dedicated flash memory programmer. figure 28-11. signal collision (reset pin) reset dedicated flash memory programmer connection signal reset signal generator signal collision output pin in the flash memory programming mode, the signal output by the reset signal generator collides with the signal output by the dedicated flash memory programmer. therefore, isolate the signal of the reset signal generator. 78k0/lf3 28.6.4 port pins when the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately afte r reset. if external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to v dd or v ss via a resistor. 28.6.5 regc pin connect the regc pin to gnd via a capacitor (0.47 to 1 f: recommended) in the same manner as during normal operation. 28.6.6 other signal pins connect x1 and x2 in the same status as in t he normal operation mode when using the on-board clock. to input the operating clock from the dedicated flash me mory programmer, however, connect clk of the pg-fp5 or fl-pr5 to exclk/x2/p122. cautions 1. only the internal high-speed oscillation clock (f rh ) can be used when csi10 is used. 2. the x1 clock (f x ), external main system clock (f exclk ), or internal high-s peed oscillation clock (f rh ) can be used when uart6 is used. 28.6.7 power supply to use the supply voltage output of the flash memory programmer, connect the v dd pin to v dd of the flash memory programmer, and the v ss pin to gnd of the flash memory programmer. to use the on-board supply voltage, connect in compliance with the normal operation mode. however, be sure to connect the v dd and v ss pins to v dd and gnd of the flash memory programmer to use the power monitor function with the flash memory progra mmer, even when using the on-board supply voltage. supply the same other power supplies (av ref and av ss ) as those in the normal operation mode. chapter 28 flash memory user?s manual u18329ej4v0ud 713 28.7 programming method 28.7.1 controlling flash memory the following figure illustrates the proc edure to manipulate the flash memory. figure 28-12. flash memory manipulation procedure start selecting communication mode manipulate flash memory end? yes flmd0 pulse supply no end flash memory programming mode is set 28.7.2 flash memory programming mode to rewrite the contents of t he flash memory by using the dedicated flas h memory programmer, set the 78k0/lf3 in the flash memory programming mode. to set the mode, set the flmd0 pin to v dd and clear the reset signal. change the mode by using a jumper when writing the flash memory on-board. figure 28-13. flash memory programming mode v dd reset 5.5 v 0 v v dd 0 v flash memory programming mode flmd0 flmd0 pulse v dd 0 v table 28-6. relationship between flmd0 pi n and operation mode after reset release flmd0 operation mode 0 normal operation mode v dd flash memory programming mode chapter 28 flash memory user?s manual u18329ej4v0ud 714 28.7.3 selecting communication mode in the 78k0/lf3, a communication mode is selected by inputting pulses to the flmd0 pin after the dedicated flash memory programming mode is entered. these flmd0 puls es are generated by the flash memory programmer. the following table shows the relationship between the number of pulses and communication modes. table 28-7. communication modes standard setting note 1 communication mode port speed frequency multiply rate pins used peripheral clock number of flmd0 pulses uart-ext-osc f x 0 uart-ext-fp5clk 2 m to 10 mhz note 2 f exclk 3 uart (uart6) uart-internal-osc 115,200 bps note 3 ? txd6, rxd6 f rh 5 3-wire serial i/o (csi10) csi-internal-osc 2.4 khz to 2.5 mhz ? 1.0 so10, si10, sck10 f rh 8 notes 1. selection items for standard settings on gu i of the flash memory programmer. 2. the possible setting range differs depending on the voltage. for details, see chapter 31 electrical specifications (standard products) . 3. because factors other than the baud rate error, such as the signal waveform slew, also affect uart communication, thoroughly evaluate the slew as well as the baud rate error. caution when uart6 is select ed, the receive clock is calculated b ased on the reset command sent from the dedicated flash memory programmer afte r the flmd0 pulse h as been received. remark f x : x1 clock f exclk : external main system clock f rh : internal high-speed oscillation clock chapter 28 flash memory user?s manual u18329ej4v0ud 715 28.7.4 communication commands the 78k0/lf3 communicates with the de dicated flash memory programmer by using commands. the signals sent from the flash memory programmer to the 78k0/lf3 are ca lled commands, and the signals sent from the 78k0/lf3 to the dedicated flash memory programmer are called response. figure 28-14. communication commands command response 78k0/lf3 dedicated flash memory programmer pg-fp5 start power pass busy ng the flash memory control commands of the 78k0/lf3 are listed in the t able below. all these commands are issued from the programmer and the 78k0/lf3 perform pr ocessing corresponding to the respective commands. table 28-8. flash memory control commands classification command name function verify verify compares the contents of a specified area of the flash memory with data transmitted from the programmer. chip erase erases the entire flash memory. erase block erase erases a specified area in the flash memory. blank check block blank check checks if a specified block in the flash memory has been correctly erased. write programming writes data to a sp ecified area in the flash memory. status gets the current operating status (status data). silicon signature gets 78k0/lx3 information (such as the part number and flash memory configuration). version get gets the 78k0/lx3 version and firmware version. getting information checksum gets the checksum data for a specified area. security security set sets security information. reset used to detect synchronization status of communication. others oscillating frequency set specifies an oscillation frequency. the 78k0/lf3 return a response for the command issued by the dedicated flash memory programmer. the response names sent from t he 78k0/lf3 are listed below. table 28-9. response names response name function ack acknowledges command/data. nak acknowledges illegal command/data. chapter 28 flash memory user?s manual u18329ej4v0ud 716 28.8 security settings the 78k0/lf3 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. the operations shown below can be performed using the se curity set command. the security setting is valid when the programming mode is set next. ? disabling batch erase (chip erase) execution of the block erase and batch erase (chip eras e) commands for entire blocks in the flash memory is prohibited by this setting during on-board/off-board prog ramming. once execution of the batch erase (chip erase) command is prohibited, all of the prohibition settings (including prohibition of batch erase (chip erase)) can no longer be cancelled. caution after the security setting for the batch erase is set, erasure ca nnot be performed for the device. in addition, even if a write command is executed, data different from that which has already been written to the flash memory cannot be wr itten, because th e erase command is disabled. ? disabling block erase execution of the block erase command fo r a specific block in the flash memo ry is prohibited during on-board/off- board programming. however, blocks can be erased by means of self programming. ? disabling write execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on- board/off-board programming. however, blocks can be written by means of self programming. ? disabling rewriting boot cluster 0 execution of the batch erase (chi p erase) command, block erase command, and write command on boot cluster 0 (0000h to 0fffh) in the flash memo ry is prohibited by this setting. caution if a security setting that rewrites boot cluster 0 has been applied, boot cl uster 0 of that device will not be rewritten. the batch erase (chip erase), block eras e, write commands, and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. security can be set by on-board/off-board programming and self programming. each security setting can be used in combination. prohibition of erasing blocks and wr iting is cleared by ex ecuting the batch erase (chip erase) command. table 28-10 shows the relationship between the erase and write commands when the 78k0/lf3 security function is enabled. chapter 28 flash memory user?s manual u18329ej4v0ud 717 table 28-10. relationship between enabling security function and command (1) during on-board/off-board programming executed command valid security batch erase (chip erase) block erase write prohibition of batch erase (c hip erase) cannot be erased in batch can be performed note . prohibition of block erase can be performed. prohibition of writing can be erased in batch. blocks cannot be erased. cannot be performed. prohibition of rewriting boot cluster 0 cannot be erased in batch boot cluster 0 cannot be erased. boot cluster 0 cannot be written. note confirm that no data has been wri tten to the write area. because data cannot be erased after batch erase (chip erase) is prohibited, do not wr ite data if the data has not been erased. (2) during self programming executed command valid security block erase write prohibition of batch erase (chip erase) prohibition of block erase prohibition of writing blocks can be erased. can be performed. prohibition of rewriting boot cluster 0 boot cluster 0 cannot be erased. boot cluster 0 cannot be written. table 28-11 shows how to perform security settings in each programming mode. table 28-11. setting security in each programming mode (1) on-board/off-board programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command prohibition of rewriting boot cluster 0 set via gui of dedicated flash memory programmer, etc. cannot be disabled after set. (2) self programming security security setting how to disable security setting prohibition of batch erase (chip er ase) cannot be disabled after set. prohibition of block erase prohibition of writing execute batch erase (chip erase) command during on-board/off-board programming (cannot be disabled during self programming) prohibition of rewriting boot cluster 0 set by using information library. cannot be disabled after set. chapter 28 flash memory user?s manual u18329ej4v0ud 718 28.9 processing time for each command when pg-fp5 is used (reference) the following table shows the processing time for eac h command (reference) when the pg-fp5 is used as a dedicated flash memory programmer. table 28-12. processing time for each command when pg-fp5 is used (reference) (1/3) (1) pd78f0471, 78f0481, 78f0491 (produ cts with internal rom: 16 kb) port:uart-ext-osc (x1 clock (f x )) speed:115200 bps port: uart-ext-fp5clk (external main system clock (f exclk )), speed:115200 bps command of pg-fp5 port: csi-internal-osc (internal high- speed oscillation clock (f rh )) speed: 2.5 mhz port: uart-internal-osc (internal high-speed oscillation clock (f rh )) speed: 115200 bps frequency: 2.0 mhz frequency: 10 mhz frequency: 2.0 mhz frequency: 10 mhz signature 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) blankcheck 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) erase 1.5 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) program 3 s (typ.) 4 s (typ.) 4 s (t yp.) 4 s (typ.) 4 s (typ.) 4 s (typ.) verify 2 s (typ.) 3 s (typ.) 3 s (typ.) 3 s (typ.) 3 s (typ.) 3 s (typ.) e.p.v 3.5 s (typ.) 4 s (typ.) 4 s (typ.) 4 s (typ.) 4 s (typ.) 4 s (typ.) checksum 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) security 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) (2) pd78f0472, 78f0482, 78f0492 (pr oducts with internal rom: 24 kb) port:uart-ext-osc (x1 clock (f x )) speed:115200 bps port:uart-ext-fp5clk (external main system clock (f exclk )) speed:115200 bps command of pg-fp5 port: csi-internal-osc (internal high- speed oscillation clock (f rh )) speed: 2.5 mhz port: uart-internal-osc (internal high-speed oscillation clock (f rh )) speed: 115200 bps frequency: 2.0 mhz frequency: 10 mhz frequency: 2.0 mhz frequency: 10 mhz signature 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) blankcheck 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) erase 1.5 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) program 4 s (typ.) 5.5 s (typ.) 5.5 s (typ.) 5.5 s (typ.) 5.5 s (typ.) 5.5 s (typ.) verify 2.5 s (typ.) 4 s (typ.) 4 s (typ.) 4 s (typ.) 4 s (typ.) 4 s (typ.) e.p.v 4.5 s (typ.) 5.5 s (typ.) 5.5 s (typ.) 5.5 s (typ.) 5.5 s (typ.) 5.5 s (typ.) checksum 1.5 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) security 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) caution when executing boot swapping , do not use the e.p.v. command wi th the dedicated flash memory programmer. chapter 28 flash memory user?s manual u18329ej4v0ud 719 table 28-12. processing time for each command when pg-fp5 is used (reference) (2/3) (3) pd78f0473, 78f0483, 78f0493 (pr oducts with internal rom: 32 kb) port:uart-ext-osc (x1 clock (f x )) speed:115200 bps port:uart-ext-fp5clk (external main system clock (f exclk )) speed:115200 bps command of pg-fp5 port: csi-internal-osc (internal high- speed oscillation clock (f rh )) speed: 2.5 mhz port: uart-internal-osc (internal high-speed oscillation clock (f rh )) speed: 115200 bps frequency: 2.0 mhz frequency: 10 mhz frequency: 2.0 mhz frequency: 10 mhz signature 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) blankcheck 1.5 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) erase 1.5 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) program 4.5 s (typ.) 6.5 s (typ.) 6.5 s (typ.) 6.5 s (typ.) 6.5 s (typ.) 6.5 s (typ.) verify 2.5 s (typ.) 5 s (typ.) 5 s (typ.) 5 s (typ.) 5 s (typ.) 5 s (typ.) e.p.v 5.5 s (typ.) 7 s (typ.) 7 s (typ.) 7 s (typ.) 7 s (typ.) 7 s (typ.) checksum 1.5 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) security 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) (4) pd78f0474, 78f0484, 78f0494 (pr oducts with internal rom: 48 kb) port:uart-ext-osc (x1 clock (f x )) speed:115200 bps port:uart-ext-fp5clk (external main system clock (f exclk )) speed:115200 bps command of pg-fp5 port: csi-internal-osc (internal high- speed oscillation clock (f rh )) speed: 2.5 mhz port: uart-internal-osc (internal high-speed oscillation clock (f rh )) speed: 115200 bps frequency: 2.0 mhz frequency: 10 mhz frequency: 2.0 mhz frequency: 10 mhz signature 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) blankcheck 1 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) erase 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) program 6.5 s (typ.) 9.5 s (typ.) 9.5 s (typ.) 9.5 s (typ.) 9.5 s (typ.) 9.5 s (typ.) verify 3.5 s (typ.) 7 s (typ.) 7 s (typ.) 7 s (typ.) 7 s (typ.) 7 s (typ.) e.p.v 7.5 s (typ.) 10 s (typ.) 10 s (typ.) 10 s (typ.) 10 s (typ.) 10 s (typ.) checksum 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) security 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) caution when executing boot swapping , do not use the e.p.v. command wi th the dedicated flash memory programmer. chapter 28 flash memory user?s manual u18329ej4v0ud 720 table 28-12. processing time for each command when pg-fp5 is used (reference) (3/3) (5) pd78f0475, 78f0485, 78f0495 (pr oducts with internal rom: 60 kb) port:uart-ext-osc (x1 clock (f x )) speed:115200 bps port:uart-ext-fp5clk (external main system clock (f exclk )) speed:115200 bps command of pg-fp5 port: csi-internal-osc (internal high- speed oscillation clock (f rh )) speed: 2.5 mhz port: uart-internal-osc (internal high-speed oscillation clock (f rh )) speed: 115200 bps frequency: 2.0 mhz frequency: 10 mhz frequency: 2.0 mhz frequency: 10 mhz signature 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) blankcheck 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) erase 2 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) program 8 s (typ.) 12 s (typ.) 12 s (typ.) 11.5 s (typ.) 12 s (typ.) 11.5 s (typ.) verify 4.5 s (typ.) 8.5 s (typ.) 8.5 s (typ.) 8.5 s (typ.) 8.5 s (typ.) 8.5 s (typ.) e.p.v 9 s (typ.) 12.5 s (typ.) 12.5 s (typ.) 12.5 s (typ.) 12.5 s (typ.) 12.5 s (typ.) checksum 2 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) 1.5 s (typ.) security 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) 1 s (typ.) caution when executing boot swapping , do not use the e.p.v. command wi th the dedicated flash memory programmer. chapter 28 flash memory user?s manual u18329ej4v0ud 721 28.10 flash memory programming by self-programming the 78k0/lf3 microcontrollers support a self-programming function that can be used to rewrite the flash memory via a user program. because this function allows a user application to rewrite the flas h memory by using the self- programming library, it can be used to upgrade the program in the field. if an interrupt occurs during self-programming, self -programming can be temporarily stopped and interrupt servicing can be executed. to execute interrupt servicing, restore the normal operation mode after self-programming has been stopped, and execute t he ei instruction. after the self-pr ogramming mode is later restored, self- programming can be resumed. cautions 1. the self-programmi ng function cannot be used when th e cpu operates with the subsystem clock. 2. oscillation of the internal high-speed oscillator is started during self programming, regardless of the setting of the rstop flag (b it 0 of the internal oscillation mode register (rcm)). oscillation of the internal high-speed oscillator cannot be stopped even if the stop instruction is executed. 3. input a high level to the fl md0 pin during self-programming. 4. be sure to execute the di instru ction before starting self-programming. the self-programming function checks the interrupt request flags (if0l, if0h, if1l, and if1h). if an interrupt request is gene rated, self-programming is stopped. 5. self-programming is also st opped by an interrupt request that is not masked even in the di status. to prevent this, mask the interrupt by using the interrupt mask flag registers (mk0l, mk0h, mk1l, and mk1h). 6. allocate the entry program for self-programming in th e 0000h to 7fffh. figure 28-15. operation mode and memory map for se lf-programming ( pd78f0475) normal mode internal high- speed ram internal high- speed ram self-programming mode flash memory (user area) flash memory (user area) flash memory control firmware rom flash memory control firmware rom instructions can be fetched from user area. instructions can be fetched from user area and firmware rom. internal expansion ram internal expansion ram sfr disable accessing disable accessing sfr reserved reserved enable accessing ffffh fb00h faffh ff00h feffh f800h f7ffh f000h efffh 8000h 7fffh 0000h ffffh fb00h faffh ff00h feffh f800h f7ffh f000h efffh 8000h 7fffh 0000h f400h f3ffh f400h f3ffh chapter 28 flash memory user?s manual u18329ej4v0ud 722 the following figure illustrates a flow of rewriting the fl ash memory by using a self programming sample library. figure 28-16. flow of self programming (rewriting flash memory) remark for details of the self programming library, refer to 78k0 microcontroller se lf-programming library type01 user?s manual (u18274e) . flashblockblankchec k flashenv flashblockerase flashwordwrite settin g operatin g normal completion? flashstart yes no flashblockverify no start of self programming checkflmd normal completion? yes flashblockerase flashwordwrite flashblockverify end of self programming normal completion? flashend normal completion? error no yes chapter 28 flash memory user?s manual u18329ej4v0ud 723 the following table shows the processing time and interrupt response time for the self-programming library. table 28-13. processing time and interrupt acknowledgment (1/4) (when normal model library and entry ram are a llocated outside short direct addressing range) processing time (unit: s) rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note function mcs = 0 (internal high-speed oscillation clock) mcs = 1 (high-speed system clock) mcs = 1 (high-speed system clock) interrupt acknowledgment self programming start function 34/f cpu 34/f cpu 34/f cpu disabled self programming end function 34/f cpu 34/f cpu 34/f cpu disabled initialize function 55/f cpu +1140 55/f cpu +1140 55/f cpu +1912 disabled block erase function 179/f cpu +353193 179/f cpu +353193 179/f cpu +353965 enabled word write function 333/f cpu +1154+ 2142w 333/f cpu +1154+ 2142w 333/f cpu +1927+ 2142w enabled block verify function 179/f cpu +25596 179/f cpu +25596 179/f cpu +26369 enabled block blank check function 179/f cpu +12805 179/f cpu +12805 179/f cpu +13578 enabled option value: 03h 180/f cpu +1065 180/f cpu +1065 180/f cpu +1838 disabled option value: 04h 190/f cpu +1056 190/f cpu +1056 190/f cpu +1829 disabled get information function option value: 05h 350/f cpu +1041 350/f cpu +1041 350/f cpu +1813 disabled set information function 80/f cpu +753218 80/f cpu +753218 80/f cpu +753990 enabled mode check function 36/f cpu +952 36/f cpu +952 36/f cpu +1724 disabled eeprom write function 333/f cpu +1297+ 2286w 333/f cpu +1297+ 2286w 333/f cpu +2069+ 2286w enabled note this is the function processing time when the function is executed immediately after the self programming start function has been executed. the processing time afte r a function other than the self programming start function has been executed is the same as that of rstop = 0. remark rstop: bit 0 of the internal oscillation mode register (rcm) rsts: bit 7 of rcm mcs: bit 1 of main clock mode register (mcm) f cpu : cpu clock frequency w: number of words to be written (1 word = 4 bytes) chapter 28 flash memory user?s manual u18329ej4v0ud 724 table 28-13. processing time and interrupt acknowledgment (2/4) (when normal model library and entry ram are allo cated within short direct addressing range) processing time (unit: s) rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note function mcs = 0 (internal high-speed oscillation clock) mcs = 1 (high-speed system clock) mcs = 1 (high-speed system clock) interrupt acknowledgment self programming start function 34/f cpu 34/f cpu 34/f cpu disabled self programming end function 34/f cpu 34/f cpu 34/f cpu disabled initialize function 55/f cpu +462 55/f cpu +462 55/f cpu +473 disabled block erase function 179/f cpu +352516 179/f cpu +352516 179/f cpu +352528 enabled word write function 333/f cpu +477+ 2142w 333/f cpu +477+ 2142w 333/f cpu +488+ 2142w enabled block verify function 179/f cpu +24918 179/f cpu +24918 179/f cpu +24930 enabled block blank check function 179/f cpu +12128 179/f cpu +12128 179/f cpu +12139 enabled option value: 03h 180/f cpu +388 180/f cpu +388 180/f cpu +399 disabled option value: 04h 190/f cpu +378 190/f cpu +378 190/f cpu +390 disabled get information function option value: 05h 350/f cpu +363 350/f cpu +363 350/f cpu +375 disabled set information function 80/f cpu +752540 80/f cpu +752540 80/f cpu +753654 enabled mode check function 36/f cpu +274 36/f cpu +274 36/f cpu +286 disabled eeprom write function 333/f cpu +619+ 2286w 333/f cpu +619+ 2286w 333/f cpu +630+ 2286w enabled note this is the function processing time when the function is executed immediately after the self programming start function has been executed. the processing time afte r a function other than the self programming start function has been executed is the same as that of rstop = 0. remark rstop: bit 0 of the internal oscillation mode register (rcm) rsts: bit 7 of rcm mcs: bit 1 of main clock mode register (mcm) f cpu : cpu clock frequency w: number of words to be written (1 word = 4 bytes) chapter 28 flash memory user?s manual u18329ej4v0ud 725 table 28-13. processing time and interrupt acknowledgment (3/4) (when static model library and entry ram are a llocated outside short direct addressing range) processing time (unit: s) rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note function mcs = 0 (cpu operates with internal high-speed oscillation clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 1 (cpu operates with high-speed system clock) interrupt acknowledgment self programming start function 34/f cpu 34/f cpu 34/f cpu disabled self programming end function 34/f cpu 34/f cpu 34/f cpu disabled initialize function 55/f cpu +1140 55/f cpu +1140 55/f cpu +1912 disabled block erase function 136/f cpu +353193 136/f cpu +353193 136/f cpu +353965 enabled word write function 272/f cpu +1154+ 2142w 272/f cpu +1154+ 2142w 272/f cpu +1927+ 2142w enabled block verify function 136/f cpu +25596 136/f cpu +25596 136/f cpu +26369 enabled block blank check function 136/f cpu +12805 136/f cpu +12805 136/f cpu +13578 enabled option value: 03h 134/f cpu +1065 134/f cpu +1065 134/f cpu +1838 disabled option value: 04h 144/f cpu +1056 144/f cpu +1056 144/f cpu +1829 disabled get information function option value: 05h 304/f cpu +1041 304/f cpu +1041 304/f cpu +1813 disabled set information function 72/f cpu +753218 72/f cpu +753218 72/f cpu +753990 enabled mode check function 30/f cpu +952 30/f cpu +952 30/f cpu +1724 disabled eeprom write function 268/f cpu +1297+ 2286w 268/f cpu +1297+ 2286w 268/f cpu +2069+ 2286w enabled note this is the function processing time when the function is executed immediately after the self programming start function has been executed. the processing time afte r a function other than the self programming start function has been executed is the same as that of rstop = 0. remark rstop: bit 0 of the internal oscillation mode register (rcm) rsts: bit 7 of rcm mcs: bit 1 of main clock mode register (mcm) f cpu : cpu clock frequency w: number of words to be written (1 word = 4 bytes) chapter 28 flash memory user?s manual u18329ej4v0ud 726 table 28-13. processing time and interrupt acknowledgment (4/4) (when static model library and entry ram are a llocated within short direct addressing range) processing time (unit: s) rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note function name mcs = 0 (cpu operates with internal high-speed oscillation clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 1 (cpu operates with high-speed system clock) interrupt acknowledgment self programming start function 34/f cpu 34/f cpu 34/f cpu disabled self programming end function 34/f cpu 34/f cpu 34/f cpu disabled initialize function 55/f cpu +462 55/f cpu +462 55/f cpu +473 disabled block erase function 136/f cpu +352516 136/f cpu +352516 136/f cpu +352528 enabled word write function 272/f cpu +477+ 2142w 272/f cpu +477+ 2142w 272/f cpu +488+ 2142w enabled block verify function 136/f cpu +24918 136/f cpu +24918 136/f cpu +24930 enabled block blank check function 136/f cpu +12128 136/f cpu +12128 136/f cpu +12139 enabled option value: 03h 134/f cpu +388 134/f cpu +388 134/f cpu +399 disabled option value: 04h 144/f cpu +378 144/f cpu +378 144/f cpu +390 disabled get information function option value: 05h 304/f cpu +363 304/f cpu +363 304/f cpu +375 disabled set information function 72/f cpu +752540 72/f cpu +752540 72/f cpu +753654 enabled mode check function 30/f cpu +274 30/f cpu +274 30/f cpu +286 disabled eeprom write function 268/f cpu +619+ 2286w 268/f cpu +619+ 2286w 268/f cpu +630+ 2286w enabled note this is the function processing time when the function is executed immediately after the self programming start function has been executed. the processing time afte r a function other than the self programming start function has been executed is the same as that of rstop = 0. remark rstop: bit 0 of the internal oscillation mode register (rcm) rsts: bit 7 of rcm mcs: bit 1 of main clock mode register (mcm) f cpu : cpu clock frequency w: number of words to be written (1 word = 4 bytes) chapter 28 flash memory user?s manual u18329ej4v0ud 727 table 28-14. interrupt response time (library for normal model) (1/2) interrupt response time (unit: s) when entry ram is allocated outside short direct addressing range when entry ram is allocated within short direct addressing range rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note function name mcs = 0 (cpu operates with internal high-speed oscillation clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 0 (cpu operates with internal high-speed oscillation clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 1 (cpu operates with high-speed system clock) block erase function 179/f cpu +1269 179/f cpu +1269 179/f cpu +1912 179/f cpu +703 179/f cpu +703 179/f cpu +713 word write function 333/f cpu +1098 333/f cpu +1098 333/f cpu +1742 333/f cpu +533 333/f cpu +533 333/f cpu +543 block verify function 179/f cpu +1013 179/f cpu +1013 179/f cpu +1656 179/f cpu +448 179/f cpu +448 179/f cpu +456 block blank check function 179/f cpu +993 179/f cpu +993 179/f cpu +1637 179/f cpu +428 179/f cpu +428 179/f cpu +438 set information function 80/f cpu +833 80/f cpu +833 80/f cpu +1477 80/f cpu +346 80/f cpu +346 80/f cpu +346 eeprom write function 333/f cpu +1107 333/f cpu +1107 333/f cpu +1751 333/f cpu +542 333/f cpu +542 333/f cpu +5 52 note this is the function processing time when the function is executed immediately after the self programming start function has been executed. the processing time afte r a function other than the self programming start function has been executed is the same as that of rstop = 0. remark rstop: bit 0 of the internal oscillation mode register (rcm) rsts: bit 7 of rcm mcs: bit 1 of main clock mode register (mcm) f cpu : cpu clock frequency w: number of words to be written (1 word = 4 bytes) chapter 28 flash memory user?s manual u18329ej4v0ud 728 table 28-14. interrupt response time (library for static model) (2/2) interrupt response time ( s) when entry ram is allocated outside short direct addressing range when entry ram is allocated within short direct addressing range rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note rstop = 0 and rsts = 1 (during stable operation of internal high-speed oscillator) rstop = 1 (internal high-speed oscillator stopped) note function name mcs = 0 (cpu operates with internal high-speed oscillation clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 0 (cpu operates with internal high-speed oscillation clock) mcs = 1 (cpu operates with high-speed system clock) mcs = 1 (cpu operates with high-speed system clock) block erase function 136/f cpu +1269 136/f cpu +1269 136/f cpu +1912 136/f cpu +703 136/f cpu +703 136/f cpu +713 word write function 272/f cpu +1098 272/f cpu +1098 272/f cpu +1742 272/f cpu +533 272/f cpu +533 272/f cpu + 54 3 block verify function 136/f cpu +1013 136/f cpu +1013 136/f cpu +1656 136/f cpu +448 136/f cpu +448 136/f cpu +456 block blank check function 136/f cpu +993 136/f cpu +993 136/f cpu +1637 136/f cpu +428 136/f cpu +428 136/f cpu +438 set information function 72/f cpu +833 72/f cpu +833 72/f cpu +1477 72/f cpu +346 72/f cpu +346 72/f cpu +346 eeprom write function 268/f cpu +1107 268/f cpu +1107 268/f cpu +1751 268/f cpu +542 268/f cpu +542 268/f cpu +5 52 note this is the function processing time when the function is executed immediately after the self programming start function has been executed. the processing time afte r a function other than the self programming start function has been executed is the same as that of rstop = 0. remark rstop: bit 0 of the internal oscillation mode register (rcm) rsts: bit 7 of rcm mcs: bit 1 of main clock mode register (mcm) f cpu : cpu clock frequency w: number of words to be written (1 word = 4 bytes) chapter 28 flash memory user?s manual u18329ej4v0ud 729 28.10.1 boot swap function if rewriting the boot area has failed dur ing self-programming due to a power fa ilure or some other cause, the data in the boot area may be lost and the pr ogram may not be restarted by resetting. the boot swap function is used to avoid this problem. before erasing boot cluster 0 note , which is a boot program area, by self-p rogramming, write a new boot program to boot cluster 1 in advance. when the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the 78k0/lf3, so that boot cluster 1 is used as a boot area. after that, erase or write the or iginal boot program area, boot cluster 0. as a result, even if a power failure occurs while the bo ot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. if the program has been correctly written to boot cluster 0, restore the original bo ot area by using the set information function of the firmware of the 78k0/lf3. note a boot cluster is a 4 kb area and boot clusters 0 and 1 are swapped by the boot swap function. boot cluster 0 (0000h to 0fffh ): original boot program area boot cluster 1 (1000h to 1fffh): area subject to boot swap function figure 28-17. boot swap function boot program (boot cluster 0) new boot program (boot cluster 1) user program self programming to boot cluster 1 self programming to boot cluster 0 setting of boot flag setting of boot flag user program boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) new boot program (boot cluster 0) user program new boot program (boot cluster 1) boot program (boot cluster 0) user program xxxxh xxxxh 2000h 0000h 1000h 2000h 0000h 1000h boot boot boot boot boot remark boot cluster 1 becomes 0000h to 0fffh when a re set is generated after t he boot flag has been set. chapter 28 flash memory user?s manual u18329ej4v0ud 730 figure 28-18. example of executing boot swapping boot cluster 1 booted by boot cluster 0 booted by boot cluster 1 booted by boot cluster 0 block number erasing block 4 boot cluster 0 program program boot program 1000h 0000h 1000h 0000h 0000h 1000h erasing block 5 writing blocks 5 to 7 boot swap boot swap 3 2 1 0 7 6 5 4 boot program boot program boot program program program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program program erasing block 6 erasing block 7 program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program boot program 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program erasing block 0 erasing block 1 erasing block 2 erasing block 3 3 2 1 0 7 6 5 4 boot program boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program writing blocks 0 to 3 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program 3 2 1 0 7 6 5 4 new boot program new boot program new boot program new boot program new boot program new boot program new boot program new boot program user?s manual u18329ej4v0ud 731 chapter 29 on-chip debug function 29.1 connecting qb-mini2 to 78k0/lf3 the 78k0/lf3 uses the v dd , flmd0, reset, ocd0a/x1, ocd0b/x2, and v ss pins to communicate with the host machine via an on-chip debug emulator (qb-mini2). caution the 78k0/lf3 has an on-chip debug function, which is provided for development and evaluation. do not use the on-chip debug function in pr oducts designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. nec electronics is not liable for problems occurring when the on-chip debug function is used. figure 29-1. connection exampl e of qb-mini2 and 78k0/lf3 v dd target device flmd0 x1/ocd0a x2 /ocd0b reset signal reset_in note 1 data clk flmd0 reset v dd reset_out gnd target connector (10-pin) gnd v dd reset circuit v dd v dd gnd r.f.u. r.f.u. note 2 10 k (recommended) 1 k (recommended) (open) (open) notes 1. this connection is designed assuming that the re set signal is output from the n-ch open-drain buffer (output resistance: 100 or less). for details, refer to qb-mini2 user?s manual (u18371e) . 2. make pull-down resistor 470 or more (10 k : recommended). caution input the clock from the ocd0a/x1 pin during on-chip debugging. chapter 29 on-chip debug function user?s manual u18329ej4v0ud 732 connect the flmd0 pin as follows when performing self programming by means of on-chip debugging. figure 29-2. connection of flmd0 pin for self programming by means of on-chip debugging target connector flmd0 flmd0 78k0/lf3 port 1 k (recommended) 10 k (recommended) 29.2 reserved area used by qb-mini2 qb-mini2 uses the reserved areas shown in figure 29-3 below to implement communication with the 78k0/lf3 , or each debug function. the shaded reserved areas are used fo r the respective debug functions to be used, and the other areas are always used for debugging. these reserved areas can be secured by using user programs and compiler options. when using a boot swap operation during self programming , set the same value to boot cluster 1 beforehand. for details on reserved area, refer to qb-mini2 user?s manual (u18371e) . figure 29-3. reserved area used by qb-mini2 debug monitor area (2 bytes) software break area (2 bytes) security id area (10 bytes) option byte area (1 byte) debug monitor area (257 bytes) pseudo rrm area (256 bytes) internal rom space internal ram space stack area for debugging (max. 16 bytes) pseudo rrm area (16 bytes) note ff7fh f7f0h 28fh 190h 18fh 8fh 8eh 85h 84h 7fh 7eh 03h 02h 00h remark shaded reserved areas: area used for the respective debug functions to be used other reserved areas: areas always used for debugging user?s manual u18329ej4v0ud 733 chapter 30 instruction set this chapter lists each instruction set of the 78k0/lf3 in table form. for details of each operation and operation code, refer to the separate document 78k/0 series instructions user?s manual (u12326e) . 30.1 conventions used in operation list 30.1.1 operand identifier s and specification methods operands are written in the ?operand? column of each instruction in ac cordance with the specification method of the instruction operand identifier (refer to the assembler s pecifications for details). when there are two or more methods, select one of them. uppercase letters and the sym bols #, !, $ and [ ] are keywords and must be written as they are. each symbol has the following meaning. ? #: immediate data specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, describe an appropriate num eric value or a label. when using a label, be sure to write the #, !, $, and [ ] symbols. for operand register identifiers r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for specification. table 30-1. operand identifi ers and specification methods identifier specification method r rp sfr sfrp x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special function register symbol note special function register symbol (16-bit manipulatable register even addresses only) note saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even address only) addr16 addr11 addr5 0000h to ffffh immediate data or labels (only even addresses for 16-bit da ta transfer instructions) 0800h to 0fffh immediate data or labels 0040h to 007fh immediate data or labels (even address only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh c annot be accessed with these operands. remark for special function register symbols, see table 3-6 special function register list . chapter 30 instruction set user?s manual u18329ej4v0ud 734 30.1.2 description of operation column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag rbs: register bank select flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ?? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 30.1.3 description of flag operation column (blank): not affected 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is restored chapter 30 instruction set user?s manual u18329ej4v0ud 735 30.2 operation list clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy r, #byte 2 4 ? r byte saddr, #byte 3 6 7 (saddr) byte sfr, #byte 3 ? 7 sfr byte a, r note 3 1 2 ? a r r, a note 3 1 2 ? r a a, saddr 2 4 5 a (saddr) saddr, a 2 4 5 (saddr) a a, sfr 2 ? 5 a sfr sfr, a 2 ? 5 sfr a a, !addr16 3 8 9 a (addr16) !addr16, a 3 8 9 (addr16) a psw, #byte 3 ? 7 psw byte a, psw 2 ? 5 a psw psw, a 2 ? 5 psw a a, [de] 1 4 5 a (de) [de], a 1 4 5 (de) a a, [hl] 1 4 5 a (hl) [hl], a 1 4 5 (hl) a a, [hl + byte] 2 8 9 a (hl + byte) [hl + byte], a 2 8 9 (hl + byte) a a, [hl + b] 1 6 7 a (hl + b) [hl + b], a 1 6 7 (hl + b) a a, [hl + c] 1 6 7 a (hl + c) mov [hl + c], a 1 6 7 (hl + c) a a, r note 3 1 2 ? a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? (sfr) a, !addr16 3 8 10 a ? (addr16) a, [de] 1 4 6 a ? (de) a, [hl] 1 4 6 a ? (hl) a, [hl + byte] 2 8 10 a ? (hl + byte) a, [hl + b] 2 8 10 a ? (hl + b) 8-bit data transfer xch a, [hl + c] 2 8 10 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 736 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy rp, #word 3 6 ? rp word saddrp, #word 4 8 10 (saddrp) word sfrp, #word 4 ? 10 sfrp word ax, saddrp 2 6 8 ax (saddrp) saddrp, ax 2 6 8 (saddrp) ax ax, sfrp 2 ? 8 ax sfrp sfrp, ax 2 ? 8 sfrp ax ax, rp note 3 1 4 ? ax rp rp, ax note 3 1 4 ? rp ax ax, !addr16 3 10 12 ax (addr16) movw !addr16, ax 3 10 12 (addr16) ax 16-bit data transfer xchw ax, rp note 3 1 4 ? ax ? rp a, #byte 2 4 ? a, cy a + byte saddr, #byte 3 6 8 (saddr), cy (saddr) + byte a, r note 4 2 4 ? a, cy a + r r, a 2 4 ? r, cy r + a a, saddr 2 4 5 a, cy a + (saddr) a, !addr16 3 8 9 a, cy a + (addr16) a, [hl] 1 4 5 a, cy a + (hl) a, [hl + byte] 2 8 9 a, cy a + (hl + byte) a, [hl + b] 2 8 9 a, cy a + (hl + b) add a, [hl + c] 2 8 9 a, cy a + (hl + c) a, #byte 2 4 ? a, cy a + byte + cy saddr, #byte 3 6 8 (saddr), cy (saddr) + byte + cy a, r note 4 2 4 ? a, cy a + r + cy r, a 2 4 ? r, cy r + a + cy a, saddr 2 4 5 a, cy a + (saddr) + cy a, !addr16 3 8 9 a, cy a + (addr16) + c a, [hl] 1 4 5 a, cy a + (hl) + cy a, [hl + byte] 2 8 9 a, cy a + (hl + byte) + cy a, [hl + b] 2 8 9 a, cy a + (hl + b) + cy 8-bit operation addc a, [hl + c] 2 8 9 a, cy a + (hl + c) + cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. only when rp = bc, de or hl 4. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 737 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a, cy a ? byte saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte a, r note 3 2 4 ? a, cy a ? r r, a 2 4 ? r, cy r ? a a, saddr 2 4 5 a, cy a ? (saddr) a, !addr16 3 8 9 a, cy a ? (addr16) a, [hl] 1 4 5 a, cy a ? (hl) a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) a, [hl + b] 2 8 9 a, cy a ? (hl + b) sub a, [hl + c] 2 8 9 a, cy a ? (hl + c) a, #byte 2 4 ? a, cy a ? byte ? cy saddr, #byte 3 6 8 (saddr), cy (saddr) ? byte ? cy a, r note 3 2 4 ? a, cy a ? r ? cy r, a 2 4 ? r, cy r ? a ? cy a, saddr 2 4 5 a, cy a ? (saddr) ? cy a, !addr16 3 8 9 a, cy a ? (addr16) ? cy a, [hl] 1 4 5 a, cy a ? (hl) ? cy a, [hl + byte] 2 8 9 a, cy a ? (hl + byte) ? cy a, [hl + b] 2 8 9 a, cy a ? (hl + b) ? cy subc a, [hl + c] 2 8 9 a, cy a ? (hl + c) ? cy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) 8-bit operation and a, [hl + c] 2 8 9 a a (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 738 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) or a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a a byte saddr, #byte 3 6 8 (saddr) (saddr) byte a, r note 3 2 4 ? a a r r, a 2 4 ? r r a a, saddr 2 4 5 a a (saddr) a, !addr16 3 8 9 a a (addr16) a, [hl] 1 4 5 a a (hl) a, [hl + byte] 2 8 9 a a (hl + byte) a, [hl + b] 2 8 9 a a (hl + b) xor a, [hl + c] 2 8 9 a a (hl + c) a, #byte 2 4 ? a ? byte saddr, #byte 3 6 8 (saddr) ? byte a, r note 3 2 4 ? a ? r r, a 2 4 ? r ? a a, saddr 2 4 5 a ? (saddr) a, !addr16 3 8 9 a ? (addr16) a, [hl] 1 4 5 a ? (hl) a, [hl + byte] 2 8 9 a ? (hl + byte) a, [hl + b] 2 8 9 a ? (hl + b) 8-bit operation cmp a, [hl + c] 2 8 9 a ? (hl + c) notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed 3. except ?r = a? remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 739 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy addw ax, #word 3 6 ? ax, cy ax + word subw ax, #word 3 6 ? ax, cy ax ? word 16-bit operation cmpw ax, #word 3 6 ? ax ? word mulu x 2 16 ? ax a x multiply/ divide divuw c 2 25 ? ax (quotient), c (remainder) ax c r 1 2 ? r r + 1 inc saddr 2 4 6 (saddr) (saddr) + 1 r 1 2 ? r r ? 1 dec saddr 2 4 6 (saddr) (saddr) ? 1 incw rp 1 4 ? rp rp + 1 increment/ decrement decw rp 1 4 ? rp rp ? 1 ror a, 1 1 2 ? (cy, a 7 a 0 , a m ? 1 a m ) 1 time rol a, 1 1 2 ? (cy, a 0 a 7 , a m + 1 a m ) 1 time rorc a, 1 1 2 ? (cy a 0 , a 7 cy, a m ? 1 a m ) 1 time rolc a, 1 1 2 ? (cy a 7 , a 0 cy, a m + 1 a m ) 1 time ror4 [hl] 2 10 12 a 3 ? 0 (hl) 3 ? 0 , (hl) 7 ? 4 a 3 ? 0 , (hl) 3 ? 0 (hl) 7 ? 4 rotate rol4 [hl] 2 10 12 a 3 ? 0 (hl) 7 ? 4 , (hl) 3 ? 0 a 3 ? 0 , (hl) 7 ? 4 (hl) 3 ? 0 adjba 2 4 ? decimal adjust accumulator after addition bcd adjustment adjbs 2 4 ? decimal adjust accumulator after subtract cy, saddr.bit 3 6 7 cy (saddr.bit) cy, sfr.bit 3 ? 7 cy sfr.bit cy, a.bit 2 4 ? cy a.bit cy, psw.bit 3 ? 7 cy psw.bit cy, [hl].bit 2 6 7 cy (hl).bit saddr.bit, cy 3 6 8 (saddr.bit) cy sfr.bit, cy 3 ? 8 sfr.bit cy a.bit, cy 2 4 ? a.bit cy psw.bit, cy 3 ? 8 psw.bit cy bit manipulate mov1 [hl].bit, cy 2 6 8 (hl).bit cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 740 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit and1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw.bit 3 ? 7 cy cy psw.bit or1 cy, [hl].bit 2 6 7 cy cy (hl).bit cy, saddr.bit 3 6 7 cy cy (saddr.bit) cy, sfr.bit 3 ? 7 cy cy sfr.bit cy, a.bit 2 4 ? cy cy a.bit cy, psw. bit 3 ? 7 cy cy psw.bit xor1 cy, [hl].bit 2 6 7 cy cy (hl).bit saddr.bit 2 4 6 (saddr.bit) 1 sfr.bit 3 ? 8 sfr.bit 1 a.bit 2 4 ? a.bit 1 psw.bit 2 ? 6 psw.bit 1 set1 [hl].bit 2 6 8 (hl).bit 1 saddr.bit 2 4 6 (saddr.bit) 0 sfr.bit 3 ? 8 sfr.bit 0 a.bit 2 4 ? a.bit 0 psw.bit 2 ? 6 psw.bit 0 clr1 [hl].bit 2 6 8 (hl).bit 0 set1 cy 1 2 ? cy 1 1 clr1 cy 1 2 ? cy 0 0 bit manipulate not1 cy 1 2 ? cy cy notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 741 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy call !addr16 3 7 ? (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callf !addr11 2 5 ? (sp ? 1) (pc + 2) h , (sp ? 2) (pc + 2) l , pc 15 ? 11 00001, pc 10 ? 0 addr11, sp sp ? 2 callt [addr5] 1 6 ? (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (addr5 + 1), pc l (addr5), sp sp ? 2 brk 1 6 ? (sp ? 1) psw, (sp ? 2) (pc + 1) h , (sp ? 3) (pc + 1) l , pc h (003fh), pc l (003eh), sp sp ? 3, ie 0 ret 1 6 ? pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr call/return retb 1 6 ? pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 rrr psw 1 2 ? (sp ? 1) psw, sp sp ? 1 push rp 1 4 ? (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 2 ? psw (sp), sp sp + 1 r r r pop rp 1 4 ? rp h (sp + 1), rp l (sp), sp sp + 2 sp, #word 4 ? 10 sp word sp, ax 2 ? 8 sp ax stack manipulate movw ax, sp 2 ? 8 ax sp !addr16 3 6 ? pc addr16 $addr16 2 6 ? pc pc + 2 + jdisp8 unconditional branch br ax 2 8 ? pch a, pc l x bc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 1 bnc $addr16 2 6 ? pc pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 1 conditional branch bnz $addr16 2 6 ? pc pc + 2 + jdisp8 if z = 0 notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 742 clocks flag instruction group mnemonic operands bytes note 1 note 2 operation zaccy saddr.bit, $addr16 3 8 9 pc pc + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9 pc pc + 3 + jdisp8 if psw.bit = 1 bt [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 1 saddr.bit, $addr16 4 10 11 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc pc + 4 + jdisp8 if psw. bit = 0 bf [hl].bit, $addr16 3 10 11 pc pc + 3 + jdisp8 if (hl).bit = 0 saddr.bit, $addr16 4 10 12 pc pc + 4 + jdisp8 if (saddr.bit) = 1 then reset (saddr.bit) sfr.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12 pc pc + 4 + jdisp8 if psw.bit = 1 then reset psw.bit btclr [hl].bit, $addr16 3 10 12 pc pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit b, $addr16 2 6 ? b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 ? c c ? 1, then pc pc + 2 + jdisp8 if c 0 conditional branch dbnz saddr, $addr16 3 8 10 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 sel rbn 2 4 ? rbs1, 0 n nop 1 2 ? no operation ei 2 ? 6 ie 1 (enable interrupt) di 2 ? 6 ie 0 (disable interrupt) halt 2 6 ? set halt mode cpu control stop 2 6 ? set stop mode notes 1. when the internal high-speed ram area is acce ssed or for an instruction with no data access 2. when an area except the internal high-speed ram area is accessed remarks 1. one instruction clock cycle is one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. this clock cycle applies to the internal rom program. chapter 30 instruction set user?s manual u18329ej4v0ud 743 30.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz second operand first operand #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + byte] [hl + b] [hl + c] $addr16 1 none a add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov add addc sub subc and or xor cmp inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] [hl + b] [hl + c] mov x mulu c divuw note except ?r = a? chapter 30 instruction set user?s manual u18329ej4v0ud 744 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand first operand #word ax rp note sfrp saddrp !addr16 sp none ax addw subw cmpw movw xchw movw movw movw movw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand first operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none a.bit mov1 bt bf btclr set1 clr1 sfr.bit mov1 bt bf btclr set1 clr1 saddr.bit mov1 bt bf btclr set1 clr1 psw.bit mov1 bt bf btclr set1 clr1 [hl].bit mov1 bt bf btclr set1 clr1 cy mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 mov1 and1 or1 xor1 set1 clr1 not1 chapter 30 instruction set user?s manual u18329ej4v0ud 745 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand first operand ax !addr16 !addr11 [addr5] $addr16 basic instruction br call br callf callt br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop user?s manual u18329ej4v0ud 746 chapter 31 electrical specifications (standard products) caution the 78k0/lf3 has an on-chi p debug function, which is provid ed for development and evaluation. do not use the on-chip debug function in products designate d for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. nec electronics is not liable for problems occurring when the on-chip debug function is used. absolute maximum ratings (t a = 25 c) (1/2) parameter symbol conditions ratings unit v dd ? 0.5 to +6.5 v v ss ? 0.5 to +0.3 v av ref note 2 ? 0.5 to v dd + 0.3 note 1 v supply voltage av ss note 2 ? 0.5 to +0.3 v regc pin input voltage v iregc ? 0.5 to + 3.6 and ? 0.5 to v dd v input voltage v i p10 to p17, p20 to p27, p30 to p34, p40 to p47, p80 to p83, p90 to p93, p100 to p103, p110 to p113, p120 to p124, p130 to p133, p140 to p143, p150 to p153, x1, x2, xt1, xt2, flmd0, reset ? 0.3 to v dd + 0.3 note 1 v output voltage v o ? 0.3 to v dd + 0.3 note 1 v v an ani0 to ani7 note 2 , ds0 ? to ds2 ? note 3 , ds0+ to ds2+ note 3 ? 0.3 to av ref + 0.3 note 1 and ? 0.3 to v dd + 0.3 note 1 v ref+ note 3 ? 0.5 to av ref + 0.3 note 1 v analog input voltage ref ? note 3 ? 0.5 to + 0.3 v notes 1. must be 6.5 v or lower. 2. pd78f048x and 78f049x only. 3. pd78f049x only. caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 747 standard p roducts absolute maximum ratings (t a = 25 c) (2/2) parameter symbol conditions ratings unit per pin p10 to p17, p30 to p34, p40 to p47, p80 to p83, p90 to p93, p100 to p103, p110 to p113, p120, p130 to p133, p140 to p143, p150 to p153 ? 10 ma p10 to p17, p30 to p34, p40 to p47, p120 ? 25 ma i oh1 total of all pins ? 35 ma p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 ? 10 ma per pin ? 0.5 ma output current, high i oh2 total of all pins p20 to p27 ? 2 ma per pin p10 to p17, p30 to p34, p40 to p47, p80 to p83, p90 to p93, p100 to p103, p110 to p113, p120, p130 to p133, p140 to p143, p150 to p153 30 ma p10 to p17, p30 to p34, p40 to p47, p120 40 ma total of all pins 80 ma p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 40 ma per pin 1 ma output current, low i ol total of all pins p20 to p27 5 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute m aximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 748 standard p roducts x1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit 2.7 v v dd 5.5 v 2.0 10.0 c1 x2 x1 v ss c2 x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 2.0 10.0 crystal resonator c1 x2 x1 c2 v ss x1 clock oscillation frequency (f x ) note 1.8 v v dd < 2.7 v 2.0 5.0 mhz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the x1 oscillator, wire as follo ws in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. ? keep the wiring leng th as short as possible. ? do not cross the wiring wi th the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the o scillator capacitor th e same potential as v ss . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 2. since the cpu is started by the internal high-speed oscillation clock after a reset release, check the x1 clock oscillation stabilization time using th e oscillation stabilization time counter status register (ostc) by the user. de termine the oscillation stabilizat ion time of the ostc register and oscillation stabilization time select register (osts) a fter sufficiently evaluating the oscillation stabilization time wit h the resonator to be used. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 749 standard p roducts internal oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) resonator parameter conditions min. typ. max. unit 2.5 v v dd 5.5 v 7.6 8.0 8.4 mhz rsts = 1 1.8 v v dd < 2.5 v 6.75 8.0 8.4 mhz 8 mhz internal oscillator internal high-speed oscillation clock frequency (f rh ) notes 1, 2 rsts = 0 2.48 5.6 9.86 mhz 2.6 v v dd 5.5 v 216 240 264 khz 240 khz internal oscillator internal low-speed oscillation clock frequency (f rl ) 1.8 v v dd < 2.6 v 192 240 264 khz notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. when setting hiotrm = 10h ( 0%: default) remark rsts: bit 7 of the internal oscillation mode register (rcm) xt1 oscillator characteristics (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) resonator recommended circuit parameter conditions min. typ. max. unit crystal resonator xt1 xt2 c4 c3 rd v ss xt1 clock oscillation frequency (f xt ) note 32 32.768 35 khz note indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. cautions 1. when using the xt1 oscillator, wire as follows in the area enclosed by the br oken lines in the above figure to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the xt1 oscillator is desi gned as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than th e x1 oscillator. partic ular care is therefore required with the wiring method when the xt1 clock is used. remark for the resonator selection and oscillator const ant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 750 standard p roducts recommended oscillator constants (1) x1 oscillator: ceramic resonator (t a = ? 40 to +85 c) recommended circuit invariable oscillation voltage range manufacturer part number smd/ lead frequency (mhz) c1 (pf) c2 (pf) min.(v) max.(v) cstcc2m00g56-r0 smd 2.00 internal (47) internal (47) cstls4m00g56-b0 lead internal (47) internal (47) cstcr4m00g55-r0 smd 4.00 internal (39) internal (39) cstls4m19g56-b0 lead internal (47) internal (47) cstcr4m19g55-r0 smd 4.194 internal (39) internal (39) 1.8 cstls4m91g56-b0 lead internal (47) internal (47) 2.0 cstcr4m91g55-r0 smd 4.915 internal (39) internal (39) 1.8 cstls5m00g56-b0 lead internal (47) internal (47) 2.0 cstcr5m00g55-r0 smd 5.00 internal (39) internal (39) 1.8 cstls6m00g56-b0 lead internal (47) internal (47) 2.2 cstcr6m00g55-r0 smd 6.00 internal (39) internal (39) 1.9 cstls8m00g56-b0 lead internal (47) internal (47) 2.2 cstce8m00g55-r0 smd 8.00 internal (33) internal (33) 1.8 cstls8m38g56-b0 lead internal (47) internal (47) 2.2 cstce8m38g55-r0 smd 8.388 internal (33) internal (33) 1.8 cstls10m0g53-b0 smd internal (15) internal (15) 1.8 murata mfg. cstce10m0g55-r0 smd 10.0 internal (33) internal (33) 2.1 5.5 cstls4m91g53-b0 lead 4.915 internal (15) internal (15) 1.8 cstls5m00g53-b0 lead 5.00 internal (15) internal (15) 1.8 cstcr6m00g53-r0 smd internal (15) internal (15) 1.8 cstls6m00g53-b0 lead 6.00 internal (15) internal (15) 1.8 cstls8m00g53-b0 lead 8.00 internal (15) internal (15) 1.8 cstls8m38g53-b0 lead 8.388 internal (15) internal (15) 1.8 murata mfg. (low-capacitance products) cstce10m0g52-r0 smd 10.0 internal (10) internal (10) 1.8 5.5 caution the oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator ma nufacturer. if it is necessary to optimize the oscillator characteristics in the actual application, appl y to the resonator manufacturer for evaluation on the implementation circuit. the oscillation voltage and oscillati on frequency only indicate the oscillator characteristic. use the 78k0/lf3 so that the internal operation conditions are within the specifications of the dc and ac characteristics. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 751 standard p roducts dc characteristics (1/5) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v ? 3.0 ma 2.7 v v dd < 4.0 v ? 2.5 ma per pin for p10 to p17, p30 to p34, p40 to p47, p120 1.8 v v dd < 2.7 v ? 1.0 ma 4.0 v v dd 5.5 v ? 0.1 ma 2.7 v v dd < 4.0 v ? 0.1 ma per pin for p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 1.8 v v dd < 2.7 v ? 0.1 ma 4.0 v v dd 5.5 v ? 20.0 ma 2.7 v v dd < 4.0 v ? 10.0 ma total note3 of p10 to p17, p30 to p34, p40 to p47, p120 1.8 v v dd < 2.7 v ? 5.0 ma 4.0 v v dd 5.5 v ? 2.8 ma 2.7 v v dd < 4.0 v ? 2.8 ma total note3 of p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 1.8 v v dd < 2.7 v ? 2.8 ma 4.0 v v dd 5.5 v ? 22.8 ma 2.7 v v dd < 4.0 v ? 12.8 ma i oh1 total note3 of all pins 1.8 v v dd < 2.7 v ? 7.8 ma output current, high note1 i oh2 per pin for p20 to p27 av ref = v dd ? 0.1 ma 4.0 v v dd 5.5 v 8.5 ma 2.7 v v dd < 4.0 v 5.0 ma per pin for p10 to p17, p30 to p34, p40 to p47, p120 1.8 v v dd < 2.7 v 2.0 ma 4.0 v v dd 5.5 v 0.4 ma 2.7 v v dd < 4.0 v 0.4 ma per pin for p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 1.8 v v dd < 2.7 v 0.4 ma 4.0 v v dd 5.5 v 20.0 ma 2.7 v v dd < 4.0 v 15.0 ma total note3 of p10 to p17, p30 to p34, p40 to p47, p120 1.8 v v dd < 2.7 v 9.0 ma 4.0 v v dd 5.5 v 11.2 ma 2.7 v v dd < 4.0 v 11.2 ma total note3 of p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 1.8 v v dd < 2.7 v 11.2 ma 4.0 v v dd 5.5 v 31.2 ma 2.7 v v dd < 4.0 v 26.2 ma i ol1 total note3 of all pins 1.8 v v dd < 2.7 v 20.2 ma output current, low note2 i ol2 per pin for p20 to p27 av ref = v dd 0.4 ma notes 1. value of current at which the device operation is guaranteed even if the current flows from v dd to an output pin. 2. value of current at which the device operation is guaran teed even if the current flows from an output pin to gnd. 3. specification under conditions where the duty factor is 70% (time for which cu rrent is output is 0.7 t and time for which current is not output is 0.3 t, where t is a specific time). the total output current of the pins at a duty factor of other than 70% can be calculated by the following expression. ? where the duty factor of i oh is n%: total output current of pins = (i oh 0.7)/(n 0.01) chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 752 standard p roducts dc characteristics (2/5) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 p10, p16, p17, p32, p80 to p83, p90 to p93, p100 to p103, p110 to p112, p121 to p124, p130 to p133, p140 to p143, p150 to p153 0.7v dd v dd v v ih2 p11 to p15, p30, p31, p33, p34, p40 to p47, p113, p120, reset, exclk 0.8v dd v dd v input voltage, high v ih3 p20 to p27 av ref = v dd 0.7av ref av ref v v il1 p10, p16, p17, p32, p80 to p83, p90 to p93, p100 to p103, p110 to p112, p121 to p124, p130 to p133, p140 to p143, p150 to p153 0 0.3v dd v v il2 p11 to p15, p30, p31, p33, p34, p40 to p47, p113, p120, reset, exclk 0 0.2v dd v input voltage, low v il3 p20 to p27 av ref = v dd 0 0.3av ref v 4.0 v v dd 5.5 v, i oh1 = ? 3.0 ma v dd ? 0.7 v 2.7 v v dd < 4.0 v, i oh1 = ? 2.5 ma v dd ? 0.5 v p10 to p17, p30 to p34, p40 to p47, p120 1.8 v v dd < 2.7 v, i oh1 = ? 1.0 ma v dd ? 0.5 v v oh1 p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 i oh1 = ? 0.1 ma v dd ? 0.5 v output voltage, high v oh2 p20 to p27 av ref = v dd , i oh2 = ? 0.1 ma v dd ? 0.5 v 4.0 v v dd 5.5 v, i ol1 = 8.5 ma 0.7 v 2.7 v v dd < 4.0 v, i ol1 = 5.0 ma 0.7 v 1.8 v v dd < 2.7 v, i ol1 = 2.0 ma 0.5 v 1.8 v v dd < 2.7 v, i ol1 = 1.0 ma 0.5 v p10 to p17, p30 to p34, p40 to p47, p120 1.8 v v dd < 2.7 v, i ol1 = 0.5 ma 0.4 v v ol1 p80 to p83, p90 to p93, p100 to p103, p110 to p113, p130 to p133, p140 to p143, p150 to p153 i ol1 = 0.4 ma 0.4 v output voltage, low v ol2 p20 to p27 av ref = v dd , i ol2 = 0.4 ma 0.4 v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. caution the high-level and low-level input voltages of p122/exclk vary between the input port mode and external clock mode. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 753 standard p roducts dc characteristics (3/5) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit i lih1 p10 to p17, p30 to p34, p40 to p47, p80 to p83, p90 to p93, p100 to p103, p110 to p113, p120, p130 to p133, p140 to p143, p150 to p153, flmd0, reset v i = v dd 1 a i lih2 p20 to p27 v i = av ref = v dd 1 a i/o port mode 1 a input leakage current, high i lih3 p121 to 124 (x1, x2, xt1, xt2) v i = v dd osc mode 20 a i lil1 p10 to p17, p30 to p34, p40 to p47, p80 to p83, p90 to p93, p100 to p103, p110 to p113, p120, p130 to p133, p140 to p143, p150 to p153, flmd0, reset v i = v ss ? 1 a i lil2 p20 to p27 v i = v ss , av ref = v dd ? 1 a i/o port mode ? 1 a input leakage current, low i lil3 p121 to 124 (x1, x2, xt1, xt2) v i = v ss osc mode ? 20 a pull-up resistor r u v i = v ss 10 20 100 k v il in normal operation mode 0 0.2v dd v flmd0 supply voltage v ih in self-programming mode 0.8v dd v dd v remark unless specified otherwise, the characteristics of alter nate-function pins are the same as those of port pins. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 754 standard p roducts dc characteristics (4/5) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit square wave input 1.6 3.0 f xh = 10 mhz note 2 , v dd = 5.0 v resonator connection 2.3 3.4 ma square wave input 1.5 2.9 f xh = 10 mhz note 2 , v dd = 3.0 v resonator connection 2.2 3.3 ma square wave input 0.9 1.7 f xh = 5 mhz note 2 , v dd = 3.0 v resonator connection 1.3 2.0 ma square wave input 0.7 1.4 f xh = 5 mhz note 2 , v dd = 2.0 v resonator connection 1.0 1.6 ma f rh = 8 mhz, v dd = 5.0 v note 3 1.4 2.3 ma i dd1 note 1 operating mode f sub = 32.768 khz note 4 , v dd = 5.0 v resonator connection 6.7 26 a square wave input 0.4 1.4 f xh = 10 mhz note 2 , v dd = 5.0 v resonator connection 1.0 1.7 ma square wave input 0.2 0.7 f xh = 5 mhz note 2 , v dd = 3.0 v resonator connection 0.5 1.0 ma f rh = 8 mhz, v dd = 5.0 v note 3 0.4 1.2 ma i dd2 note 1 halt mode f sub = 32.768 khz note 5 , v dd = 5.0 v resonator connection 2.4 22 a v dd = 5.0 v 1 20 a supply current i dd3 note 6 stop mode v dd = 5.0 v, t a = ? 40 to +70 c 1 10 a notes 1. total current flowing into the internal power supply (v dd ), including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . the max. values include the peri pheral operation current. however, the current flowing into the pull-up resistors and the output current of the port are not included. 2. not including the operating current of the 8 mhz inte rnal oscillator, 240 khz internal oscillator and xt1 oscillation, and the current flowing into the a/ d converter, watchdog timer, lvi circuit and lcd controller/driver. 3. not including the operating current of the x1 oscillation, xt1 oscilla tion and 240 khz internal oscillator, and the current flowing into the a/d converter, wa tchdog timer, lvi circuit and lcd controller/driver. 4. not including the operating current of the x1 oscillation, 8 mhz inte rnal oscillator and 240 khz internal oscillator, and the current flowing into the a/ d converter, watchdog timer, lvi circuit and lcd controller/driver. 5. not including the operating current of the x1 oscillation, 8 mhz inte rnal oscillator and 240 khz internal oscillator, and the current flowing into the a/d converter, watchdog timer, lvi circuit, lcd controller/driver and real-time counter. 6. total current flowing into the internal power supply (v dd ), including the input leakage current flowing when the level of the input pin is fixed to v dd or v ss . however, the current flowing into the pull-up resistors and the output current of the por t, the operating current of the 240 khz inte rnal oscillator and xt1 oscillation, and the current flowing into the a/d converter, watchdog timer, lvi circuit, lcd controller/driver and real- time counter are not included. remarks 1. f xh : high-speed system clock frequency (x1 clock oscillation frequency or external main system clock frequency) 2. f rh : internal high-speed oscillation clock frequency 3. f sub : subsystem clock frequency (xt1 clock oscillation frequency) chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 755 standard p roducts dc characteristics (5/5) (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, av ref v dd , v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit watchdog timer operating current i wdt note 1 during 240 khz internal low-spee d oscillation clock operation 5 10 a lvi operating current i lvi note 2 9 18 a successive approximation type a/d converter operating current i adc1 note 3 2.3 v av ref v dd 0.86 1.9 ma ? type a/d converter operating current i adc2 note 3 2.7 v av ref v dd 1.4 2.7 ma v dd = 5.0 v 3.0 8.0 a i lcd1 note 4 lcd display off (des elect signal output) (lcdon = 0, scoc = 1) v dd = 3.0 v 2.0 5.0 a v dd = 5.0 v 3.0 8.0 a lcd operating current i lcd2 note 4 lcd display on (lcdon = 1, scoc = 1) v dd = 3.0 v 2.0 5.0 a notes 1. this includes only the current that flows through t he watchdog timer (including t he operating current of the 240 khz internal oscillator). when the watchdog time r is operating in halt mode or stop mode, the current value of the 78k0/ lf3 is obtained by adding i wdt to i dd2 or i dd3 . 2. this includes only the current that flows through the lvi circuit. when the lvi circuit is operating in halt mode or stop mode, the current value of the 78k0/lf3 is obtained by adding i lvi to i dd2 or i dd3 . 3. this includes only the current that flows through the a/d converter (av ref ). when the a/d converter is operating in halt mode or stop m ode, the current value of the 78k0 /lf3 is obtained by adding i adc1 or i adc2 to i dd1 or i dd2 . 4. this includes only the current that flows through the lcd controller/driver. not including the current that flows through the lcd divider resistor. the current value of the 78k0/lf3 is obtained by adding the lcd operating current (i lcd1 or i lcd2 ) to the supply current (i dd1 , i dd2 , or i dd3 ). chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 756 standard p roducts ac characteristics (1) basic operation (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 0.2 16 s main system clock (f xp ) operation 1.8 v v dd < 2.7 v 0.4 16 s instruction cycle (minimum instruction execution time) t cy subsystem clock (f sub ) operation 114 122 125 s 2.7 v v dd 5.5 v 10 mhz xsel = 1 1.8 v v dd < 2.7 v 5 mhz 2.7 v v dd 5.5 v 7.6 8.4 mhz peripheral hardware clock frequency f pns xsel = 0 1.8 v v dd < 2.7 v note 1 6.75 8.4 mhz 2.7 v v dd 5.5 v 2.0 10.0 mhz external main system clock frequency f exclk 1.8 v v dd < 2.7 v 2.0 5.0 mhz 2.7 v v dd 5.5 v 48 500 ns external main system clock input high-level width, low-level width t exclkh , t exclkl 1.8 v v dd < 2.7 v 96 500 ns 2.7 v v dd 5.5 v 2/f sam + 0.2 note 2 s ti000 input high-level width, low-level width t tih0 , t til0 1.8 v v dd < 2.7 v 2/f sam + 0.5 note 2 s ti50, ti51 10 mhz 4.0 v v dd 5.5 v ti52 16 mhz 2.7 v v dd < 4.0 v 10 mhz ti50, ti51, ti52 input frequency f ti5 1.8 v v dd < 2.7 v 5 mhz ti50, ti51 50 ns 4.0 v v dd 5.5 v ti52 31.25 ns 2.7 v v dd < 4.0 v 50 ns ti50, ti51, ti52 input high-level width, low-level width t tih5 , t til5 1.8 v v dd < 2.7 v 100 ns interrupt input high-level width, low-level width t inth , t intl 1 s key return input low-level width t kr 250 ns reset low-level width t rsl 10 s notes 1. a characteristic of the main system clock frequency. set the clock di vider to be set using a peripheral function to f rh /2 or less. 2. selection of f sam = f prs , f prs /4, f prs /256 is possible using bits 0 and 1 (prm000, prm001) of prescaler mode registers 00 (prm00). note that when select ing the ti000 valid edge as the count clock, f sam = f prs. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 757 standard p roducts t cy vs. v dd (main system clock operation) 5.0 1.0 2.0 0.4 0.2 0.1 0 10 1.0 2.0 3.0 4.0 5.0 6.0 5.5 2.7 100 0.01 1.8 16 supply voltage v dd [v] guaranteed operation range cycle time t cy [ s] ac timing test points (excluding ex ternal main system clock) v ih v il test points v ih v il external main system clock timing exclk 0.8v dd (min.) 0.2v dd (max.) 1/f exclk t exclkl t exclkh chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 758 standard p roducts ti timing ti000 t til0 t tih0 ti50, ti51, ti52 1/f ti5 t til5 t tih5 interrupt request input timing intp0 to intp5 t intl t inth key interrupt input timing kr0 to kr7 t kr reset input timing reset t rsl chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 759 standard p roducts (2) serial interface (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit transfer rate 250 kbps (3) serial interface (t a = ? 40 to +85 c, 1.8 v v dd 5.5 v, v ss = av ss = 0 v) (a) uart6 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps (b) uart0 (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 625 kbps chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 760 standard p roducts (c) csi10 (master mode, sck1 0... internal clock output) parameter symbol conditions min. typ. max. unit 2.7 v v dd 5.5 v 250 ns sck10 cycle time t kcy1 1.8 v v dd < 2.7 v 500 ns 2.7 v v dd 5.5 v t kcy1 /2 ? 25 note 1 ns sck10 high-/low-level width t kh1 , t kl1 1.8 v v dd < 2.7 v t kcy1 /2 ? 50 note 1 ns 2.7 v v dd 5.5 v 80 ns si10 setup time (to sck10 ) t sik1 1.8 v v dd < 2.7 v 170 ns si10 hold time (from sck10 ) t ksi1 30 ns delay time from sck10 to so10 output t kso1 c = 50 pf note 2 40 ns notes 1. this value is when high-speed system clock (f xh ) is used. 2. c is the load capacitance of the sck10 and so10 output lines. (d) csi10 (slave mode, sck10... external clock input) parameter symbol conditions min. typ. max. unit sck10 cycle time t kcy2 400 ns sck10 high-/low-level width t kh2 , t kl2 t kcy2 /2 ns si10 setup time (to sck10 ) t sik2 80 ns si10 hold time (from sck10 ) t ksi2 50 ns 2.7 v v dd 5.5 v 120 ns delay time from sck10 to so10 output t kso2 c = 50 pf note 1.8 v v dd < 2.7 v 165 ns note c is the load capacitance of the so10 output line. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 761 standard p roducts (e) autocsi (master mode, scka0... internal clock output) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns 2.7 v v dd < 4.0 v 1200 ns scka0 cycle time t kcy3 1.8 v v dd < 2.7 v 1800 ns 4.0 v v dd 5.5 v t kcy3 /2 ? 50 ns 2.7 v v dd < 4.0 v t kcy3 /2 ? 100 ns scka0 high-/low-level width t kh3 , t kl3 1.8 v v dd < 2.7 v t kcy3 /2 ? 200 ns 2.7 v v dd 5.5 v 100 ns sia0 setup time (to scka0 ) t sik3 1.8 v v dd < 2.7 v 200 ns sia0 hold time (from scka0 ) t ksi3 300 ns 4.0 v v dd 5.5 v 200 ns 2.7 v v dd < 4.0 v 300 ns delay time from scka0 to soa0 output t kso3 c = 100 pf note 1.8 v v dd < 2.7 v 400 ns note c is the load capacitance of the scka0 and soa0 output lines. (f) autocsi (slave mode, scka0... external clock input) parameter symbol conditions min. typ. max. unit 4.0 v v dd 5.5 v 600 ns 2.7 v v dd < 4.0 v 1200 ns scka0 cycle time t kcy4 1.8 v v dd < 2.7 v 1800 ns 4.0 v v dd 5.5 v 300 ns 2.7 v v dd < 4.0 v 600 ns scka0 high-/low-level width t kh4 , t kl4 1.8 v v dd < 2.7 v 900 ns sia0 setup time (to scka0 ) t sik4 4.0 v v dd 5.5 v 100 ns sia0 hold time (from scka0 ) t ksi4 2/f w +100 ns 4.0 v v dd 5.5 v 2/f w +100 ns 2.7 v v dd < 4.0 v 2/f w +200 ns delay time from scka0 to soa0 output t kso4 c = 100 pf note 1.8 v v dd < 2.7 v 2/f w +300 ns scka0 rise/fall time t r4 , t f4 1000 ns note c is the load capacitance of the soa0 output line. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 762 standard p roducts serial transfer timing (1/2) csi10: si10 so10 t kcym t klm t khm t sikm t ksim input data t ksom output data sck10 remark m = 1, 2 chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 763 standard p roducts serial transfer timing (2/2) csia0: scka0 sia0 soa0 d2 d1 d0 d2 d1 d0 d7 d7 t sik3, 4 t ksi3, 4 t kso3, 4 t kh3, 4 t f4 t r4 t kl3, 4 t kcy3, 4 chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 764 standard p roducts 10-bit successive approximation type a/d converter characteristics ( pd78f048x and 78f049x only) (t a = ? 40 to +85 c, 2.3 v av ref v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es1 10 bit 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr overall error notes 1, 2 a inl 2.3 v av ref < 2.7 v 1.2 %fsr 4.0 v av ref 5.5 v 6.1 36.7 s 2.7 v av ref < 4.0 v 12.2 36.7 s conversion time t conv 2.3 v av ref < 2.7 v 27 66.6 s 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr zero-scale error notes 1, 2 e zs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 0.4 %fsr 2.7 v av ref < 4.0 v 0.6 %fsr full-scale error notes 1, 2 e fs 2.3 v av ref < 2.7 v 0.6 %fsr 4.0 v av ref 5.5 v 2.5 lsb 2.7 v av ref < 4.0 v 4.5 lsb integral non-linearity error note 1 i le1 2.3 v av ref < 2.7 v 6.5 lsb 4.0 v av ref 5.5 v 1.5 lsb 2.7 v av ref < 4.0 v 2.0 lsb differential non-linearity error note 1 d le1 2.3 v av ref < 2.7 v 2.0 lsb analog input voltage v ain1 av ss av ref v notes 1. excludes quantization error ( 1/2 lsb). 2. this value is indicated as a ratio (%fsr) to the full-scale value. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 765 standard p roducts 16-bit ? type a/d converter characteristics ( pd78f049x only) (t a = ? 40 to +85 c, 2.7 v av ref v dd 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution r es2 8 16 bit 3.5 v av ref 5.5 v 0.016 1.25 mhz at differential input 2.7 v av ref < 3.5 v 0.016 0.625 mhz 2.85 v av ref 5.5 v 0.016 0.625 mhz sampling clock note 1 f vp at single input 2.7 v av ref < 2.85 v 0.016 0.525 mhz av ref = 5.0 v 1.0 lsb 3.5 v av ref 5.5 v 1.7 lsb at differential input note 2 14-bit resolution note 3 2.7 v av ref < 3.5 v 2.6 lsb integral non-linearity error (relative accuracy) i le2 at single input note 2 12-bit resolution note 3 2.8 lsb av ref = 5.0 v 1.0 lsb 3.5 v av ref 5.5 v 1.7 lsb at differential input note 2 14-bit resolution note 3 2.7 v av ref < 3.5 v 2.6 lsb differential non-linearity error (relative accuracy) d le2 at single input note 2 12-bit resolution note 3 2.8 lsb at differential input 0.032 %fsr offset eos at single input 0.16 %fsr at differential input 0.09 % gain error ge at single input 0.1 % ref+ av ref v reference voltage ref ? av ss v in high-accuracy mode off 0 ref+ v analog input voltage v ain2 in high-accuracy mode on 0.1ref+ 0.9ref+ v notes 1. the conversion time can be calculated by using the following expression, based on the sampling clock (f vp ) and set resolution (n bits). conversion time = 2 n / f vp 2. these values apply when the high-accuracy mode is set to be on during differential input, or when the high-accuracy mode is set to be off during single input. 3. the characteristics of resolutions (n bits) other t han those stated as conditions in the integral linearity error (i le2 ) and differential linearity error (d le2 ) columns can be calculated by using the following expressions. ? during differential input i le2 in n-bit resolution = i le2 in 14-bit resolution 2 (n ? 14) d le2 in n-bit resolution = d le2 in 14-bit resolution 2 (n ? 14) ? during single input i le2 in n-bit resolution = i le2 in 12-bit resolution 2 (n ? 12) d le2 in n-bit resolution = d le2 in 12-bit resolution 2 (n ? 12) remark in the 16-bit ? type a/d converter characteristics, the approxi mation line is defined by the least-squares method. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 766 standard p roducts lcd characteristics (1) resistance division method (a) static display mode (t a = ? 40 to +85 c, 1.8 v v lcd v dd 5.5 v, v ss = 0 v) note 3 parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd note 3 v dd v lcd divider resistor note 1 r lcd 60 100 150 k lcd output resistor note 2 (common) r odc 40 k lcd output resistor note 2 (segment) r ods 200 k (b) 1/3 bias method (t a = ? 40 to +85 c, 1.8 v v lcd v dd 5.5 v, v ss = 0 v) note 3 parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd note 3 v dd v lcd divider resistor note 1 r lcd 60 100 150 k lcd output resistor note 2 (common) r odc 40 k lcd output resistor note 2 (segment) r ods 200 k (c) 1/2 bias method, 1/4 bias method (t a = ? 40 to +85 c, 1.8 v v lcd v dd 5.5 v, v ss = 0 v) note 3 parameter symbol conditions min. typ. max. unit lcd drive voltage v lcd note 3 v dd v lcd divider resistor note 1 r lcd 60 100 150 k lcd output resistor note 2 (common) r odc 40 k lcd output resistor note 2 (segment) r ods 200 k notes 1. internal resistance division method only. 2. the output resistor is a resist or connected between one of the v lc0 , v lc1 , v lc2 and v ss pins, and either of the seg and com pins. 3. set vaon based on the following conditions. chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 767 standard p roducts 1.59 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage v poc 1.44 1.59 1.74 v power supply voltage rise inclination t pth v dd : 0 v change inclination of v poc 0.5 v/ms minimum pulse width t pw 200 s poc circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t pth t pw supply voltage rise time (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit maximum time to rise to 1.8 v (v dd (min.)) (v dd : 0 v 1.8 v) t pup1 pocmode (option byte) = 0, when reset input is not used 3.6 ms maximum time to rise to 1.8 v (v dd (min.)) (releasing reset input v dd : 1.8 v) t pup2 pocmode (option byte) = 0, when reset input is used 1.9 ms supply voltage rise time timing ? when reset pin input is not used ? when reset pin input is used supply voltage (v dd ) time 1.8 v t pup1 supply voltage (v dd ) time 1.8 v t pup2 v poc reset pin 2.7 v poc circuit characteristics (t a = ? 40 to +85 c, v ss = 0 v) parameter symbol conditions min. typ. max. unit detection voltage on application of supply voltage v ddpoc pocmode (option bye) = 1 2.50 2.70 2.90 v chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 768 standard p roducts lvi circuit characteristics (t a = ? 40 to +85 c, v poc v dd 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit v lvi0 4.14 4.24 4.34 v v lvi1 3.99 4.09 4.19 v v lvi2 3.83 3.93 4.03 v v lvi3 3.68 3.78 3.88 v v lvi4 3.52 3.62 3.72 v v lvi5 3.37 3.47 3.57 v v lvi6 3.22 3.32 3.42 v v lvi7 3.06 3.16 3.26 v v lvi8 2.91 3.01 3.11 v v lvi9 2.75 2.85 2.95 v v lvi10 2.60 2.70 2.80 v v lvi11 2.45 2.55 2.65 v v lvi12 2.29 2.39 2.49 v v lvi13 2.14 2.24 2.34 v v lvi14 1.98 2.08 2.18 v supply voltage level v lvi15 1.83 1.93 2.03 v detection voltage external input pin note 1 exlvi exlvi < v dd , 1.8 v v dd 5.5 v 1.11 1.21 1.31 v minimum pulse width t lw 200 s operation stabilization wait time note 2 t lwait 10 s notes 1. the exlvi/p120/intp0 pin is used. 2. time required from setting bit 7 (lvion) of the low- voltage detection register (lvim) to 1 to operation stabilization. remark v lvi(n ? 1) > v lvin : n = 1 to 15 lvi circuit timing supply voltage (v dd ) time detection voltage (min.) detection voltage (typ.) detection voltage (max.) t lw t lwait lvion 1 chapter 31 electrical specifications (standard products) user?s manual u18329ej4v0ud 769 standard p roducts data memory stop mode low supply vo ltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the poc detec tion voltage. when the voltage drop s, the data is retained until a poc reset is effected, but data is not re tained when a poc reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode flash memory programming characteristics (t a = ? 40 to +85 c, 2.7 v v dd 5.5 v, v ss = av ss = 0 v) ? basic characteristics parameter symbol conditions min. typ. max. unit v dd supply current i dd 4.5 11.0 ma all block t eraca 20 200 ms erase time note 1, 2 block unit t erasa 20 200 ms write time (in 8-bit units) note 1 t wrwa 10 100 s when a flash memory programmer is used, and the libraries provided by nec electronics are used retention: 15 years 1000 times number of rewrites per chip c erwr 1 erase + 1 write after erase = 1 rewrite note 3 when the eeprom emulation libraries provided by nec electronics are used, and the rewritable rom size is 4 kb retention: 3 years note 4 10000 times notes 1. characteristic of the flash memory. for the characte ristic when a dedicated flash programmer, pg-fp5, is used and the rewrite time during self programming, see tables 28-12 and 28-13 . 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? and ?write only? are both taken as one rewrite. 4. data retention is guaranteed for three years after data has been written. if re writing has been performed, data retention is guaranteed for another three years thereafter. remark f xp : main system clock oscillation frequency user?s manual u18329ej4v0ud 770 chapter 32 package drawings s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 14.00 0.20 14.00 0.20 17.20 0.20 17.20 0.20 1.70 max. 0.125 0.075 1.40 0.05 0.25 c e x y zd ze 0.65 0.13 0.10 0.825 0.825 l lp l1 0.80 0.886 0.15 1.60 0.20 p80gc-65-gad 3 + 5 ? 3 note each lead centerline is located within 0.13 mm of its true position at maximum material condition. detail of lead end 80-pin plastic lqfp (14x14) 0.30 b 20 40 80 21 41 60 1 + 0.08 ? 0.04 61 chapter 32 package drawings user?s manual u18329ej4v0ud 771 s y e s x b m l c lp hd he zd ze l1 a1 a2 a d e a3 s 0.125 + 0.075 ? 0.025 (unit:mm) item dimensions d e hd he a a1 a2 a3 12.00 0.20 12.00 0.20 14.00 0.20 14.00 0.20 1.60 max. 0.10 0.05 1.40 0.05 0.25 c e x y zd ze 0.50 0.08 0.08 1.25 1.25 l lp l1 0.50 0.60 0.15 1.00 0.20 p80gk-50-gak 3 + 5 ? 3 note each lead centerline is located within 0.08 mm of its true position at maximum material condition. detail of lead end 0.20 b 20 40 1 80 21 41 61 60 80-pin plastic lqfp (fine pitch) (12x12) + 0.07 ? 0.03 user?s manual u18329ej4v0ud 772 chapter 33 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for soldering methods and conditions other than those recommended below, please contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 33-1. surface mounting ty pe soldering conditions soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220 c or higher), count: 3 times or less, exposure limit: 7 days note (after that, prebake at 125 c for 10 to 72 hours) ir60-107-3 partial heating pin temperature: 350 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together ( except for partial heating). user?s manual u18329ej4v0ud 773 chapter 34 cautions for wait 34.1 cautions for wait this product has two internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with the low-speed peripheral hardware. because the clock of the cpu bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the cpu conflict s with an access to the peripheral hardware. when accessing the peripheral hardware that may cause a conflict, therefore, the cpu repeatedly executes processing, until the correct data is passed. as a result, the cpu does not start the next instruction processing but waits. if this happens, the number of execution clocks of an instruction increas es by the number of wait clocks (for the number of wait clocks, see tables 34-1 and 34-2 ). this must be noted when real -time processing is performed. chapter 34 cautions for wait user?s manual u18329ej4v0ud 774 34.2 peripheral hardware that generates wait table 34-1 lists the register s that issue a wait request when accessed by the cpu, and the number of cpu wait clocks and table 34-2 lists the ram accesses that issue a wait request and the num ber of cpu wait clocks. table 34-1. registers that generate wait and number of cpu wait clocks peripheral hardware register access number of wait clocks serial interface uart0 asis0 read 1 clock (fixed) serial interface uart6 asis6 read 1 clock (fixed) adm write ads write adpc write adcr read 1 to 5 clocks (when f ad = f prs /2 is selected) 1 to 7 clocks (when f ad = f prs /3 is selected) 1 to 9 clocks (when f ad = f prs /4 is selected) 2 to 13 clocks (when f ad = f prs /6 is selected) 2 to 17 clocks (when f ad = f prs /8 is selected) 2 to 25 clocks (when f ad = f prs /12 is selected) 10-bit successive approximation type a/d converter the above number of clocks is when the same source clock is selected for f cpu and f prs . the number of wait clocks can be calculated by the following expression and under the following conditions. user?s manual u18329ej4v0ud 775 appendix a development tools the following development t ools are available for t he development of systems t hat employ the 78k0/lf3 figure a-1 shows the developm ent tool configuration. ? support for pc98-nx series unless otherwise specified, pr oducts supported by ibm pc/at tm compatibles are compatible with pc98-nx series computers. when using pc98-nx series computer s, refer to the explanation for ibm pc/at compatibles. ? windows tm unless otherwise specified, ?windows? means the following oss. ? windows 98 ? windows nt tm ? windows 2000 ? windows xp appendix a development tools user?s manual u18329ej4v0ud 776 figure a-1. development tool configuration (1/2) (1) when using the in-circu it emulator qb-78k0lx3 language processing software ? assembler package ? c compiler package ? device file note 1 ? c library source file note 2 debugging software ? integrated debugger note 4 host machine (pc or ews) qb-78k0lx3 note 4 emulation probe target system flash memory programmer flash memory write adapter flash memory ? software package ? project manager software package flash memory write environment control software (windows only) note 3 power supply unit note 4 usb interface cable note 4 notes 1. download the device file (df780495) for the 78k0/lf 3 from the download site for development tools ( http://www.necel.com/micro/ods/eng/index.html). 2. the c library source file is not included in the software package. 3. the project manager pm+ is in cluded in the assembler package. the pm+ is only used for windows. 4. the qb-78k0lx3 is supplied with the integrated debugger id78k0-qb, a usb interface cable, a power supply unit, the on-chip debug emulator qb-mini2, c onnection cables (10-pin and 16-pin cables), and the 78k0-ocd board. any other pr oducts are sold separately. download the software for operating the qb-mini2 from the download site for development tools ( http://www.necel.com/micro/ods/eng/ind ex.html) when using the qb-mini2. appendix a development tools user?s manual u18329ej4v0ud 777 figure a-1. development tool configuration (2/2) (2) when using the on-chip debug emulat or with programming function qb-mini2 qb-mini2 note 4 qb-mini2 note 4 78k0-ocd board note 4 language processing software ? assembler package ? c compiler package ? device file note 1 ? c library source file note 2 debugging software ? integrated debugger note 1 host machine (pc or ews) usb interface cable note 4 connection cable (10-pin/16-pin cable) note 4 target connector target system connection cable (16-pin cable) note 4 ? software package ? project manager software package appendix a development tools user?s manual u18329ej4v0ud 778 a.1 software package development tools (software) common to the 78k0 microcontrollers are combined in this package. sp78k0 78k0 microcontroller software package part number: s sp78k0 remark in the part number differs depending on the host machine and os used. s sp78k0 host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom a.2 language processing software this assembler converts programs written in mnemonics into object codes executable with a microcontroller. this assembler is also provided with functi ons capable of automatically creating symbol tables and branch instruction optimization. this assembler should be used in combi nation with a device file (df780495) (sold separately). appendix a development tools user?s manual u18329ej4v0ud 779 remark in the part number differs depending on the host machine and os used. s ra78k0 s cc78k0 s cc78k0-l host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4) solaris tm (rel. 2.5.1) cd-rom s df780495 host machine os supply medium ab13 windows (japanese version) bb13 pc-9800 series, ibm pc/at compatibles windows (english version) 3.5-inch 2hd fd a.3 control software pm+ project manager this is control software designed to enable e fficient user program development in the windows environment. all operations used in development of a user program, such as starting the editor, building, and starting the debugger, can be performed from the project manager. appendix a development tools user?s manual u18329ej4v0ud 780 a.4 flash memory writing tools a.4.1 when using flash memory programmer pg-fp5 and fl-pr5 pg-fp5, fl-pr5 flash memory programmer flash memory programmer dedica ted to microcontrollers with on-chip flash memory. fa-80gc-gad-b fa-78f0495gc-gad-rx fa-80gk-gak-b fa-78f0495gk-gak-rx flash memory writing adapter flash memory writing adapter used conne cted to the flash memory programmer. ? fa-80gc-gad-b, fa-78f0495gc-gad-rx: for 80pin plastic lqfp (gc-gad type) ? fa-80gk-gak-b, fa-78f0495gk-gak-rx: for 80-pin plastic lqfp (gk-gak type) remarks 1. fl-pr5, fa-80gc-gad-b, fa-78f0495gc-ga d-rx, fa-80gk-gak-b, and fa-78f0495gk-gak- rx are products of naito densei machida mfg. co., ltd. tel: +81-42-750-4172 naito densei machida mfg. co., ltd. 2. use the latest version of the flash memory programming adapter. a.4.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this is a flash memory programmer dedicat ed to microcontrollers with on-chip flash memory. it is available also as on-chip debug emulator which serves to debug hardware and software when developing application syst ems using the 78k0/lx3. when using this as flash memory programmer, it should be us ed in combination with a connection cable (16-pin cable) and a usb interface cable that is used to connect the host machine. target connector specific ations 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface cable, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. the connection cable (1 0-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). appendix a development tools user?s manual u18329ej4v0ud 781 a.5 debugging tools (hardware) a.5.1 when using in-circu it emulator qb-78k0lx3 qb-78k0/lx3 in-circuit emulator this in-circuit emulator serves to debug har dware and software when developing application systems using the 78k0/lx3. it supports to the integrated debugger (id78k0-qb). this emulator should be used in combination with a power su pply unit and emulation probe, and the usb is used to connect this emulat or to the host machine. qb-144-ca-01 check pin adapter this check pin adapter is used in waveform monitoring using the oscilloscope, etc. qb-80-ep-01t emulation probe this emulation probe is flexible type and used to connect the in-circuit emulator and target system. qb-80gc-ea-01t, qb-80gk-ea-01t exchange adapter this exchange adapter is used to perform pin conver sion from the in-circuit emulator to target connector. ? qb-80gc-ea-01t: for 80-pin plastic lqfp (gc-gad type) ? qb-80gk-ea-01t: for 80-pin plastic lqfp (gk-gak type) qb-80gc-ys-01t, qb-80gk-ys-01t space adapter this space adapter is used to adjust the height bet ween the target system and in-circuit emulator. ? qb-80gc-ys-01t: for 80-pin plastic lqfp (gc-gad type) ? qb-80gk-ys-01t: for 80-pin plastic lqfp (gk-gak type) qb-80gc-yq-01t, qb-80gk-yq-01t yq connector this yq connector is used to connect the target connector and exchange adapter. ? qb-80gc-yq-01t: for 80-pin plastic lqfp (gc-gad type) ? qb-80gk-yq-01t: for 80-pin plastic lqfp (gk-gak type) qb-80gc-hq-01t, qb-80gk-hq-01t mount adapter this mount adapter is used to mount the target device with socket. ? qb-80gc-hq-01t: for 80-pin plastic lqfp (gc-gad type) ? qb-80gk-hq-01t: for 80-pin plastic lqfp (gk-gak type) qb-80gc-nq-01t, qb-80gk-nq-01t target connector this target connector is used to mount on the target system. ? qb-80gc-nq-01t: for 80-pin plastic lqfp (gc-gad type) ? qb-80gk-nq-01t: for 80-pin plastic lqfp (gk-gak type) remarks 1. the qb-78k0lx3 is supplied with the integrated debugger id78k0-qb, a usb interface cable, a power supply unit, the on-chip debug emulator qb-mini2, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. download the software for operating the qb-mini 2 from the download site for development tools ( http://www.necel.com/micro/ods/eng/ind ex.html) when using the qb-mini2. 2. the packed contents differ depending on the part number, as follows. packed contents part number in-circuit emulator emulation probe exch ange adapter yq connector target connector qb-78k0lx3 -zzz none qb-78k0lx3-t80gc qb-80gc-ea-01t qb-80gc-yq-01t qb-80gc-nq-01t qb-78k0lx3-t80gk qb-78k0lx3 qb-80-ep-01t qb-80gk-ea-01t qb-80gk-yq-01t qb-80gk-nq-01t appendix a development tools user?s manual u18329ej4v0ud 782 a.5.2 when using on-chip debug emul ator with programming function qb-mini2 qb-mini2 on-chip debug emulator with programming function this on-chip debug emulator serves to debug hardware and software when developing application systems using the 78k0/lx3. it is available also as flash memory programmer dedicated to microcontrollers with on-chip fl ash memory. when using this as on-chip debug emulator, it should be used in combination with a connection cable (10-pin ca ble or 16-pin cable), a usb interface cable that is used to con nect the host machine, and the 78k0-ocd board. target connector specifications 10-pin general-purpose connector (2. 54 mm pitch) or 16-pin general-purpose connector (2.54 mm pitch) remarks 1. the qb-mini2 is supplied with a usb interface cable, connection cables (10-pin and 16-pin cables), and the 78k0-ocd board. the connection cable (1 0-pin cable) and the 78k0-ocd board are used only when using the on-chip debug function. 2. download the software for operating the qb-mini2 from the download site for development tools (http://www.necel.com/micro/ods/eng/index.html). a.6 debugging tools (software) this debugger supports the in-circuit emul ators for the 78k0 microcontrollers. the id78k0-qb is a windows-based software. it has improved c-compatible debugging functions and can display the results of tracing with the source program using an integrating window function that associates the source program, disassemble display, and memory di splay with the trace result. it should be used in combination with the device file (sold separately). id78k0-qb integrated debugger part number: s id78k0-qb remark in the part number differs depending on the host machine and os used. s id78k0-qb host machine os supply medium ab17 windows (japanese version) bb17 pc-9800 series, ibm pc/at compatibles windows (english version) cd-rom user?s manual u18329ej4v0ud 783 appendix b revision history b.1 major revisions in this edition (1/3) page description classification throughout ? addition of pg-fp5 and fl-pr5 ? addition of explanation fo r segment key scan function (b, c) chapter 1 outline p. 17 addition of note 2 to table of rom, ram capacities in 1.1 features (d) pp. 20 to 22 addition of remark 2 to 1.4 pin configuration (top view) (c) pp. 25 to 27 addition of note to table of function list in 1.5 78k0/lx3 microcontroller series lineup (c) p. 30 addition of note 4 to 1.7 outline of functions ( pd78f047x) (c) p. 33 addition of note 4 to 1.8 outline of functions ( pd78f048x) (c) p. 36 addition of note 5 to 1.9 outline of functions ( pd78f049x) (c) chapter 3 cpu architecture pp. 59, 61, 63, 65, 67 addition of note 3 to memory map of figure 3-2 , figure 3-4 , figure 3-6 , figure 3-8 , and figure 3-10 (b) pp. 73, 75, 77, 79, 81 addition of note to correspondence between data memory and addressing of figure 3-12 , figure 3-14 , figure 3-16 , figure 3-18 , and figure 3-20 (b) p. 95 change of illustration in 3.3.3 table indirect addressing (c) chapter 4 port functions p. 116 change of figure 4-8. block diagram of p20 to p27 (a) p. 138 change of figure 4-28. format of port register and addition of notes 1, 2 , and 3 (b, c) p. 139 addition of note to figure 4-29. format of pull-up resistor option register (c) chapter 5 clock generator p. 160 change of figure 5-9. format of internal high-speed oscillation trimming register (hiotrm) (b) p. 166 change of figure 5-13. clock generator operation when power supply voltage is turned on (b) p. 167 change of caution 1 in figure 5-14. clock generator operation when power supply voltage is turned on (b) chapter 6 16-bit timer/event counter 00 p. 197 addition of note 2 to figure 6-10. format of input switch control register (isc) (c) p. 232 modification of figure 6-42. (f) 16-bit capture/compare register 000 (cr000) (a) p. 259 addition of 6.6 (12) reading of 16-bit timer counter 00 (tm00) (c) chapter 7 8-bit timer/event counters 50, 51, and 52 p. 270 addition of note 2 to figure 7-12. format of input switch control register (isc) (c) p. 280 change of 7.5 (2) cautions for 16-bit timer/event counter 00 count up during external 24-bit event counter operation (c) p. 281 addition of 7.5 (3) reading of 8-bit timer counter 5n (tm5n) (c) chapter 8 8-bit timers h0, h1, and h2 p. 284 change of figure 8-2. block diagram of 8-bit timer h1 (a) p. 288 change of figure 8-6. format of 8-bit timer h mode register 0 (tmhmd0) (c) p. 310 addition of 8.4.4 control of number of carrier clocks by timer 51 counter (b, c) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): additi on/change of specifications, (c): a ddition/change of description or note, (d): addition/change of package, part number, or ma nagement division, (e): addition/change of related documents appendix b revision history user?s manual u18329ej4v0ud 784 (2/3) page description classification chapter 9 real-time counter p. 316 change of caution in figure 9-4. format of real-time counter control register 1 (rtcc1) (b, c) p. 320 change of table 9-2. displayed time digits (c) p. 322 addition of caution to figure 9-11. format of week count register (week) (c) p. 324 change of (13) watch error correction register (subcud) (c) p. 325 addition of explanation to (15) alarm hour register (alarmwh) (c) p. 327 addition of note to figure 9-18. procedure for starting operation of real-time counter (c) p. 328 addition of 9.4.2 shifting to stop mode after starting operation (c) p. 332 addition of 9.4.5 1 hz output of real-time counter (c) p. 332 addition of 9.4.6 32.768 khz output of real-time counter (c) p. 333 addition of 9.4.7 512 hz, 16.384 khz output of real-time counter (c) p. 334 addition of 9.4.8 example of watch error correction of real-time counter (c) chapter 10 watchdog timer p. 345 change of remark in 10.4.3 setting window open period of watchdog timer (a) chapter 12 10-bit successive approximation type a/d converter ( pd78f048x and 78f049x only) p. 356 change of caution 1 in table 12-2. a/d conversion time selection (c) p. 360 modification of figure 12-9. format of a/d port configuration register 0 (adpc0) (a) p. 372 change of 12.6 (11) internal equivalent circuit (b) chapter 13 16-bit ? type a/d converter ( pd78f049x only) pp. 373 to 396 full-scale revision of chapter (b, c) chapter 14 serial interface uart0 p. 416 change of table 14-5. set data of baud rate generator (b) chapter 18 lcd controller/driver pp. 509 to 570 full-scale revision of chapter (b, c) chapter 20 remote controller receiver pp. 596 to 627 full-scale revision of chapter (b, c) chapter 21 interrupt functions p. 635 change of figure 21-2. format of interrupt request flag registers (if0l, if0h, if1l, if1h) (a) p. 637 change of figure 21-3. format of interrupt mask flag registers (mk0l, mk0h, mk1l, mk1h) (a) p. 638 change of figure 21-4. format of priority specification flag registers (pr0l, pr0h, pr1l, pr1h) (a) chapter 22 key interrupt function p. 649 addition of caution 5 to figure 22-2. format of key return mode register (krm) (c) chapter 23 standby function p. 657 change of figure 23-4. halt mode release by reset (c) pp. 659, 660 change of table 23-3. operating statuses in stop mode , note 2 , and caution 3 and addition of caution 4 (c) p. 663 change of figure 23-7. stop mode release by reset (c) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): additi on/change of specifications, (c): a ddition/change of description or note, (d): addition/change of package, part number, or ma nagement division, (e): addition/change of related documents appendix b revision history user?s manual u18329ej4v0ud 785 (3/3) page description classification chapter 24 reset function p. 666 change of figure 24-2. timing of reset by reset input (c) p. 666 change of figure 24-3. timing of reset due to watchdog timer overflow (c) p. 667 change of figure 24-4. timing of reset in stop mode by reset input (c) chapter 25 power-on-clear circuit p. 676 change of figure 25-2. timing of generation of internal reset signal by power-on-clear circuit and low-voltage detector (1) (b) p. 677 change of caution 2 in figure 25-2. timing of generation of internal reset signal by power- on-clear circuit and low-voltage detector (2) (b, c) chapter 26 low-voltage detector p. 697 change of figure 26-9. example of software processing after reset release (2/2) (c) chapter 28 flash memory p. 705 change of note 2 in and addition of caution to table 28-3. wiring between 78k0/lf3 and dedicated flash memory programmer (c) p. 709 change of note 1 in table 28-4. pin connection (c) p. 712 change of caution 2 in 28.6.6 other signal pins (c) p. 713 change of figure 28-12. flash memory manipulation procedure (b) p. 714 change of table 28-7. communication modes (b) pp. 718 to 720 addition of 28.9 processing time for each command when pg-fp5 is used (reference) (b, c) pp. 721 to 730 revision of 28.10 flash memory programming by self-programming (b, c) chapter 29 on-chip debug function pp. 731, 732 full-scale revision of chapter (c) chapter 31 electrical specifications (standard products) p. 746 addition of caution (c) p. 750 addition of recommended oscillator constants (b) p. 754 change of supply current value and notes 1 , 6 in and addition of note 5 to dc characteristics (b) p. 755 change of ? type a/d converter operating current value in dc characteristics (b) p. 765 change of 16-bit ? type a/d converter characteristics (b) p. 766 change of note 3 in lcd characteristics (b) p. 769 change of basic characteristics in flash memory programming characteristics and addition of notes 1 , 4 (b, c) chapter 33 recommended soldering conditions p. 772 addition of chapter (b, c) appendix a development tools pp. 775 to 782 addition of appendix a (c) remark ?classification? in the above table classifies revisions as follows. (a): error correction, (b): additi on/change of specifications, (c): a ddition/change of description or note, (d): addition/change of package, part number, or ma nagement division, (e): addition/change of related documents appendix b revision history user?s manual u18329ej4v0ud 786 b.2 revision history up to previous editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. (1/3) edition description applied to: addition of note to 1.3 ordering information addition of caution 3 to (1) in 1.4 pin configuration (top view) chapter 1 outline change of table 2-2. pin i/o circuit types chapter 2 pin functions modification of figure 3-9. memory map ( pd78f0475, 78f0485) modification of figure 3-10. memory map ( pd78f0495) chapter 3 cpu architecture modification of figure 4-5. block diagram of p13 modification of figure 4-6. block diagram of p16 modification of figure 4-29. format of pull-up resistor option register change of table 4-5. settings of pfall, pf2, pf1, isc, port mode register, and output latch when using alternate function chapter 4 port functions change of 5.3 (9) internal high-speed oscillation trimming register (hiotrm) addition of explanation to table 5-4. clocks supplied to cpu and peripheral hardware, and register setting addition of explanation to table 5-6. changing cpu clock chapter 5 clock generator ? to00 pin output to00 output ? addition of to00 output in block diagram addition of explanation to figure 6-8 format of 16-bit timer output control register 00 (toc00) addition of notes 1 and 2 to and change of note 3 in figure 6-9 format of prescaler mode register 00 (prm00) change of figure 6-54. configuration diagram of external 24-bit event counter change of figure 6-55. operation timing of external 24-bit event counter chapter 6 16-bit timer/event counter 00 ? to50 pin output to50 output, to51 pin output to51 output ? addition of to50, to51 output in block diagram addition of notes 1 and 2 to figure 7-6 format of timer clock selection register 50 (tcl50) addition of notes 1 and 2 to figure 7-7 format of timer clock selection register 51 (tcl51) addition of notes 1 and 2 to figure 7-8 format of timer clock selection register 52 (tcl52) chenge of caution 3 in and addition of caution 4 to figure 7-9 format of 8-bit timer mode control register 50 (tmc50) and figure 7-10 format of 8-bit timer mode control register 51 (tmc51) chapter 7 8-bit timer/event counters 50, 51, and 52 full-scale revision chapter 8 8-bit timers h0, h1, and h2 2nd edition addition of note 1 to figure 11-2 format of clock output selection register (cks) chapter 11 clock output/buzzer output controller appendix b revision history user?s manual u18329ej4v0ud 787 (2/3) edition description applied to: change of figure 14-1 block diagram of serial interface uart0 addition of note 1 to figure 14-4 format of baud rate generator control register 0 (brgc0) change of 14.3 (5) port mode register 1 (pm1) change of table 14-2. relationship between register settings and pins addition of notes 1 and 2 to table 14-4 set value of tps01 and tps00 chapter 14 serial interface uart0 change of explanation in 15.1 functions of serial interface uart6 change of figure 15-4 block diagram of serial interface uart6 addition of notes 1 and 2 to figure 15-8 format of clock selection register 6 (cksr6) change of 15.3 (9) port mode register 1 (pm1) change of (a) in table 15-2. relationship between register settings and pins addition of notes 1 , 2 , and 3 to table 15-4 set value of tps63 to tps60 chapter 15 serial interface uart6 change of figure 16-1. block diagram of serial interface csi10 addition of notes 1 and 2 to figure 16-3 format of serial clock selection register 10 (csic10) chapter 16 serial interface csi10 change of figure 17-1. block diagram of serial interface csia0 addition of notes 2 and 3 to figure 17-3. format of serial status register 0 (csis0) chapter 17 serial interface csia0 change of note 2 in 18.3 (2) lcd display mode register (lcdm) change of note in 18.4 setting lcd controller/driver chapter 18 lcd controller/driver addition of notes 1 and 2 to figure 19-5. format of mcg control register 1 (mc0ctl1) addition of notes 1 and 2 to 19.4.2 (b) mcg control register 1 (mc0ctl1) chapter 19 manchester code generator change of note 4 in table 21-1. interrupt source list change of note 2 in and addition of notes 4 , 5 , and 6 to table 21-2 flags corresponding to interrupt request sources chapter 21 interrupt functions change of caution 1 in figure 22-2 format of key return mode register (krm) chapter 22 key interrupt function addition of explanation to caution 3 in 23.1.1 standby function chapter 23 standby function change of explanation in 26.3 (1) low-voltage detection register (lvim) addition of notes 1 and 4 and cautions 3 and 4 to figure 26-2 format of low-voltage detection register (lvim) change of explanation in 26.3 (2) low-voltage detection level selection register (lvis) addition of note and caution 4 to figure 26-3 format of low-voltage detection level selection register (lvis) addition of note 3 to figure 26-7 timing of low-voltage detector interrupt signal generation (detects level of supply voltage (v dd )) addition of note 3 to figure 26-8 timing of low-voltage detector interrupt signal generation (detects level of input voltage from external input pin (exlvi)) 2nd edition change of figure 26-9 example of software processing after reset release chapter 26 low- voltage detector appendix b revision history user?s manual u18329ej4v0ud 788 (3/3) edition description applied to: change of and addition of remark to figure 28-17 boot swap function change of figure 28-18 example of executing boot swapping chapter 28 flash memory change to formal spec from target spec chapter 31 electrical specifications (standard products) addition of explanation to table 33-1. registers that generate wait and number of cpu wait clocks change of table 33-2. ram accesses that generate wait and number of cpu wait clocks chapter 33 cautions for wait 2nd edition addition of appendix appendix revision history nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ shanghai branch room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai, p.r.china p.c:200120 tel:021-5888-5400 http://www.cn.necel.com/ shenzhen branch unit 01, 39/f, excellence times square building, no. 4068 yi tian road, futian district, shenzhen, p.r.china p.c:518048 tel:0755-8282-9800 http://www.cn.necel.com/ nec electronics hong kong ltd. unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: 2886-9318 http://www.hk.necel.com/ nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-8175-9600 http://www.tw.necel.com/ nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ nec electronics korea ltd. 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 http://www.kr.necel.com/ for further information, please contact: g0706 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielskistrasse 166 b 30177 hannover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands steijgerweg 6 5616 hs eindhoven the netherlands tel: 040 265 40 10 |
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